Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
155242 |
1 |
|
|
T3 |
207 |
|
T7 |
639 |
|
T8 |
75 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
81125 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
54906 |
1 |
|
|
T3 |
205 |
|
T7 |
16 |
|
T8 |
73 |
seven_bytes |
2756 |
1 |
|
|
T7 |
14 |
|
T19 |
37 |
|
T17 |
22 |
six_bytes |
2706 |
1 |
|
|
T7 |
19 |
|
T19 |
34 |
|
T17 |
22 |
five_bytes |
2782 |
1 |
|
|
T7 |
11 |
|
T19 |
46 |
|
T17 |
21 |
four_bytes |
2741 |
1 |
|
|
T7 |
7 |
|
T19 |
38 |
|
T17 |
19 |
three_bytes |
2728 |
1 |
|
|
T7 |
14 |
|
T19 |
48 |
|
T17 |
21 |
two_bytes |
2728 |
1 |
|
|
T7 |
14 |
|
T19 |
41 |
|
T17 |
15 |
one_byte |
2770 |
1 |
|
|
T7 |
19 |
|
T19 |
30 |
|
T17 |
18 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
152302 |
1 |
|
|
T3 |
203 |
|
T7 |
633 |
|
T8 |
71 |
auto[1] |
2940 |
1 |
|
|
T3 |
4 |
|
T7 |
6 |
|
T8 |
4 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
155242 |
1 |
|
|
T3 |
207 |
|
T7 |
639 |
|
T8 |
75 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
155237 |
1 |
|
|
T3 |
207 |
|
T7 |
639 |
|
T8 |
75 |
auto[1] |
5 |
1 |
|
|
T35 |
1 |
|
T171 |
1 |
|
T172 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1024 |
1 |
|
|
T3 |
2 |
|
T7 |
1 |
|
T8 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2940 |
1 |
|
|
T3 |
4 |
|
T7 |
6 |
|
T8 |
4 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
161981 |
1 |
|
|
T3 |
118 |
|
T7 |
797 |
|
T8 |
124 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
85335 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
56539 |
1 |
|
|
T3 |
115 |
|
T7 |
19 |
|
T8 |
122 |
seven_bytes |
2904 |
1 |
|
|
T7 |
26 |
|
T19 |
39 |
|
T17 |
18 |
six_bytes |
2823 |
1 |
|
|
T7 |
18 |
|
T19 |
40 |
|
T17 |
32 |
five_bytes |
3002 |
1 |
|
|
T7 |
18 |
|
T19 |
33 |
|
T17 |
30 |
four_bytes |
2842 |
1 |
|
|
T7 |
30 |
|
T19 |
44 |
|
T17 |
21 |
three_bytes |
2833 |
1 |
|
|
T7 |
21 |
|
T19 |
38 |
|
T17 |
28 |
two_bytes |
2879 |
1 |
|
|
T7 |
23 |
|
T19 |
36 |
|
T17 |
23 |
one_byte |
2824 |
1 |
|
|
T7 |
26 |
|
T19 |
41 |
|
T17 |
22 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
158912 |
1 |
|
|
T3 |
112 |
|
T7 |
791 |
|
T8 |
120 |
auto[1] |
3069 |
1 |
|
|
T3 |
6 |
|
T7 |
6 |
|
T8 |
4 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
161981 |
1 |
|
|
T3 |
118 |
|
T7 |
797 |
|
T8 |
124 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
161968 |
1 |
|
|
T3 |
118 |
|
T7 |
797 |
|
T8 |
124 |
auto[1] |
13 |
1 |
|
|
T173 |
1 |
|
T174 |
1 |
|
T175 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1040 |
1 |
|
|
T3 |
3 |
|
T8 |
2 |
|
T21 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3069 |
1 |
|
|
T3 |
6 |
|
T7 |
6 |
|
T8 |
4 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
300732 |
1 |
|
|
T3 |
380 |
|
T7 |
919 |
|
T8 |
201 |
auto[1] |
335 |
1 |
|
|
T9 |
73 |
|
T10 |
13 |
|
T11 |
7 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
159743 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
103479 |
1 |
|
|
T3 |
374 |
|
T7 |
28 |
|
T8 |
196 |
seven_bytes |
5328 |
1 |
|
|
T7 |
14 |
|
T19 |
181 |
|
T17 |
51 |
six_bytes |
5491 |
1 |
|
|
T7 |
25 |
|
T19 |
152 |
|
T17 |
57 |
five_bytes |
5405 |
1 |
|
|
T7 |
20 |
|
T19 |
163 |
|
T17 |
55 |
four_bytes |
5377 |
1 |
|
|
T7 |
31 |
|
T19 |
143 |
|
T17 |
55 |
three_bytes |
5526 |
1 |
|
|
T7 |
25 |
|
T19 |
155 |
|
T17 |
70 |
two_bytes |
5342 |
1 |
|
|
T7 |
27 |
|
T19 |
183 |
|
T17 |
52 |
one_byte |
5376 |
1 |
|
|
T7 |
14 |
|
T19 |
159 |
|
T17 |
51 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
295191 |
1 |
|
|
T3 |
368 |
|
T7 |
911 |
|
T8 |
191 |
auto[1] |
5876 |
1 |
|
|
T3 |
12 |
|
T7 |
8 |
|
T8 |
10 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
301067 |
1 |
|
|
T3 |
380 |
|
T7 |
919 |
|
T8 |
201 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
301042 |
1 |
|
|
T3 |
380 |
|
T7 |
919 |
|
T8 |
201 |
auto[1] |
25 |
1 |
|
|
T35 |
1 |
|
T9 |
3 |
|
T173 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2018 |
1 |
|
|
T3 |
6 |
|
T7 |
2 |
|
T8 |
5 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
5876 |
1 |
|
|
T3 |
12 |
|
T7 |
8 |
|
T8 |
10 |