Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

42392322

1

T1

19

T2

16

T3

20778

full_word

43127688

1

T1

5

T2

203

T3

29291

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	85519690	1			T1	24		T2	219		T3	50069
auto[TlIntgErrCmd]	101	1			T125	8		T126	3		T127	4
auto[TlIntgErrData]	100	1			T125	4		T126	5		T127	11
auto[TlIntgErrBoth]	119	1			T125	8		T126	2		T127	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47528510

1

T1

1

T2

78

T3

32845

auto[1]

37991500

1

T1

23

T2

141

T3

17224

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	28530443	1			T2	7		T3	13415		T16	311846
auto[TlIntgErrNone]	partial	auto[1]	13861591	1			T1	19		T2	9		T3	7363
auto[TlIntgErrNone]	full_word	auto[0]	18997926	1			T1	1		T2	71		T3	19430
auto[TlIntgErrNone]	full_word	auto[1]	24129730	1			T1	4		T2	132		T3	9861
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T125	3		T127	3		T176	1
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T125	5		T126	2		T127	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T179	1		T181	1		T182	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T126	1		T183	2		T184	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T125	2		T126	2		T127	6
auto[TlIntgErrData]	partial	auto[1]	50	1			T125	2		T126	3		T127	4
auto[TlIntgErrData]	full_word	auto[0]	4	1			T127	1		T184	1		T185	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T179	2		T183	1		T181	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T125	2		T126	2		T127	3
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T125	5		T176	7		T179	4
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T125	1		T127	1		T180	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T127	1		T176	1		T177	1