Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	518339219	53710	0	0
RunThenComplete_M	518339219	667071	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518339219	53710	0	0
T3	502257	58	0	0
T7	179837	24	0	0
T8	140033	170	0	0
T12	4111	0	0	0
T16	881015	100	0	0
T20	179276	164	0	0
T30	101359	69	0	0
T31	351192	337	0	0
T32	538517	273	0	0
T33	150544	167	0	0
T38	0	20	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	518339219	667071	0	0
T3	502257	310	0	0
T7	179837	133	0	0
T8	140033	947	0	0
T12	4111	0	0	0
T16	881015	5250	0	0
T20	179276	867	0	0
T30	101359	2507	0	0
T31	351192	507	0	0
T32	538517	411	0	0
T33	150544	899	0	0
T38	0	119	0	0