Unified Coverage Report :: Module :: prim_packer

Module : prim_packer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	100.00			92.31	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_msgfifo.u_packer	98.08	100.00	100.00			92.31	100.00

---

Module Instance : tb.dut.u_msgfifo.u_packer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	100.00			92.31	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.41	100.00	100.00	89.74		92.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.21	100.00			100.00	92.86	100.00	u_msgfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_pos_dupcnt.u_pos	89.74			89.74

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_packer

	Line No.	Total	Covered	Percent
TOTAL		62	62	100.00
ALWAYS	65	3	3	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	110	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
ALWAYS	120	3	3	100.00
ALWAYS	157	4	4	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
ALWAYS	185	9	9	100.00
ALWAYS	214	8	8	100.00
ALWAYS	235	3	3	100.00
ALWAYS	243	14	14	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	291	0	0
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	296	1	1	100.00
CONT_ASSIGN	299	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
66	1	1
67	1	1
72	1	1
110	1	1
111	1	1
112	1	1
115	1	1
120	1	1
122	1	1
124	1	1
			MISSING_ELSE
157	1	1
158	1	1
159	1	1
160	1	1
			MISSING_ELSE
165	1	1
166	1	1
170	1	1
171	1	1
174	1	1
175	1	1
178	1	1
180	1	1
185	1	1
187	1	1
188	1	1
192	1	1
193	1	1
197	1	1
198	1	1
202	1	1
203	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
221	1	1
222	1	1
235	1	1
236	1	1
238	1	1
243	1	1
245	1	1
246	1	1
248	1	1
250	1	1
251	1	1
253	1	1
258	1	1
259	1	1
261	1	1
262	1	1
264	1	1
266	1	1
267	1	1
279	1	1
283	1	1
291		unreachable
294	1	1
295	1	1
296	1	1
299		unreachable

---

Cond Coverage for Module : prim_packer

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       110
 EXPRESSION (ack_in && ((!ack_out)))
             ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T2,T3,T16

 LINE       111
 EXPRESSION (((!ack_in)) && ack_out)
             -----1-----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T16,T7

 LINE       112
 EXPRESSION (ack_in && ack_out)
             ---1--    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T16,T7
1	0	Covered	T2,T3,T16
1	1	Covered	T3,T7,T8

 LINE       115
 EXPRESSION (g_pos_dupcnt.cnt_incr_en ? (8'(inmask_ones)) : (8'(OutW)))
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T16

 LINE       159
 EXPRESSION (mask_i[i] == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T16

 LINE       165
 EXPRESSION (valid_i & ready_o)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable	T7,T8,T19
1	1	Covered	T2,T3,T16

 LINE       166
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T54
1	1	Covered	T3,T16,T7

 LINE       170
 EXPRESSION (valid_i ? ((data_i >> lod_idx)) : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T16

 LINE       171
 EXPRESSION (valid_i ? ((mask_i >> lod_idx)) : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T16

 LINE       258
 EXPRESSION (pos_q == '0)
            ------1------

-1-	Status	Tests
0	Covered	T3,T16,T7
1	Covered	T3,T16,T7

 LINE       283
 EXPRESSION ((int'(pos_q) >= OutW) ? 1'b1 : flush_valid)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable	T3,T16,T7

---

Branch Coverage for Module : prim_packer

	Line No.	Total	Covered	Percent
Branches		26	24	92.31
TERNARY	170	2	2	100.00
TERNARY	171	2	2	100.00
TERNARY	283	1	1	100.00
TERNARY	115	2	2	100.00
IF	159	2	2	100.00
CASE	185	5	4	80.00
IF	214	3	3	100.00
IF	235	2	2	100.00
CASE	248	5	4	80.00
IF	122	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	170	(valid_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	171	(valid_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	283	((int'(pos_q) >= OutW)) ? 

Branches:

-1-	Status	Tests
1	Unreachable	T3,T16,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	(g_pos_dupcnt.cnt_incr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	159	if ((mask_i[i] == 1'b1))

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	185	case ({ack_in, ack_out})

Branches:

-1-	Status	Tests
2'b00	Covered	T1,T2,T3
2'b01	Covered	T3,T16,T7
2'b10	Covered	T2,T3,T16
2'b11	Covered	T3,T7,T8
default	Not Covered

	LineNo.	Expression
-1-:	214	if ((!rst_ni))
-2-:	217	if (flush_done)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T16,T7
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	235	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	248	case (flush_st)
-2-:	250	if (flush_i)
-3-:	258	if ((pos_q == '0))

Branches:

-1-	-2-	-3-	Status	Tests
FlushIdle	1	-	Covered	T3,T16,T7
FlushIdle	0	-	Covered	T1,T2,T3
FlushSend	-	1	Covered	T3,T16,T7
FlushSend	-	0	Covered	T3,T16,T7
default	-	-	Not Covered

	LineNo.	Expression
-1-:	122	if ((pos_with_input > 8'(OutW)))

Branches:

-1-	Status	Tests
1	Covered	T3,T16,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_packer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	28	28	100.00	28	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	28	28	100.00	28	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataIStable_M	518339219	399150	0	661
DataOStableWhenPending_A	518339219	622029	0	661
ExFlushValid_M	518339219	53719	0	0
ExcessiveDataStored_A	518339219	42550	0	0
ExcessiveMaskStored_A	518339219	42550	0	0
FlushFollowedByDone_A	518339219	53719	0	661
ValidIDeassertedOnFlush_M	518339219	104764	0	0
ValidOAssertedForStoredDataGTEOutW_A	518339219	10907941	0	0
ValidOPairedWidthReadyI_A	518339219	622029	0	0
g_byte_assert.InputDividedBy8_A	661	661	0	0
g_byte_assert.OutputDividedBy8_A	661	661	0	0
g_byte_assert.g_byte_input_masking[0].InputMaskContiguous_A	518339219	22748686	0	0
g_byte_assert.g_byte_input_masking[1].InputMaskContiguous_A	518339219	22748686	0	0
g_byte_assert.g_byte_input_masking[2].InputMaskContiguous_A	518339219	22748686	0	0
g_byte_assert.g_byte_input_masking[3].InputMaskContiguous_A	518339219	22748686	0	0
g_byte_assert.g_byte_input_masking[4].InputMaskContiguous_A	518339219	22748686	0	0
g_byte_assert.g_byte_input_masking[5].InputMaskContiguous_A	518339219	22748686	0	0
g_byte_assert.g_byte_input_masking[6].InputMaskContiguous_A	518339219	22748686	0	0
g_byte_assert.g_byte_input_masking[7].InputMaskContiguous_A	518339219	22748686	0	0
g_byte_assert.g_byte_output_masking[0].OutputMaskContiguous_A	518339219	10953496	0	0
g_byte_assert.g_byte_output_masking[1].OutputMaskContiguous_A	518339219	10953496	0	0
g_byte_assert.g_byte_output_masking[2].OutputMaskContiguous_A	518339219	10953496	0	0
g_byte_assert.g_byte_output_masking[3].OutputMaskContiguous_A	518339219	10953496	0	0
g_byte_assert.g_byte_output_masking[4].OutputMaskContiguous_A	518339219	10953496	0	0
g_byte_assert.g_byte_output_masking[5].OutputMaskContiguous_A	518339219	10953496	0	0
g_byte_assert.g_byte_output_masking[6].OutputMaskContiguous_A	518339219	10953496	0	0
g_byte_assert.g_byte_output_masking[7].OutputMaskContiguous_A	518339219	10953496	0	0
gen_mask_assert.ContiguousOnesMask_M	518339219	22748686	0	0

DataIStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	518339219	399150	0	661
T7	179837	2298	0	1
T8	140033	1590	0	1
T12	4111	0	0	1
T14	0	7567	0	0
T17	0	1757	0	0
T18	0	1322	0	0
T19	0	15	0	0
T20	179276	0	0	1
T21	765661	0	0	1
T30	101359	0	0	1
T31	351192	0	0	1
T32	538517	0	0	1
T33	150544	0	0	1
T38	227994	0	0	1
T55	0	14	0	0
T60	0	2	0	0
T93	0	8644	0	0
T94	0	3101	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518339219	622029	0	661
T7	179837	2045	0	1
T8	140033	1688	0	1
T12	4111	0	0	1
T14	0	14205	0	0
T17	0	1499	0	0
T18	0	1322	0	0
T20	179276	0	0	1
T21	765661	0	0	1
T30	101359	0	0	1
T31	351192	0	0	1
T32	538517	0	0	1
T33	150544	0	0	1
T38	227994	0	0	1
T49	0	408	0	0
T54	0	10789	0	0
T61	0	17353	0	0
T93	0	8789	0	0
T94	0	3199	0	0

ExFlushValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	518339219	53719	0	0
T3	502257	58	0	0
T7	179837	24	0	0
T8	140033	170	0	0
T12	4111	0	0	0
T16	881015	100	0	0
T20	179276	164	0	0
T30	101359	69	0	0
T31	351192	337	0	0
T32	538517	273	0	0
T33	150544	167	0	0
T38	0	20	0	0

ExcessiveDataStored_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518339219	42550	0	0
T3	502257	6	0	0
T7	179837	110	0	0
T8	140033	185	0	0
T12	4111	0	0	0
T16	881015	0	0	0
T17	0	107	0	0
T18	0	181	0	0
T19	0	4	0	0
T20	179276	0	0	0
T30	101359	0	0	0
T31	351192	0	0	0
T32	538517	0	0	0
T33	150544	0	0	0
T34	0	6	0	0
T35	0	37	0	0
T55	0	3	0	0
T95	0	3	0	0

ExcessiveMaskStored_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518339219	42550	0	0
T3	502257	6	0	0
T7	179837	110	0	0
T8	140033	185	0	0
T12	4111	0	0	0
T16	881015	0	0	0
T17	0	107	0	0
T18	0	181	0	0
T19	0	4	0	0
T20	179276	0	0	0
T30	101359	0	0	0
T31	351192	0	0	0
T32	538517	0	0	0
T33	150544	0	0	0
T34	0	6	0	0
T35	0	37	0	0
T55	0	3	0	0
T95	0	3	0	0

FlushFollowedByDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518339219	53719	0	661
T3	502257	58	0	1
T7	179837	24	0	1
T8	140033	170	0	1
T12	4111	0	0	1
T16	881015	100	0	1
T20	179276	164	0	1
T30	101359	69	0	1
T31	351192	337	0	1
T32	538517	273	0	1
T33	150544	167	0	1
T38	0	20	0	0

ValidIDeassertedOnFlush_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	518339219	104764	0	0
T3	502257	99	0	0
T7	179837	42	0	0
T8	140033	415	0	0
T12	4111	0	0	0
T16	881015	188	0	0
T20	179276	309	0	0
T30	101359	131	0	0
T31	351192	631	0	0
T32	538517	511	0	0
T33	150544	315	0	0
T38	0	40	0	0

ValidOAssertedForStoredDataGTEOutW_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518339219	10907941	0	0
T3	502257	3816	0	0
T7	179837	3703	0	0
T8	140033	12129	0	0
T12	4111	1	0	0
T16	881015	88138	0	0
T20	179276	10405	0	0
T30	101359	45703	0	0
T31	351192	6930	0	0
T32	538517	4522	0	0
T33	150544	10359	0	0

ValidOPairedWidthReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518339219	622029	0	0
T7	179837	2045	0	0
T8	140033	1688	0	0
T12	4111	0	0	0
T14	0	14205	0	0
T17	0	1499	0	0
T18	0	1322	0	0
T20	179276	0	0	0
T21	765661	0	0	0
T30	101359	0	0	0
T31	351192	0	0	0
T32	538517	0	0	0
T33	150544	0	0	0
T38	227994	0	0	0
T49	0	408	0	0
T54	0	10789	0	0
T61	0	17353	0	0
T93	0	8789	0	0
T94	0	3199	0	0

g_byte_assert.InputDividedBy8_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	661	661	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T16	1	1	0	0
T20	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0

g_byte_assert.OutputDividedBy8_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	661	661	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T16	1	1	0	0
T20	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0

g_byte_assert.g_byte_input_masking[0].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518339219	22748686	0	0
T2	3464	1	0	0
T3	502257	7868	0	0
T7	179837	6301	0	0
T8	140033	25966	0	0
T12	4111	3	0	0
T16	881015	207537	0	0
T20	179276	24750	0	0
T30	101359	91659	0	0
T31	351192	16718	0	0
T32	538517	10929	0	0

g_byte_assert.g_byte_input_masking[1].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518339219	22748686	0	0
T2	3464	1	0	0
T3	502257	7868	0	0
T7	179837	6301	0	0
T8	140033	25966	0	0
T12	4111	3	0	0
T16	881015	207537	0	0
T20	179276	24750	0	0
T30	101359	91659	0	0
T31	351192	16718	0	0
T32	538517	10929	0	0

g_byte_assert.g_byte_input_masking[2].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518339219	22748686	0	0
T2	3464	1	0	0
T3	502257	7868	0	0
T7	179837	6301	0	0
T8	140033	25966	0	0
T12	4111	3	0	0
T16	881015	207537	0	0
T20	179276	24750	0	0
T30	101359	91659	0	0
T31	351192	16718	0	0
T32	538517	10929	0	0

g_byte_assert.g_byte_input_masking[3].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518339219	22748686	0	0
T2	3464	1	0	0
T3	502257	7868	0	0
T7	179837	6301	0	0
T8	140033	25966	0	0
T12	4111	3	0	0
T16	881015	207537	0	0
T20	179276	24750	0	0
T30	101359	91659	0	0
T31	351192	16718	0	0
T32	538517	10929	0	0

g_byte_assert.g_byte_input_masking[4].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518339219	22748686	0	0
T2	3464	1	0	0
T3	502257	7868	0	0
T7	179837	6301	0	0
T8	140033	25966	0	0
T12	4111	3	0	0
T16	881015	207537	0	0
T20	179276	24750	0	0
T30	101359	91659	0	0
T31	351192	16718	0	0
T32	538517	10929	0	0

g_byte_assert.g_byte_input_masking[5].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518339219	22748686	0	0
T2	3464	1	0	0
T3	502257	7868	0	0
T7	179837	6301	0	0
T8	140033	25966	0	0
T12	4111	3	0	0
T16	881015	207537	0	0
T20	179276	24750	0	0
T30	101359	91659	0	0
T31	351192	16718	0	0
T32	538517	10929	0	0

g_byte_assert.g_byte_input_masking[6].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518339219	22748686	0	0
T2	3464	1	0	0
T3	502257	7868	0	0
T7	179837	6301	0	0
T8	140033	25966	0	0
T12	4111	3	0	0
T16	881015	207537	0	0
T20	179276	24750	0	0
T30	101359	91659	0	0
T31	351192	16718	0	0
T32	538517	10929	0	0

g_byte_assert.g_byte_input_masking[7].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518339219	22748686	0	0
T2	3464	1	0	0
T3	502257	7868	0	0
T7	179837	6301	0	0
T8	140033	25966	0	0
T12	4111	3	0	0
T16	881015	207537	0	0
T20	179276	24750	0	0
T30	101359	91659	0	0
T31	351192	16718	0	0
T32	538517	10929	0	0

g_byte_assert.g_byte_output_masking[0].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518339219	10953496	0	0
T3	502257	3857	0	0
T7	179837	3721	0	0
T8	140033	12277	0	0
T12	4111	1	0	0
T16	881015	88226	0	0
T20	179276	10550	0	0
T30	101359	45765	0	0
T31	351192	7224	0	0
T32	538517	4760	0	0
T33	150544	10507	0	0

g_byte_assert.g_byte_output_masking[1].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518339219	10953496	0	0
T3	502257	3857	0	0
T7	179837	3721	0	0
T8	140033	12277	0	0
T12	4111	1	0	0
T16	881015	88226	0	0
T20	179276	10550	0	0
T30	101359	45765	0	0
T31	351192	7224	0	0
T32	538517	4760	0	0
T33	150544	10507	0	0

g_byte_assert.g_byte_output_masking[2].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518339219	10953496	0	0
T3	502257	3857	0	0
T7	179837	3721	0	0
T8	140033	12277	0	0
T12	4111	1	0	0
T16	881015	88226	0	0
T20	179276	10550	0	0
T30	101359	45765	0	0
T31	351192	7224	0	0
T32	538517	4760	0	0
T33	150544	10507	0	0

g_byte_assert.g_byte_output_masking[3].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518339219	10953496	0	0
T3	502257	3857	0	0
T7	179837	3721	0	0
T8	140033	12277	0	0
T12	4111	1	0	0
T16	881015	88226	0	0
T20	179276	10550	0	0
T30	101359	45765	0	0
T31	351192	7224	0	0
T32	538517	4760	0	0
T33	150544	10507	0	0

g_byte_assert.g_byte_output_masking[4].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518339219	10953496	0	0
T3	502257	3857	0	0
T7	179837	3721	0	0
T8	140033	12277	0	0
T12	4111	1	0	0
T16	881015	88226	0	0
T20	179276	10550	0	0
T30	101359	45765	0	0
T31	351192	7224	0	0
T32	538517	4760	0	0
T33	150544	10507	0	0

g_byte_assert.g_byte_output_masking[5].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518339219	10953496	0	0
T3	502257	3857	0	0
T7	179837	3721	0	0
T8	140033	12277	0	0
T12	4111	1	0	0
T16	881015	88226	0	0
T20	179276	10550	0	0
T30	101359	45765	0	0
T31	351192	7224	0	0
T32	538517	4760	0	0
T33	150544	10507	0	0

g_byte_assert.g_byte_output_masking[6].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518339219	10953496	0	0
T3	502257	3857	0	0
T7	179837	3721	0	0
T8	140033	12277	0	0
T12	4111	1	0	0
T16	881015	88226	0	0
T20	179276	10550	0	0
T30	101359	45765	0	0
T31	351192	7224	0	0
T32	538517	4760	0	0
T33	150544	10507	0	0

g_byte_assert.g_byte_output_masking[7].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518339219	10953496	0	0
T3	502257	3857	0	0
T7	179837	3721	0	0
T8	140033	12277	0	0
T12	4111	1	0	0
T16	881015	88226	0	0
T20	179276	10550	0	0
T30	101359	45765	0	0
T31	351192	7224	0	0
T32	538517	4760	0	0
T33	150544	10507	0	0

gen_mask_assert.ContiguousOnesMask_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	518339219	22748686	0	0
T2	3464	1	0	0
T3	502257	7868	0	0
T7	179837	6301	0	0
T8	140033	25966	0	0
T12	4111	3	0	0
T16	881015	207537	0	0
T20	179276	24750	0	0
T30	101359	91659	0	0
T31	351192	16718	0	0
T32	538517	10929	0	0