Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	519724534	51707728	0	0
DepthKnown_A	519724534	519515599	0	0
RvalidKnown_A	519724534	519515599	0	0
WreadyKnown_A	519724534	519515599	0	0
gen_passthru_fifo.paramCheckPass	876	876	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519724534	51707728	0	0
T1	1192	24	0	0
T2	3464	128	0	0
T3	502257	27237	0	0
T7	179837	6695	0	0
T8	140033	99418	0	0
T16	881015	624884	0	0
T20	179276	90704	0	0
T30	101359	26088	0	0
T31	351192	55766	0	0
T32	538517	37313	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519724534	519515599	0	0
T1	1192	1113	0	0
T2	3464	3346	0	0
T3	502257	502181	0	0
T7	179837	179782	0	0
T8	140033	140025	0	0
T16	881015	881005	0	0
T20	179276	179267	0	0
T30	101359	101353	0	0
T31	351192	351112	0	0
T32	538517	538432	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519724534	519515599	0	0
T1	1192	1113	0	0
T2	3464	3346	0	0
T3	502257	502181	0	0
T7	179837	179782	0	0
T8	140033	140025	0	0
T16	881015	881005	0	0
T20	179276	179267	0	0
T30	101359	101353	0	0
T31	351192	351112	0	0
T32	538517	538432	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519724534	519515599	0	0
T1	1192	1113	0	0
T2	3464	3346	0	0
T3	502257	502181	0	0
T7	179837	179782	0	0
T8	140033	140025	0	0
T16	881015	881005	0	0
T20	179276	179267	0	0
T30	101359	101353	0	0
T31	351192	351112	0	0
T32	538517	538432	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T16	1	1	0	0
T20	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	519724534	85615298	0	0
DepthKnown_A	519724534	519515599	0	0
RvalidKnown_A	519724534	519515599	0	0
WreadyKnown_A	519724534	519515599	0	0
gen_passthru_fifo.paramCheckPass	876	876	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519724534	85615298	0	0
T1	1192	50	0	0
T2	3464	128	0	0
T3	502257	27237	0	0
T7	179837	6695	0	0
T8	140033	99418	0	0
T16	881015	281210	0	0
T20	179276	412609	0	0
T30	101359	26088	0	0
T31	351192	55766	0	0
T32	538517	37313	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519724534	519515599	0	0
T1	1192	1113	0	0
T2	3464	3346	0	0
T3	502257	502181	0	0
T7	179837	179782	0	0
T8	140033	140025	0	0
T16	881015	881005	0	0
T20	179276	179267	0	0
T30	101359	101353	0	0
T31	351192	351112	0	0
T32	538517	538432	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519724534	519515599	0	0
T1	1192	1113	0	0
T2	3464	3346	0	0
T3	502257	502181	0	0
T7	179837	179782	0	0
T8	140033	140025	0	0
T16	881015	881005	0	0
T20	179276	179267	0	0
T30	101359	101353	0	0
T31	351192	351112	0	0
T32	538517	538432	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519724534	519515599	0	0
T1	1192	1113	0	0
T2	3464	3346	0	0
T3	502257	502181	0	0
T7	179837	179782	0	0
T8	140033	140025	0	0
T16	881015	881005	0	0
T20	179276	179267	0	0
T30	101359	101353	0	0
T31	351192	351112	0	0
T32	538517	538432	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T16	1	1	0	0
T20	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0