Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	519724534	14701	0	0
entropy_period_rd_A	519724534	1677	0	0
intr_enable_rd_A	519724534	2065	0	0
prefix_0_rd_A	519724534	1580	0	0
prefix_10_rd_A	519724534	1604	0	0
prefix_1_rd_A	519724534	1605	0	0
prefix_2_rd_A	519724534	1670	0	0
prefix_3_rd_A	519724534	1477	0	0
prefix_4_rd_A	519724534	1512	0	0
prefix_5_rd_A	519724534	1514	0	0
prefix_6_rd_A	519724534	1511	0	0
prefix_7_rd_A	519724534	1562	0	0
prefix_8_rd_A	519724534	1679	0	0
prefix_9_rd_A	519724534	1495	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519724534	14701	0	0
T15	180782	1609	0	0
T39	2839	0	0	0
T49	192530	1818	0	0
T50	0	1860	0	0
T61	111471	0	0	0
T94	451760	0	0	0
T126	0	2	0	0
T131	0	1539	0	0
T132	0	4784	0	0
T133	0	204	0	0
T134	0	175	0	0
T135	0	1	0	0
T136	0	150	0	0
T137	57419	0	0	0
T138	20798	0	0	0
T139	740908	0	0	0
T140	85872	0	0	0
T141	10142	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519724534	1677	0	0
T125	22334	133	0	0
T126	11511	33	0	0
T135	5032	25	0	0
T149	5780	26	0	0
T150	5401	6	0	0
T151	1926	9	0	0
T152	11134	32	0	0
T153	2661	8	0	0
T154	4647	18	0	0
T155	7477	10	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519724534	2065	0	0
T125	22334	216	0	0
T126	11511	16	0	0
T135	5032	5	0	0
T149	5780	28	0	0
T151	1926	11	0	0
T152	11134	14	0	0
T153	2661	7	0	0
T154	4647	6	0	0
T156	1787	9	0	0
T157	863	7	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519724534	1580	0	0
T125	22334	89	0	0
T126	11511	22	0	0
T135	5032	10	0	0
T149	5780	9	0	0
T150	5401	8	0	0
T151	1926	5	0	0
T152	11134	5	0	0
T153	2661	9	0	0
T154	4647	10	0	0
T156	1787	3	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519724534	1604	0	0
T125	22334	80	0	0
T126	11511	23	0	0
T135	5032	8	0	0
T149	5780	3	0	0
T150	5401	14	0	0
T151	1926	1	0	0
T152	11134	15	0	0
T153	2661	4	0	0
T154	4647	10	0	0
T156	1787	9	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519724534	1605	0	0
T125	22334	92	0	0
T126	11511	30	0	0
T135	5032	11	0	0
T150	5401	14	0	0
T151	1926	1	0	0
T152	11134	12	0	0
T153	2661	3	0	0
T154	4647	9	0	0
T155	7477	5	0	0
T156	1787	5	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519724534	1670	0	0
T125	22334	71	0	0
T126	11511	21	0	0
T135	5032	12	0	0
T149	5780	30	0	0
T150	5401	37	0	0
T152	11134	31	0	0
T153	2661	3	0	0
T154	4647	7	0	0
T155	7477	3	0	0
T158	6394	51	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519724534	1477	0	0
T125	22334	80	0	0
T126	11511	27	0	0
T135	5032	2	0	0
T149	5780	11	0	0
T150	5401	4	0	0
T151	1926	3	0	0
T152	11134	15	0	0
T153	2661	4	0	0
T154	4647	2	0	0
T156	1787	4	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519724534	1512	0	0
T125	22334	77	0	0
T126	11511	16	0	0
T135	5032	2	0	0
T149	5780	13	0	0
T150	5401	13	0	0
T151	1926	6	0	0
T152	11134	17	0	0
T153	2661	7	0	0
T154	4647	1	0	0
T156	1787	5	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519724534	1514	0	0
T125	22334	96	0	0
T126	11511	28	0	0
T135	5032	6	0	0
T149	5780	4	0	0
T150	5401	10	0	0
T151	1926	2	0	0
T152	11134	10	0	0
T153	2661	8	0	0
T154	4647	11	0	0
T156	1787	9	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519724534	1511	0	0
T125	22334	101	0	0
T126	11511	10	0	0
T135	5032	10	0	0
T150	5401	10	0	0
T151	1926	7	0	0
T152	11134	28	0	0
T153	2661	8	0	0
T154	4647	8	0	0
T155	7477	10	0	0
T156	1787	1	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519724534	1562	0	0
T125	22334	71	0	0
T126	11511	15	0	0
T135	5032	7	0	0
T149	5780	12	0	0
T150	5401	16	0	0
T151	1926	3	0	0
T152	11134	1	0	0
T153	2661	1	0	0
T154	4647	13	0	0
T156	1787	1	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519724534	1679	0	0
T125	22334	101	0	0
T126	11511	17	0	0
T135	5032	6	0	0
T149	5780	43	0	0
T150	5401	18	0	0
T151	1926	8	0	0
T152	11134	18	0	0
T153	2661	8	0	0
T154	4647	11	0	0
T156	1787	9	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519724534	1495	0	0
T125	22334	77	0	0
T126	11511	36	0	0
T135	5032	2	0	0
T149	5780	10	0	0
T150	5401	11	0	0
T151	1926	4	0	0
T152	11134	17	0	0
T154	4647	11	0	0
T155	7477	5	0	0
T156	1787	8	0	0