Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	343	1			T2	1		T3	5		T9	7
all_pins[1]	343	1			T2	1		T3	5		T9	7
all_pins[2]	343	1			T2	1		T3	5		T9	7

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	826	1			T2	3		T3	11		T9	15
values[0x1]	203	1			T3	4		T9	6		T10	7
transitions[0x0=>0x1]	138	1			T3	3		T9	3		T10	5
transitions[0x1=>0x0]	145	1			T3	3		T9	4		T10	5

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	274	1			T2	1		T3	5		T9	6
all_pins[0]	values[0x1]	69	1			T9	1		T10	4		T11	1
all_pins[0]	transitions[0x0=>0x1]	44	1			T10	2		T11	1		T65	1
all_pins[0]	transitions[0x1=>0x0]	43	1			T3	1		T9	2		T10	1
all_pins[1]	values[0x0]	275	1			T2	1		T3	4		T9	4
all_pins[1]	values[0x1]	68	1			T3	1		T9	3		T10	3
all_pins[1]	transitions[0x0=>0x1]	50	1			T9	2		T10	3		T11	2
all_pins[1]	transitions[0x1=>0x0]	48	1			T3	2		T9	1		T11	1
all_pins[2]	values[0x0]	277	1			T2	1		T3	2		T9	5
all_pins[2]	values[0x1]	66	1			T3	3		T9	2		T11	3
all_pins[2]	transitions[0x0=>0x1]	44	1			T3	3		T9	1		T11	3
all_pins[2]	transitions[0x1=>0x0]	54	1			T9	1		T10	4		T11	1