Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
42.68	33.14	54.83	11.73	0.00	37.28	100.00	61.76

Total tests in report: 215

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
38.06	38.06	32.72	32.72	49.87	49.87	11.20	11.20	0.00	0.00	36.74	36.74	92.11	92.11	43.77	43.77	/workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.1512303341
39.40	1.34	32.78	0.06	51.52	1.65	11.25	0.06	0.00	0.00	36.98	0.24	93.95	1.84	49.29	5.52	/workspace/coverage/cover_reg_top/2.kmac_tl_errors.2044399917
40.43	1.04	32.95	0.17	51.94	0.42	11.31	0.06	0.00	0.00	37.10	0.12	94.21	0.26	55.52	6.23	/workspace/coverage/cover_reg_top/14.kmac_intr_test.1863986005
41.37	0.93	32.95	0.00	52.85	0.91	11.40	0.09	0.00	0.00	37.22	0.12	97.37	3.16	57.79	2.27	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3358057998
41.74	0.38	32.95	0.00	53.56	0.71	12.26	0.86	0.00	0.00	37.28	0.06	97.37	0.00	58.78	0.99	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2660177365
42.04	0.30	32.95	0.00	53.56	0.00	12.26	0.00	0.00	0.00	37.28	0.00	99.47	2.11	58.78	0.00	/workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.2697022926
42.26	0.21	32.95	0.00	54.05	0.49	12.26	0.00	0.00	0.00	37.28	0.00	99.47	0.00	59.77	0.99	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.3030385306
42.38	0.12	33.14	0.19	54.57	0.52	12.26	0.00	0.00	0.00	37.28	0.00	99.47	0.00	59.92	0.14	/workspace/coverage/cover_reg_top/10.kmac_tl_errors.2371078673
42.48	0.10	33.14	0.00	54.57	0.00	12.26	0.00	0.00	0.00	37.28	0.00	99.47	0.00	60.62	0.71	/workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.4066136727
42.58	0.10	33.14	0.00	54.57	0.00	12.26	0.00	0.00	0.00	37.28	0.00	99.74	0.26	61.05	0.42	/workspace/coverage/cover_reg_top/13.kmac_intr_test.1830665227
42.66	0.08	33.14	0.00	54.57	0.00	12.26	0.00	0.00	0.00	37.28	0.00	99.74	0.00	61.61	0.57	/workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.1046122250
42.69	0.04	33.14	0.00	54.57	0.00	12.26	0.00	0.00	0.00	37.28	0.00	100.00	0.26	61.61	0.00	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.675743657
42.73	0.03	33.14	0.00	54.79	0.23	12.26	0.00	0.00	0.00	37.28	0.00	100.00	0.00	61.61	0.00	/workspace/coverage/cover_reg_top/13.kmac_tl_errors.1454114329
42.75	0.02	33.14	0.00	54.79	0.00	12.26	0.00	0.00	0.00	37.28	0.00	100.00	0.00	61.76	0.14	/workspace/coverage/cover_reg_top/1.kmac_intr_test.1251382029
42.77	0.02	33.14	0.00	54.79	0.00	12.39	0.13	0.00	0.00	37.28	0.00	100.00	0.00	61.76	0.00	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.3641133203
42.77	0.01	33.14	0.00	54.83	0.03	12.39	0.00	0.00	0.00	37.28	0.00	100.00	0.00	61.76	0.00	/workspace/coverage/cover_reg_top/11.kmac_tl_errors.998196234
42.77	0.01	33.14	0.00	54.83	0.00	12.40	0.01	0.00	0.00	37.28	0.00	100.00	0.00	61.76	0.00	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1358702106

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.2001097646
/workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.913099174
/workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1679084735
/workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.4173764694
/workspace/coverage/cover_reg_top/0.kmac_csr_rw.2675662432
/workspace/coverage/cover_reg_top/0.kmac_intr_test.1271701553
/workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.2675701817
/workspace/coverage/cover_reg_top/0.kmac_mem_walk.4290738404
/workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.3371028636
/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3368297225
/workspace/coverage/cover_reg_top/0.kmac_tl_errors.2802751228
/workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.729850499
/workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.976654700
/workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.2568682867
/workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2155225693
/workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.668669277
/workspace/coverage/cover_reg_top/1.kmac_csr_rw.1258861173
/workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.2686755901
/workspace/coverage/cover_reg_top/1.kmac_mem_walk.2874603647
/workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.815060373
/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.1731770290
/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.1927412479
/workspace/coverage/cover_reg_top/1.kmac_tl_errors.3086931249
/workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.2410588834
/workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.832359554
/workspace/coverage/cover_reg_top/10.kmac_csr_rw.3420030103
/workspace/coverage/cover_reg_top/10.kmac_intr_test.855487805
/workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1811847199
/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.606217071
/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3248642270
/workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.3387035392
/workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1290148700
/workspace/coverage/cover_reg_top/11.kmac_csr_rw.338849621
/workspace/coverage/cover_reg_top/11.kmac_intr_test.2441734877
/workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.539889845
/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.1642288044
/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.2278465296
/workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.12743018
/workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1989016207
/workspace/coverage/cover_reg_top/12.kmac_csr_rw.2520875912
/workspace/coverage/cover_reg_top/12.kmac_intr_test.2891269370
/workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3193369788
/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2423851747
/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.3543541827
/workspace/coverage/cover_reg_top/12.kmac_tl_errors.815450774
/workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.1876698970
/workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3556227843
/workspace/coverage/cover_reg_top/13.kmac_csr_rw.2615260794
/workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.2513698874
/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3131671668
/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.3417346887
/workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.12340763
/workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.3487060652
/workspace/coverage/cover_reg_top/14.kmac_csr_rw.2190521953
/workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.1259010691
/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.1080254204
/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.4126897993
/workspace/coverage/cover_reg_top/14.kmac_tl_errors.71052404
/workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.2788581982
/workspace/coverage/cover_reg_top/15.kmac_csr_rw.1899005223
/workspace/coverage/cover_reg_top/15.kmac_intr_test.2591837435
/workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.129065074
/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2837045294
/workspace/coverage/cover_reg_top/15.kmac_tl_errors.2377224033
/workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.343900169
/workspace/coverage/cover_reg_top/16.kmac_csr_rw.3304896829
/workspace/coverage/cover_reg_top/16.kmac_intr_test.2362346333
/workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.3512905603
/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1767147233
/workspace/coverage/cover_reg_top/16.kmac_tl_errors.666180035
/workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.353846072
/workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.3629720716
/workspace/coverage/cover_reg_top/17.kmac_csr_rw.2445241053
/workspace/coverage/cover_reg_top/17.kmac_intr_test.3611198813
/workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3208211792
/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.3291116914
/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.3544359467
/workspace/coverage/cover_reg_top/17.kmac_tl_errors.2546431209
/workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.1652380108
/workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.4237646493
/workspace/coverage/cover_reg_top/18.kmac_csr_rw.3965973937
/workspace/coverage/cover_reg_top/18.kmac_intr_test.3286387954
/workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2043645277
/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1295428570
/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.4273867647
/workspace/coverage/cover_reg_top/18.kmac_tl_errors.2617013374
/workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.3131115090
/workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.3608195031
/workspace/coverage/cover_reg_top/19.kmac_csr_rw.133008761
/workspace/coverage/cover_reg_top/19.kmac_intr_test.221329433
/workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.3449484589
/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.2588359942
/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2845349046
/workspace/coverage/cover_reg_top/19.kmac_tl_errors.3338087214
/workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.4038611003
/workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.3396331493
/workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.3983065842
/workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.2839911531
/workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.754842704
/workspace/coverage/cover_reg_top/2.kmac_csr_rw.1088387075
/workspace/coverage/cover_reg_top/2.kmac_intr_test.751956132
/workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.595682567
/workspace/coverage/cover_reg_top/2.kmac_mem_walk.1258915748
/workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.1604903486
/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.4006792738
/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.2012895202
/workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.448990586
/workspace/coverage/cover_reg_top/20.kmac_intr_test.2873954220
/workspace/coverage/cover_reg_top/21.kmac_intr_test.3155540318
/workspace/coverage/cover_reg_top/22.kmac_intr_test.42966141
/workspace/coverage/cover_reg_top/23.kmac_intr_test.2582331630
/workspace/coverage/cover_reg_top/24.kmac_intr_test.1651298307
/workspace/coverage/cover_reg_top/25.kmac_intr_test.4184601912
/workspace/coverage/cover_reg_top/26.kmac_intr_test.701313972
/workspace/coverage/cover_reg_top/27.kmac_intr_test.1649302333
/workspace/coverage/cover_reg_top/28.kmac_intr_test.506882627
/workspace/coverage/cover_reg_top/29.kmac_intr_test.1189576882
/workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.100906088
/workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.3636379259
/workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.3943312765
/workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.208408246
/workspace/coverage/cover_reg_top/3.kmac_csr_rw.3943387849
/workspace/coverage/cover_reg_top/3.kmac_intr_test.3791904268
/workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.596755440
/workspace/coverage/cover_reg_top/3.kmac_mem_walk.134863853
/workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.1399898672
/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.4213341241
/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.2254250798
/workspace/coverage/cover_reg_top/3.kmac_tl_errors.614475075
/workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.2557909483
/workspace/coverage/cover_reg_top/30.kmac_intr_test.1517136931
/workspace/coverage/cover_reg_top/31.kmac_intr_test.600587183
/workspace/coverage/cover_reg_top/32.kmac_intr_test.2832065001
/workspace/coverage/cover_reg_top/33.kmac_intr_test.1378223213
/workspace/coverage/cover_reg_top/34.kmac_intr_test.675463552
/workspace/coverage/cover_reg_top/35.kmac_intr_test.2672255370
/workspace/coverage/cover_reg_top/36.kmac_intr_test.414694465
/workspace/coverage/cover_reg_top/37.kmac_intr_test.375940526
/workspace/coverage/cover_reg_top/38.kmac_intr_test.2815695995
/workspace/coverage/cover_reg_top/39.kmac_intr_test.1829027142
/workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.3228910993
/workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.1023431287
/workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.3670527868
/workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.670467848
/workspace/coverage/cover_reg_top/4.kmac_csr_rw.3653975358
/workspace/coverage/cover_reg_top/4.kmac_intr_test.610906735
/workspace/coverage/cover_reg_top/4.kmac_mem_walk.702281581
/workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.2658992314
/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.1022312856
/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.1612228741
/workspace/coverage/cover_reg_top/4.kmac_tl_errors.3463922070
/workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.4148483286
/workspace/coverage/cover_reg_top/40.kmac_intr_test.2204324871
/workspace/coverage/cover_reg_top/41.kmac_intr_test.218062829
/workspace/coverage/cover_reg_top/42.kmac_intr_test.1559583625
/workspace/coverage/cover_reg_top/43.kmac_intr_test.4002526174
/workspace/coverage/cover_reg_top/44.kmac_intr_test.51476169
/workspace/coverage/cover_reg_top/45.kmac_intr_test.2700162919
/workspace/coverage/cover_reg_top/46.kmac_intr_test.3451123703
/workspace/coverage/cover_reg_top/47.kmac_intr_test.3799856663
/workspace/coverage/cover_reg_top/48.kmac_intr_test.4100189361
/workspace/coverage/cover_reg_top/49.kmac_intr_test.4156203967
/workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.411990430
/workspace/coverage/cover_reg_top/5.kmac_csr_rw.1103821162
/workspace/coverage/cover_reg_top/5.kmac_intr_test.4053608069
/workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.2106995414
/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.3370615233
/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.3753061068
/workspace/coverage/cover_reg_top/5.kmac_tl_errors.81562852
/workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.2662929338
/workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.219100849
/workspace/coverage/cover_reg_top/6.kmac_csr_rw.3262588955
/workspace/coverage/cover_reg_top/6.kmac_intr_test.1625629043
/workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.1820358136
/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.4275570066
/workspace/coverage/cover_reg_top/6.kmac_tl_errors.4157336777
/workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.975019609
/workspace/coverage/cover_reg_top/7.kmac_csr_rw.3713991819
/workspace/coverage/cover_reg_top/7.kmac_intr_test.593512277
/workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.334151377
/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.3505919542
/workspace/coverage/cover_reg_top/7.kmac_tl_errors.2723169317
/workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.1064292518
/workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2896645624
/workspace/coverage/cover_reg_top/8.kmac_csr_rw.2314219862
/workspace/coverage/cover_reg_top/8.kmac_intr_test.709053803
/workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.3374686684
/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.287680422
/workspace/coverage/cover_reg_top/8.kmac_tl_errors.3952354432
/workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.961431180
/workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2657370507
/workspace/coverage/cover_reg_top/9.kmac_csr_rw.2335493744
/workspace/coverage/cover_reg_top/9.kmac_intr_test.1323016654
/workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.401298854
/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.2695332613
/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.3822878230
/workspace/coverage/cover_reg_top/9.kmac_tl_errors.567813773
/workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.2096120517

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Total test records in report: 215

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tests.html | tests1.html | tests2.html | tests3.html

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.1512303341			Aug 14 04:37:45 PM PDT 24	Aug 14 04:37:47 PM PDT 24	112145522 ps
T2	/workspace/coverage/cover_reg_top/2.kmac_tl_errors.2044399917			Aug 14 04:37:15 PM PDT 24	Aug 14 04:37:17 PM PDT 24	60641723 ps
T3	/workspace/coverage/cover_reg_top/10.kmac_intr_test.855487805			Aug 14 04:37:45 PM PDT 24	Aug 14 04:37:46 PM PDT 24	23049745 ps
T4	/workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.2557909483			Aug 14 04:36:58 PM PDT 24	Aug 14 04:37:02 PM PDT 24	240702970 ps
T9	/workspace/coverage/cover_reg_top/8.kmac_intr_test.709053803			Aug 14 04:37:27 PM PDT 24	Aug 14 04:37:28 PM PDT 24	14936512 ps
T5	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.3417346887			Aug 14 04:37:40 PM PDT 24	Aug 14 04:37:43 PM PDT 24	355253972 ps
T12	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.2012895202			Aug 14 04:37:20 PM PDT 24	Aug 14 04:37:22 PM PDT 24	105102214 ps
T13	/workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.12743018			Aug 14 04:37:30 PM PDT 24	Aug 14 04:37:33 PM PDT 24	586730822 ps
T14	/workspace/coverage/cover_reg_top/14.kmac_csr_rw.2190521953			Aug 14 04:37:41 PM PDT 24	Aug 14 04:37:42 PM PDT 24	15118719 ps
T15	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.3030385306			Aug 14 04:37:38 PM PDT 24	Aug 14 04:37:41 PM PDT 24	197095706 ps
T27	/workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.1652380108			Aug 14 04:37:46 PM PDT 24	Aug 14 04:37:49 PM PDT 24	1347723390 ps
T10	/workspace/coverage/cover_reg_top/13.kmac_intr_test.1830665227			Aug 14 04:37:41 PM PDT 24	Aug 14 04:37:42 PM PDT 24	17165992 ps
T11	/workspace/coverage/cover_reg_top/14.kmac_intr_test.1863986005			Aug 14 04:37:51 PM PDT 24	Aug 14 04:37:52 PM PDT 24	13449092 ps
T16	/workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.2697022926			Aug 14 04:37:37 PM PDT 24	Aug 14 04:37:39 PM PDT 24	66214028 ps
T37	/workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.1259010691			Aug 14 04:37:31 PM PDT 24	Aug 14 04:37:33 PM PDT 24	98552455 ps
T30	/workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.4148483286			Aug 14 04:37:37 PM PDT 24	Aug 14 04:37:42 PM PDT 24	306264932 ps
T38	/workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.3512905603			Aug 14 04:37:58 PM PDT 24	Aug 14 04:37:59 PM PDT 24	98931876 ps
T43	/workspace/coverage/cover_reg_top/49.kmac_intr_test.4156203967			Aug 14 04:37:50 PM PDT 24	Aug 14 04:37:51 PM PDT 24	37289417 ps
T17	/workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.670467848			Aug 14 04:37:17 PM PDT 24	Aug 14 04:37:19 PM PDT 24	251277385 ps
T31	/workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.3387035392			Aug 14 04:37:26 PM PDT 24	Aug 14 04:37:29 PM PDT 24	647414934 ps
T44	/workspace/coverage/cover_reg_top/45.kmac_intr_test.2700162919			Aug 14 04:37:45 PM PDT 24	Aug 14 04:37:46 PM PDT 24	57017138 ps
T39	/workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.1820358136			Aug 14 04:37:34 PM PDT 24	Aug 14 04:37:36 PM PDT 24	94533370 ps
T45	/workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3193369788			Aug 14 04:38:04 PM PDT 24	Aug 14 04:38:06 PM PDT 24	118095534 ps
T49	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.2278465296			Aug 14 04:37:45 PM PDT 24	Aug 14 04:37:46 PM PDT 24	190021187 ps
T65	/workspace/coverage/cover_reg_top/18.kmac_intr_test.3286387954			Aug 14 04:37:47 PM PDT 24	Aug 14 04:37:48 PM PDT 24	11413079 ps
T18	/workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2896645624			Aug 14 04:37:32 PM PDT 24	Aug 14 04:37:34 PM PDT 24	654186769 ps
T46	/workspace/coverage/cover_reg_top/18.kmac_csr_rw.3965973937			Aug 14 04:37:54 PM PDT 24	Aug 14 04:37:55 PM PDT 24	24406742 ps
T69	/workspace/coverage/cover_reg_top/43.kmac_intr_test.4002526174			Aug 14 04:37:45 PM PDT 24	Aug 14 04:37:46 PM PDT 24	13789398 ps
T70	/workspace/coverage/cover_reg_top/36.kmac_intr_test.414694465			Aug 14 04:38:01 PM PDT 24	Aug 14 04:38:01 PM PDT 24	19829791 ps
T62	/workspace/coverage/cover_reg_top/48.kmac_intr_test.4100189361			Aug 14 04:37:52 PM PDT 24	Aug 14 04:37:52 PM PDT 24	13241135 ps
T33	/workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.4066136727			Aug 14 04:37:22 PM PDT 24	Aug 14 04:37:27 PM PDT 24	379531697 ps
T53	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.1642288044			Aug 14 04:37:50 PM PDT 24	Aug 14 04:37:52 PM PDT 24	48358739 ps
T40	/workspace/coverage/cover_reg_top/4.kmac_csr_rw.3653975358			Aug 14 04:37:49 PM PDT 24	Aug 14 04:37:50 PM PDT 24	77020894 ps
T52	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3358057998			Aug 14 04:37:30 PM PDT 24	Aug 14 04:37:33 PM PDT 24	148899871 ps
T34	/workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.12340763			Aug 14 04:37:48 PM PDT 24	Aug 14 04:37:51 PM PDT 24	470387680 ps
T35	/workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.2662929338			Aug 14 04:37:36 PM PDT 24	Aug 14 04:37:39 PM PDT 24	99737166 ps
T41	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.675743657			Aug 14 04:37:29 PM PDT 24	Aug 14 04:37:30 PM PDT 24	109970655 ps
T19	/workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.596755440			Aug 14 04:37:39 PM PDT 24	Aug 14 04:37:40 PM PDT 24	36612140 ps
T47	/workspace/coverage/cover_reg_top/7.kmac_csr_rw.3713991819			Aug 14 04:37:29 PM PDT 24	Aug 14 04:37:31 PM PDT 24	70397099 ps
T71	/workspace/coverage/cover_reg_top/3.kmac_mem_walk.134863853			Aug 14 04:37:15 PM PDT 24	Aug 14 04:37:16 PM PDT 24	33869330 ps
T48	/workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.401298854			Aug 14 04:37:24 PM PDT 24	Aug 14 04:37:26 PM PDT 24	224918414 ps
T28	/workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.2675701817			Aug 14 04:37:19 PM PDT 24	Aug 14 04:37:20 PM PDT 24	57243966 ps
T64	/workspace/coverage/cover_reg_top/46.kmac_intr_test.3451123703			Aug 14 04:37:43 PM PDT 24	Aug 14 04:37:43 PM PDT 24	19295662 ps
T20	/workspace/coverage/cover_reg_top/15.kmac_tl_errors.2377224033			Aug 14 04:37:51 PM PDT 24	Aug 14 04:37:53 PM PDT 24	203018766 ps
T72	/workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.2568682867			Aug 14 04:37:09 PM PDT 24	Aug 14 04:37:19 PM PDT 24	504965679 ps
T73	/workspace/coverage/cover_reg_top/21.kmac_intr_test.3155540318			Aug 14 04:37:52 PM PDT 24	Aug 14 04:37:53 PM PDT 24	41804504 ps
T74	/workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.976654700			Aug 14 04:37:20 PM PDT 24	Aug 14 04:37:29 PM PDT 24	392821079 ps
T75	/workspace/coverage/cover_reg_top/1.kmac_intr_test.1251382029			Aug 14 04:37:35 PM PDT 24	Aug 14 04:37:36 PM PDT 24	28899793 ps
T32	/workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.448990586			Aug 14 04:37:24 PM PDT 24	Aug 14 04:37:27 PM PDT 24	279949895 ps
T42	/workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.913099174			Aug 14 04:37:18 PM PDT 24	Aug 14 04:37:26 PM PDT 24	227025763 ps
T76	/workspace/coverage/cover_reg_top/29.kmac_intr_test.1189576882			Aug 14 04:37:50 PM PDT 24	Aug 14 04:37:51 PM PDT 24	41748887 ps
T50	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.3544359467			Aug 14 04:37:39 PM PDT 24	Aug 14 04:37:42 PM PDT 24	401484433 ps
T21	/workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.219100849			Aug 14 04:37:37 PM PDT 24	Aug 14 04:37:39 PM PDT 24	71991761 ps
T77	/workspace/coverage/cover_reg_top/16.kmac_csr_rw.3304896829			Aug 14 04:38:19 PM PDT 24	Aug 14 04:38:20 PM PDT 24	19156656 ps
T78	/workspace/coverage/cover_reg_top/31.kmac_intr_test.600587183			Aug 14 04:38:11 PM PDT 24	Aug 14 04:38:12 PM PDT 24	23084695 ps
T79	/workspace/coverage/cover_reg_top/23.kmac_intr_test.2582331630			Aug 14 04:37:54 PM PDT 24	Aug 14 04:37:55 PM PDT 24	26375848 ps
T80	/workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.129065074			Aug 14 04:38:10 PM PDT 24	Aug 14 04:38:13 PM PDT 24	85026597 ps
T81	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.4006792738			Aug 14 04:37:12 PM PDT 24	Aug 14 04:37:13 PM PDT 24	39608047 ps
T29	/workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.2686755901			Aug 14 04:37:34 PM PDT 24	Aug 14 04:37:36 PM PDT 24	159991040 ps
T82	/workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.3131115090			Aug 14 04:38:08 PM PDT 24	Aug 14 04:38:11 PM PDT 24	187437860 ps
T83	/workspace/coverage/cover_reg_top/7.kmac_intr_test.593512277			Aug 14 04:37:44 PM PDT 24	Aug 14 04:37:45 PM PDT 24	17205647 ps
T22	/workspace/coverage/cover_reg_top/10.kmac_tl_errors.2371078673			Aug 14 04:37:46 PM PDT 24	Aug 14 04:37:50 PM PDT 24	172766424 ps
T36	/workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.2096120517			Aug 14 04:37:42 PM PDT 24	Aug 14 04:37:47 PM PDT 24	433496662 ps
T23	/workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.208408246			Aug 14 04:37:30 PM PDT 24	Aug 14 04:37:32 PM PDT 24	102218788 ps
T51	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.2254250798			Aug 14 04:37:08 PM PDT 24	Aug 14 04:37:10 PM PDT 24	52809081 ps
T84	/workspace/coverage/cover_reg_top/12.kmac_intr_test.2891269370			Aug 14 04:37:44 PM PDT 24	Aug 14 04:37:45 PM PDT 24	12898271 ps
T24	/workspace/coverage/cover_reg_top/3.kmac_tl_errors.614475075			Aug 14 04:37:31 PM PDT 24	Aug 14 04:37:33 PM PDT 24	107683706 ps
T85	/workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.3374686684			Aug 14 04:37:42 PM PDT 24	Aug 14 04:37:44 PM PDT 24	43383176 ps
T86	/workspace/coverage/cover_reg_top/0.kmac_csr_rw.2675662432			Aug 14 04:37:11 PM PDT 24	Aug 14 04:37:12 PM PDT 24	39515641 ps
T87	/workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1811847199			Aug 14 04:37:36 PM PDT 24	Aug 14 04:37:39 PM PDT 24	690841593 ps
T88	/workspace/coverage/cover_reg_top/25.kmac_intr_test.4184601912			Aug 14 04:37:52 PM PDT 24	Aug 14 04:37:53 PM PDT 24	19922203 ps
T89	/workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.3983065842			Aug 14 04:37:32 PM PDT 24	Aug 14 04:37:40 PM PDT 24	294577712 ps
T54	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.606217071			Aug 14 04:37:41 PM PDT 24	Aug 14 04:37:42 PM PDT 24	25394153 ps
T25	/workspace/coverage/cover_reg_top/17.kmac_tl_errors.2546431209			Aug 14 04:37:46 PM PDT 24	Aug 14 04:37:49 PM PDT 24	48383007 ps
T90	/workspace/coverage/cover_reg_top/19.kmac_csr_rw.133008761			Aug 14 04:38:12 PM PDT 24	Aug 14 04:38:13 PM PDT 24	57879215 ps
T55	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.4275570066			Aug 14 04:37:28 PM PDT 24	Aug 14 04:37:29 PM PDT 24	35303951 ps
T63	/workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.1046122250			Aug 14 04:37:32 PM PDT 24	Aug 14 04:37:37 PM PDT 24	831853924 ps
T91	/workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.3943312765			Aug 14 04:37:04 PM PDT 24	Aug 14 04:37:06 PM PDT 24	91964283 ps
T92	/workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1679084735			Aug 14 04:37:13 PM PDT 24	Aug 14 04:37:14 PM PDT 24	79090270 ps
T93	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.1080254204			Aug 14 04:37:50 PM PDT 24	Aug 14 04:37:51 PM PDT 24	88322754 ps
T56	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1295428570			Aug 14 04:37:54 PM PDT 24	Aug 14 04:37:55 PM PDT 24	880632037 ps
T94	/workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.815060373			Aug 14 04:37:13 PM PDT 24	Aug 14 04:37:14 PM PDT 24	45454348 ps
T26	/workspace/coverage/cover_reg_top/11.kmac_tl_errors.998196234			Aug 14 04:37:38 PM PDT 24	Aug 14 04:37:41 PM PDT 24	98421042 ps
T95	/workspace/coverage/cover_reg_top/34.kmac_intr_test.675463552			Aug 14 04:38:39 PM PDT 24	Aug 14 04:38:40 PM PDT 24	49513404 ps
T96	/workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.2788581982			Aug 14 04:37:52 PM PDT 24	Aug 14 04:37:55 PM PDT 24	283946706 ps
T97	/workspace/coverage/cover_reg_top/6.kmac_csr_rw.3262588955			Aug 14 04:37:19 PM PDT 24	Aug 14 04:37:21 PM PDT 24	208705352 ps
T6	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2660177365			Aug 14 04:37:29 PM PDT 24	Aug 14 04:37:31 PM PDT 24	62850208 ps
T98	/workspace/coverage/cover_reg_top/10.kmac_csr_rw.3420030103			Aug 14 04:37:38 PM PDT 24	Aug 14 04:37:39 PM PDT 24	26703943 ps
T99	/workspace/coverage/cover_reg_top/12.kmac_csr_rw.2520875912			Aug 14 04:37:38 PM PDT 24	Aug 14 04:37:39 PM PDT 24	70748980 ps
T100	/workspace/coverage/cover_reg_top/38.kmac_intr_test.2815695995			Aug 14 04:37:42 PM PDT 24	Aug 14 04:37:42 PM PDT 24	14534205 ps
T101	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.2695332613			Aug 14 04:37:50 PM PDT 24	Aug 14 04:37:56 PM PDT 24	63742441 ps
T102	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3131671668			Aug 14 04:38:03 PM PDT 24	Aug 14 04:38:04 PM PDT 24	35620535 ps
T103	/workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2155225693			Aug 14 04:37:44 PM PDT 24	Aug 14 04:37:45 PM PDT 24	19672782 ps
T104	/workspace/coverage/cover_reg_top/28.kmac_intr_test.506882627			Aug 14 04:37:51 PM PDT 24	Aug 14 04:37:52 PM PDT 24	35253690 ps
T57	/workspace/coverage/cover_reg_top/13.kmac_tl_errors.1454114329			Aug 14 04:37:47 PM PDT 24	Aug 14 04:37:50 PM PDT 24	321718193 ps
T105	/workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.3608195031			Aug 14 04:37:50 PM PDT 24	Aug 14 04:37:52 PM PDT 24	49035249 ps
T106	/workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3556227843			Aug 14 04:37:38 PM PDT 24	Aug 14 04:37:40 PM PDT 24	96935909 ps
T107	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.4213341241			Aug 14 04:37:04 PM PDT 24	Aug 14 04:37:05 PM PDT 24	29040857 ps
T108	/workspace/coverage/cover_reg_top/6.kmac_intr_test.1625629043			Aug 14 04:37:32 PM PDT 24	Aug 14 04:37:33 PM PDT 24	28804793 ps
T109	/workspace/coverage/cover_reg_top/47.kmac_intr_test.3799856663			Aug 14 04:37:50 PM PDT 24	Aug 14 04:37:51 PM PDT 24	121680005 ps
T110	/workspace/coverage/cover_reg_top/1.kmac_mem_walk.2874603647			Aug 14 04:37:08 PM PDT 24	Aug 14 04:37:09 PM PDT 24	66370351 ps
T58	/workspace/coverage/cover_reg_top/6.kmac_tl_errors.4157336777			Aug 14 04:37:31 PM PDT 24	Aug 14 04:37:34 PM PDT 24	66400605 ps
T111	/workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.595682567			Aug 14 04:37:01 PM PDT 24	Aug 14 04:37:02 PM PDT 24	37039856 ps
T112	/workspace/coverage/cover_reg_top/1.kmac_csr_rw.1258861173			Aug 14 04:37:47 PM PDT 24	Aug 14 04:37:48 PM PDT 24	48968315 ps
T113	/workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3208211792			Aug 14 04:37:52 PM PDT 24	Aug 14 04:37:54 PM PDT 24	36765792 ps
T114	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.3543541827			Aug 14 04:37:43 PM PDT 24	Aug 14 04:37:46 PM PDT 24	194936050 ps
T115	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.1022312856			Aug 14 04:37:44 PM PDT 24	Aug 14 04:37:45 PM PDT 24	43450689 ps
T116	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.1927412479			Aug 14 04:37:28 PM PDT 24	Aug 14 04:37:30 PM PDT 24	169237932 ps
T59	/workspace/coverage/cover_reg_top/8.kmac_tl_errors.3952354432			Aug 14 04:37:25 PM PDT 24	Aug 14 04:37:27 PM PDT 24	30054129 ps
T117	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.1612228741			Aug 14 04:37:34 PM PDT 24	Aug 14 04:37:37 PM PDT 24	193676335 ps
T118	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.1731770290			Aug 14 04:37:26 PM PDT 24	Aug 14 04:37:27 PM PDT 24	37870810 ps
T119	/workspace/coverage/cover_reg_top/26.kmac_intr_test.701313972			Aug 14 04:37:49 PM PDT 24	Aug 14 04:37:50 PM PDT 24	14151375 ps
T68	/workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.1064292518			Aug 14 04:37:30 PM PDT 24	Aug 14 04:37:35 PM PDT 24	1375647058 ps
T120	/workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.2658992314			Aug 14 04:37:27 PM PDT 24	Aug 14 04:37:30 PM PDT 24	439252574 ps
T121	/workspace/coverage/cover_reg_top/44.kmac_intr_test.51476169			Aug 14 04:37:46 PM PDT 24	Aug 14 04:37:47 PM PDT 24	44201970 ps
T122	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.3505919542			Aug 14 04:37:45 PM PDT 24	Aug 14 04:37:46 PM PDT 24	117508317 ps
T123	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3248642270			Aug 14 04:37:44 PM PDT 24	Aug 14 04:37:46 PM PDT 24	368400956 ps
T61	/workspace/coverage/cover_reg_top/9.kmac_tl_errors.567813773			Aug 14 04:37:35 PM PDT 24	Aug 14 04:37:38 PM PDT 24	415904242 ps
T124	/workspace/coverage/cover_reg_top/11.kmac_csr_rw.338849621			Aug 14 04:37:17 PM PDT 24	Aug 14 04:37:23 PM PDT 24	20629495 ps
T125	/workspace/coverage/cover_reg_top/42.kmac_intr_test.1559583625			Aug 14 04:37:48 PM PDT 24	Aug 14 04:37:49 PM PDT 24	31411768 ps
T126	/workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.3228910993			Aug 14 04:37:31 PM PDT 24	Aug 14 04:37:35 PM PDT 24	289454463 ps
T127	/workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.3629720716			Aug 14 04:38:11 PM PDT 24	Aug 14 04:38:12 PM PDT 24	60241412 ps
T128	/workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.1604903486			Aug 14 04:37:25 PM PDT 24	Aug 14 04:37:27 PM PDT 24	34297255 ps
T129	/workspace/coverage/cover_reg_top/3.kmac_csr_rw.3943387849			Aug 14 04:37:26 PM PDT 24	Aug 14 04:37:27 PM PDT 24	93205305 ps
T130	/workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.1399898672			Aug 14 04:37:17 PM PDT 24	Aug 14 04:37:19 PM PDT 24	108450542 ps
T131	/workspace/coverage/cover_reg_top/5.kmac_intr_test.4053608069			Aug 14 04:37:43 PM PDT 24	Aug 14 04:37:44 PM PDT 24	39776833 ps
T132	/workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.3670527868			Aug 14 04:37:34 PM PDT 24	Aug 14 04:37:36 PM PDT 24	85273172 ps
T133	/workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.3371028636			Aug 14 04:37:03 PM PDT 24	Aug 14 04:37:05 PM PDT 24	74866723 ps
T134	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.4126897993			Aug 14 04:37:52 PM PDT 24	Aug 14 04:37:55 PM PDT 24	410168568 ps
T135	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.3753061068			Aug 14 04:37:33 PM PDT 24	Aug 14 04:37:35 PM PDT 24	123102299 ps
T136	/workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.343900169			Aug 14 04:37:46 PM PDT 24	Aug 14 04:37:48 PM PDT 24	117652041 ps
T137	/workspace/coverage/cover_reg_top/0.kmac_tl_errors.2802751228			Aug 14 04:37:21 PM PDT 24	Aug 14 04:37:23 PM PDT 24	244054282 ps
T138	/workspace/coverage/cover_reg_top/27.kmac_intr_test.1649302333			Aug 14 04:37:57 PM PDT 24	Aug 14 04:37:58 PM PDT 24	22083529 ps
T139	/workspace/coverage/cover_reg_top/15.kmac_intr_test.2591837435			Aug 14 04:37:35 PM PDT 24	Aug 14 04:37:41 PM PDT 24	11964643 ps
T140	/workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.975019609			Aug 14 04:37:25 PM PDT 24	Aug 14 04:37:27 PM PDT 24	62548470 ps
T141	/workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.411990430			Aug 14 04:37:32 PM PDT 24	Aug 14 04:37:33 PM PDT 24	148010323 ps
T142	/workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2657370507			Aug 14 04:37:43 PM PDT 24	Aug 14 04:37:45 PM PDT 24	51856491 ps
T143	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.3822878230			Aug 14 04:37:34 PM PDT 24	Aug 14 04:37:37 PM PDT 24	61116208 ps
T144	/workspace/coverage/cover_reg_top/40.kmac_intr_test.2204324871			Aug 14 04:37:46 PM PDT 24	Aug 14 04:37:47 PM PDT 24	38024380 ps
T145	/workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2043645277			Aug 14 04:37:55 PM PDT 24	Aug 14 04:37:57 PM PDT 24	25892608 ps
T146	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2837045294			Aug 14 04:37:39 PM PDT 24	Aug 14 04:37:40 PM PDT 24	33846594 ps
T147	/workspace/coverage/cover_reg_top/17.kmac_csr_rw.2445241053			Aug 14 04:37:57 PM PDT 24	Aug 14 04:37:58 PM PDT 24	287408010 ps
T148	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.2588359942			Aug 14 04:38:10 PM PDT 24	Aug 14 04:38:12 PM PDT 24	36771495 ps
T60	/workspace/coverage/cover_reg_top/16.kmac_tl_errors.666180035			Aug 14 04:37:56 PM PDT 24	Aug 14 04:37:58 PM PDT 24	91538711 ps
T67	/workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.1876698970			Aug 14 04:37:35 PM PDT 24	Aug 14 04:37:38 PM PDT 24	208391371 ps
T149	/workspace/coverage/cover_reg_top/37.kmac_intr_test.375940526			Aug 14 04:37:48 PM PDT 24	Aug 14 04:37:49 PM PDT 24	13459411 ps
T150	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1767147233			Aug 14 04:37:40 PM PDT 24	Aug 14 04:37:43 PM PDT 24	208158693 ps
T151	/workspace/coverage/cover_reg_top/0.kmac_mem_walk.4290738404			Aug 14 04:37:37 PM PDT 24	Aug 14 04:37:38 PM PDT 24	11786332 ps
T152	/workspace/coverage/cover_reg_top/1.kmac_tl_errors.3086931249			Aug 14 04:37:07 PM PDT 24	Aug 14 04:37:10 PM PDT 24	242090038 ps
T153	/workspace/coverage/cover_reg_top/4.kmac_tl_errors.3463922070			Aug 14 04:37:39 PM PDT 24	Aug 14 04:37:43 PM PDT 24	57202474 ps
T154	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3368297225			Aug 14 04:37:09 PM PDT 24	Aug 14 04:37:10 PM PDT 24	71068302 ps
T155	/workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.961431180			Aug 14 04:37:35 PM PDT 24	Aug 14 04:37:39 PM PDT 24	330256465 ps
T156	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.4273867647			Aug 14 04:37:54 PM PDT 24	Aug 14 04:37:56 PM PDT 24	176043556 ps
T157	/workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.3396331493			Aug 14 04:37:24 PM PDT 24	Aug 14 04:37:34 PM PDT 24	535321300 ps
T158	/workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.832359554			Aug 14 04:37:37 PM PDT 24	Aug 14 04:37:44 PM PDT 24	38828624 ps
T66	/workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.353846072			Aug 14 04:37:46 PM PDT 24	Aug 14 04:37:50 PM PDT 24	192980776 ps
T159	/workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.2839911531			Aug 14 04:37:03 PM PDT 24	Aug 14 04:37:04 PM PDT 24	49472716 ps
T160	/workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.754842704			Aug 14 04:36:58 PM PDT 24	Aug 14 04:37:00 PM PDT 24	80519732 ps
T161	/workspace/coverage/cover_reg_top/12.kmac_tl_errors.815450774			Aug 14 04:37:52 PM PDT 24	Aug 14 04:37:54 PM PDT 24	130962276 ps
T162	/workspace/coverage/cover_reg_top/35.kmac_intr_test.2672255370			Aug 14 04:38:20 PM PDT 24	Aug 14 04:38:21 PM PDT 24	111247938 ps
T163	/workspace/coverage/cover_reg_top/32.kmac_intr_test.2832065001			Aug 14 04:37:54 PM PDT 24	Aug 14 04:37:55 PM PDT 24	18584802 ps
T164	/workspace/coverage/cover_reg_top/13.kmac_csr_rw.2615260794			Aug 14 04:37:33 PM PDT 24	Aug 14 04:37:35 PM PDT 24	63792896 ps
T165	/workspace/coverage/cover_reg_top/19.kmac_intr_test.221329433			Aug 14 04:38:05 PM PDT 24	Aug 14 04:38:11 PM PDT 24	41150765 ps
T166	/workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1290148700			Aug 14 04:37:38 PM PDT 24	Aug 14 04:37:40 PM PDT 24	202723436 ps
T167	/workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.3449484589			Aug 14 04:37:45 PM PDT 24	Aug 14 04:37:47 PM PDT 24	70300547 ps
T168	/workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.2001097646			Aug 14 04:37:23 PM PDT 24	Aug 14 04:37:32 PM PDT 24	1516566667 ps
T169	/workspace/coverage/cover_reg_top/24.kmac_intr_test.1651298307			Aug 14 04:37:46 PM PDT 24	Aug 14 04:37:47 PM PDT 24	13256614 ps
T170	/workspace/coverage/cover_reg_top/41.kmac_intr_test.218062829			Aug 14 04:37:43 PM PDT 24	Aug 14 04:37:44 PM PDT 24	14880690 ps
T171	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.3370615233			Aug 14 04:37:25 PM PDT 24	Aug 14 04:37:26 PM PDT 24	67784844 ps
T172	/workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.2513698874			Aug 14 04:37:45 PM PDT 24	Aug 14 04:37:48 PM PDT 24	229563468 ps
T173	/workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.2106995414			Aug 14 04:37:36 PM PDT 24	Aug 14 04:37:39 PM PDT 24	461753670 ps
T174	/workspace/coverage/cover_reg_top/5.kmac_csr_rw.1103821162			Aug 14 04:37:29 PM PDT 24	Aug 14 04:37:30 PM PDT 24	100927813 ps
T175	/workspace/coverage/cover_reg_top/20.kmac_intr_test.2873954220			Aug 14 04:37:55 PM PDT 24	Aug 14 04:37:55 PM PDT 24	17702746 ps
T176	/workspace/coverage/cover_reg_top/4.kmac_intr_test.610906735			Aug 14 04:37:31 PM PDT 24	Aug 14 04:37:32 PM PDT 24	18144908 ps
T177	/workspace/coverage/cover_reg_top/2.kmac_intr_test.751956132			Aug 14 04:37:19 PM PDT 24	Aug 14 04:37:20 PM PDT 24	43664583 ps
T178	/workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.2410588834			Aug 14 04:37:26 PM PDT 24	Aug 14 04:37:29 PM PDT 24	202565866 ps
T179	/workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.4173764694			Aug 14 04:37:22 PM PDT 24	Aug 14 04:37:24 PM PDT 24	245481968 ps
T7	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.3641133203			Aug 14 04:37:24 PM PDT 24	Aug 14 04:37:28 PM PDT 24	156591128 ps
T180	/workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.3487060652			Aug 14 04:37:35 PM PDT 24	Aug 14 04:37:38 PM PDT 24	40416215 ps
T181	/workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.334151377			Aug 14 04:37:33 PM PDT 24	Aug 14 04:37:35 PM PDT 24	166457898 ps
T182	/workspace/coverage/cover_reg_top/33.kmac_intr_test.1378223213			Aug 14 04:37:47 PM PDT 24	Aug 14 04:37:48 PM PDT 24	15112150 ps
T183	/workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.4237646493			Aug 14 04:38:00 PM PDT 24	Aug 14 04:38:02 PM PDT 24	410887771 ps
T184	/workspace/coverage/cover_reg_top/22.kmac_intr_test.42966141			Aug 14 04:37:48 PM PDT 24	Aug 14 04:37:49 PM PDT 24	41505747 ps
T185	/workspace/coverage/cover_reg_top/0.kmac_intr_test.1271701553			Aug 14 04:37:30 PM PDT 24	Aug 14 04:37:31 PM PDT 24	21366334 ps
T186	/workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.100906088			Aug 14 04:37:44 PM PDT 24	Aug 14 04:37:52 PM PDT 24	272829874 ps
T187	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2845349046			Aug 14 04:37:48 PM PDT 24	Aug 14 04:37:51 PM PDT 24	401404788 ps
T188	/workspace/coverage/cover_reg_top/5.kmac_tl_errors.81562852			Aug 14 04:37:40 PM PDT 24	Aug 14 04:37:42 PM PDT 24	305691480 ps
T189	/workspace/coverage/cover_reg_top/9.kmac_csr_rw.2335493744			Aug 14 04:37:35 PM PDT 24	Aug 14 04:37:36 PM PDT 24	66756511 ps
T190	/workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.729850499			Aug 14 04:37:40 PM PDT 24	Aug 14 04:37:43 PM PDT 24	114734809 ps
T191	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2423851747			Aug 14 04:37:48 PM PDT 24	Aug 14 04:37:49 PM PDT 24	19621301 ps
T192	/workspace/coverage/cover_reg_top/11.kmac_intr_test.2441734877			Aug 14 04:37:32 PM PDT 24	Aug 14 04:37:33 PM PDT 24	39306744 ps
T193	/workspace/coverage/cover_reg_top/8.kmac_csr_rw.2314219862			Aug 14 04:37:38 PM PDT 24	Aug 14 04:37:39 PM PDT 24	115060875 ps
T194	/workspace/coverage/cover_reg_top/17.kmac_intr_test.3611198813			Aug 14 04:38:06 PM PDT 24	Aug 14 04:38:07 PM PDT 24	39960219 ps
T195	/workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1989016207			Aug 14 04:37:40 PM PDT 24	Aug 14 04:37:41 PM PDT 24	24143222 ps
T196	/workspace/coverage/cover_reg_top/9.kmac_intr_test.1323016654			Aug 14 04:37:38 PM PDT 24	Aug 14 04:37:39 PM PDT 24	17355262 ps
T197	/workspace/coverage/cover_reg_top/15.kmac_csr_rw.1899005223			Aug 14 04:37:32 PM PDT 24	Aug 14 04:37:34 PM PDT 24	30826784 ps
T198	/workspace/coverage/cover_reg_top/19.kmac_tl_errors.3338087214			Aug 14 04:37:50 PM PDT 24	Aug 14 04:37:54 PM PDT 24	520216000 ps
T199	/workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.4038611003			Aug 14 04:38:06 PM PDT 24	Aug 14 04:38:13 PM PDT 24	204385138 ps
T200	/workspace/coverage/cover_reg_top/16.kmac_intr_test.2362346333			Aug 14 04:37:58 PM PDT 24	Aug 14 04:37:59 PM PDT 24	12973906 ps
T201	/workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.668669277			Aug 14 04:37:19 PM PDT 24	Aug 14 04:37:21 PM PDT 24	36399246 ps
T202	/workspace/coverage/cover_reg_top/4.kmac_mem_walk.702281581			Aug 14 04:37:34 PM PDT 24	Aug 14 04:37:35 PM PDT 24	11502067 ps
T203	/workspace/coverage/cover_reg_top/3.kmac_intr_test.3791904268			Aug 14 04:37:35 PM PDT 24	Aug 14 04:37:36 PM PDT 24	25526956 ps
T204	/workspace/coverage/cover_reg_top/14.kmac_tl_errors.71052404			Aug 14 04:37:42 PM PDT 24	Aug 14 04:37:45 PM PDT 24	103138371 ps
T205	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.3291116914			Aug 14 04:37:53 PM PDT 24	Aug 14 04:37:54 PM PDT 24	114325653 ps
T8	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1358702106			Aug 14 04:38:17 PM PDT 24	Aug 14 04:38:18 PM PDT 24	84337217 ps
T206	/workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.539889845			Aug 14 04:37:33 PM PDT 24	Aug 14 04:37:35 PM PDT 24	215258837 ps
T207	/workspace/coverage/cover_reg_top/30.kmac_intr_test.1517136931			Aug 14 04:37:54 PM PDT 24	Aug 14 04:37:55 PM PDT 24	15320232 ps
T208	/workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.3636379259			Aug 14 04:37:26 PM PDT 24	Aug 14 04:37:36 PM PDT 24	1929779804 ps
T209	/workspace/coverage/cover_reg_top/18.kmac_tl_errors.2617013374			Aug 14 04:37:42 PM PDT 24	Aug 14 04:37:45 PM PDT 24	123766204 ps
T210	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.287680422			Aug 14 04:37:24 PM PDT 24	Aug 14 04:37:25 PM PDT 24	63567063 ps
T211	/workspace/coverage/cover_reg_top/39.kmac_intr_test.1829027142			Aug 14 04:38:17 PM PDT 24	Aug 14 04:38:18 PM PDT 24	12422708 ps
T212	/workspace/coverage/cover_reg_top/7.kmac_tl_errors.2723169317			Aug 14 04:37:45 PM PDT 24	Aug 14 04:37:49 PM PDT 24	164772621 ps
T213	/workspace/coverage/cover_reg_top/2.kmac_mem_walk.1258915748			Aug 14 04:37:28 PM PDT 24	Aug 14 04:37:29 PM PDT 24	17634522 ps
T214	/workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.1023431287			Aug 14 04:37:26 PM PDT 24	Aug 14 04:37:45 PM PDT 24	3696879815 ps
T215	/workspace/coverage/cover_reg_top/2.kmac_csr_rw.1088387075			Aug 14 04:37:28 PM PDT 24	Aug 14 04:37:29 PM PDT 24	31517449 ps

---

Test location	/workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.1512303341
Short name	T1
Test name
Test status
Simulation time	112145522 ps
CPU time	2.66 seconds
Started	Aug 14 04:37:45 PM PDT 24
Finished	Aug 14 04:37:47 PM PDT 24
Peak memory	216160 kb
Host	smart-3f754b63-d058-4e74-bc73-89f23eeb2c66
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512303341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.1512 303341 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/2.kmac_tl_errors.2044399917
Short name	T2
Test name
Test status
Simulation time	60641723 ps
CPU time	2.01 seconds
Started	Aug 14 04:37:15 PM PDT 24
Finished	Aug 14 04:37:17 PM PDT 24
Peak memory	216172 kb
Host	smart-c5737d53-7535-4fcb-b186-3448f66f235a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044399917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.2044399917 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/14.kmac_intr_test.1863986005
Short name	T11
Test name
Test status
Simulation time	13449092 ps
CPU time	0.81 seconds
Started	Aug 14 04:37:51 PM PDT 24
Finished	Aug 14 04:37:52 PM PDT 24
Peak memory	215732 kb
Host	smart-358f28bf-09e3-4a73-aec3-744a6530777d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863986005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.1863986005 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3358057998
Short name	T52
Test name
Test status
Simulation time	148899871 ps
CPU time	2.13 seconds
Started	Aug 14 04:37:30 PM PDT 24
Finished	Aug 14 04:37:33 PM PDT 24
Peak memory	216324 kb
Host	smart-c14d5be3-e7fd-433c-8b4c-851dc060175d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358057998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac _shadow_reg_errors_with_csr_rw.3358057998 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2660177365
Short name	T6
Test name
Test status
Simulation time	62850208 ps
CPU time	1.6 seconds
Started	Aug 14 04:37:29 PM PDT 24
Finished	Aug 14 04:37:31 PM PDT 24
Peak memory	216076 kb
Host	smart-313ee73a-383f-4b19-b85b-f0baffe53295
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660177365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac _shadow_reg_errors_with_csr_rw.2660177365 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.2697022926
Short name	T16
Test name
Test status
Simulation time	66214028 ps
CPU time	1.45 seconds
Started	Aug 14 04:37:37 PM PDT 24
Finished	Aug 14 04:37:39 PM PDT 24
Peak memory	215976 kb
Host	smart-ae0530d8-6ea9-446f-b612-74090ce8c5c6
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697022926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia l_access.2697022926 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_mem_partial_access/latest

---

Test location	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.3030385306
Short name	T15
Test name
Test status
Simulation time	197095706 ps
CPU time	2.76 seconds
Started	Aug 14 04:37:38 PM PDT 24
Finished	Aug 14 04:37:41 PM PDT 24
Peak memory	218572 kb
Host	smart-a0cd40df-88c2-485f-a1f1-6279b550323e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030385306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kma c_shadow_reg_errors_with_csr_rw.3030385306 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/10.kmac_tl_errors.2371078673
Short name	T22
Test name
Test status
Simulation time	172766424 ps
CPU time	3.7 seconds
Started	Aug 14 04:37:46 PM PDT 24
Finished	Aug 14 04:37:50 PM PDT 24
Peak memory	216060 kb
Host	smart-ec71825a-9302-4084-8bbe-9b3a0f460ef5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371078673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.2371078673 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.4066136727
Short name	T33
Test name
Test status
Simulation time	379531697 ps
CPU time	4.76 seconds
Started	Aug 14 04:37:22 PM PDT 24
Finished	Aug 14 04:37:27 PM PDT 24
Peak memory	215984 kb
Host	smart-884c2b2d-5f27-4535-8a8d-b7c99a0b3515
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066136727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.40661 36727 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/13.kmac_intr_test.1830665227
Short name	T10
Test name
Test status
Simulation time	17165992 ps
CPU time	0.81 seconds
Started	Aug 14 04:37:41 PM PDT 24
Finished	Aug 14 04:37:42 PM PDT 24
Peak memory	215800 kb
Host	smart-32154435-e081-4474-bf44-ce16701357b1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830665227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.1830665227 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.1046122250
Short name	T63
Test name
Test status
Simulation time	831853924 ps
CPU time	4.64 seconds
Started	Aug 14 04:37:32 PM PDT 24
Finished	Aug 14 04:37:37 PM PDT 24
Peak memory	216088 kb
Host	smart-b8795b72-71f0-4392-970b-08475fda9fe6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046122250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.1046 122250 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.675743657
Short name	T41
Test name
Test status
Simulation time	109970655 ps
CPU time	1.64 seconds
Started	Aug 14 04:37:29 PM PDT 24
Finished	Aug 14 04:37:30 PM PDT 24
Peak memory	219612 kb
Host	smart-9a4d2359-b6ca-4d2f-85f5-cc21e91c518d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675743657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_ shadow_reg_errors_with_csr_rw.675743657 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/13.kmac_tl_errors.1454114329
Short name	T57
Test name
Test status
Simulation time	321718193 ps
CPU time	3.75 seconds
Started	Aug 14 04:37:47 PM PDT 24
Finished	Aug 14 04:37:50 PM PDT 24
Peak memory	216088 kb
Host	smart-495f21a8-89cc-41b4-a4fd-6009483d1443
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454114329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.1454114329 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/1.kmac_intr_test.1251382029
Short name	T75
Test name
Test status
Simulation time	28899793 ps
CPU time	0.8 seconds
Started	Aug 14 04:37:35 PM PDT 24
Finished	Aug 14 04:37:36 PM PDT 24
Peak memory	215596 kb
Host	smart-40ac8a95-ba11-46c7-abb3-583f7c01b4f6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251382029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.1251382029 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.3641133203
Short name	T7
Test name
Test status
Simulation time	156591128 ps
CPU time	3.32 seconds
Started	Aug 14 04:37:24 PM PDT 24
Finished	Aug 14 04:37:28 PM PDT 24
Peak memory	219140 kb
Host	smart-69fbb4bb-cc61-453f-8413-79aaa4dfc0b9
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641133203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac _shadow_reg_errors_with_csr_rw.3641133203 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/11.kmac_tl_errors.998196234
Short name	T26
Test name
Test status
Simulation time	98421042 ps
CPU time	2.89 seconds
Started	Aug 14 04:37:38 PM PDT 24
Finished	Aug 14 04:37:41 PM PDT 24
Peak memory	216104 kb
Host	smart-6abf275e-86d4-4ed1-9162-dc9d71ee71ce
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998196234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.998196234 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1358702106
Short name	T8
Test name
Test status
Simulation time	84337217 ps
CPU time	1 seconds
Started	Aug 14 04:38:17 PM PDT 24
Finished	Aug 14 04:38:18 PM PDT 24
Peak memory	215884 kb
Host	smart-8c524934-4644-4e57-9450-2fe3f07be460
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358702106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg _errors.1358702106 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.2001097646
Short name	T168
Test name
Test status
Simulation time	1516566667 ps
CPU time	8.75 seconds
Started	Aug 14 04:37:23 PM PDT 24
Finished	Aug 14 04:37:32 PM PDT 24
Peak memory	216108 kb
Host	smart-06f63668-6b8c-4509-9663-3cc2b7500e86
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001097646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.2001097 646 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_aliasing/latest

---

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.913099174
Short name	T42
Test name
Test status
Simulation time	227025763 ps
CPU time	7.97 seconds
Started	Aug 14 04:37:18 PM PDT 24
Finished	Aug 14 04:37:26 PM PDT 24
Peak memory	215988 kb
Host	smart-e4c50aa9-6806-46c0-8c38-72c20833f8d1
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913099174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.91309917 4 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_bit_bash/latest

---

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1679084735
Short name	T92
Test name
Test status
Simulation time	79090270 ps
CPU time	0.96 seconds
Started	Aug 14 04:37:13 PM PDT 24
Finished	Aug 14 04:37:14 PM PDT 24
Peak memory	215864 kb
Host	smart-957ce83b-060e-495a-8d38-d22ff5faeda0
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679084735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.1679084 735 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_hw_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.4173764694
Short name	T179
Test name
Test status
Simulation time	245481968 ps
CPU time	2.1 seconds
Started	Aug 14 04:37:22 PM PDT 24
Finished	Aug 14 04:37:24 PM PDT 24
Peak memory	217808 kb
Host	smart-29d0f9cb-53e3-40ae-b754-b512af82196b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173764694 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.4173764694 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_rw.2675662432
Short name	T86
Test name
Test status
Simulation time	39515641 ps
CPU time	0.93 seconds
Started	Aug 14 04:37:11 PM PDT 24
Finished	Aug 14 04:37:12 PM PDT 24
Peak memory	215736 kb
Host	smart-322697f0-0ad6-42e9-8fb1-476f9bb2e415
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675662432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.2675662432 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/0.kmac_intr_test.1271701553
Short name	T185
Test name
Test status
Simulation time	21366334 ps
CPU time	0.84 seconds
Started	Aug 14 04:37:30 PM PDT 24
Finished	Aug 14 04:37:31 PM PDT 24
Peak memory	215732 kb
Host	smart-7fcce938-e879-40ac-b332-16df01e0500b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271701553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.1271701553 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.2675701817
Short name	T28
Test name
Test status
Simulation time	57243966 ps
CPU time	1.16 seconds
Started	Aug 14 04:37:19 PM PDT 24
Finished	Aug 14 04:37:20 PM PDT 24
Peak memory	216024 kb
Host	smart-e562c15d-9e77-4181-814e-2210e2b46c4e
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675701817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia l_access.2675701817 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_mem_partial_access/latest

---

Test location	/workspace/coverage/cover_reg_top/0.kmac_mem_walk.4290738404
Short name	T151
Test name
Test status
Simulation time	11786332 ps
CPU time	0.76 seconds
Started	Aug 14 04:37:37 PM PDT 24
Finished	Aug 14 04:37:38 PM PDT 24
Peak memory	215796 kb
Host	smart-f88b1dcc-bcd4-470e-8668-cc665902c1df
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290738404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.4290738404 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_mem_walk/latest

---

Test location	/workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.3371028636
Short name	T133
Test name
Test status
Simulation time	74866723 ps
CPU time	2.08 seconds
Started	Aug 14 04:37:03 PM PDT 24
Finished	Aug 14 04:37:05 PM PDT 24
Peak memory	216144 kb
Host	smart-db80befd-1c13-4b38-b0f0-503bd6432662
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371028636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr _outstanding.3371028636 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3368297225
Short name	T154
Test name
Test status
Simulation time	71068302 ps
CPU time	1.22 seconds
Started	Aug 14 04:37:09 PM PDT 24
Finished	Aug 14 04:37:10 PM PDT 24
Peak memory	216596 kb
Host	smart-c8ee9c4a-b2a0-4c90-9851-0c7cdb4fbc75
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368297225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_ errors.3368297225 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/0.kmac_tl_errors.2802751228
Short name	T137
Test name
Test status
Simulation time	244054282 ps
CPU time	2.01 seconds
Started	Aug 14 04:37:21 PM PDT 24
Finished	Aug 14 04:37:23 PM PDT 24
Peak memory	216048 kb
Host	smart-ae5ca848-e04b-4acc-b9e6-6df3979ad034
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802751228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.2802751228 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.729850499
Short name	T190
Test name
Test status
Simulation time	114734809 ps
CPU time	2.83 seconds
Started	Aug 14 04:37:40 PM PDT 24
Finished	Aug 14 04:37:43 PM PDT 24
Peak memory	216004 kb
Host	smart-80d75df5-dee7-4ee4-9209-4107705c7330
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729850499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.729850 499 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.976654700
Short name	T74
Test name
Test status
Simulation time	392821079 ps
CPU time	9.05 seconds
Started	Aug 14 04:37:20 PM PDT 24
Finished	Aug 14 04:37:29 PM PDT 24
Peak memory	216012 kb
Host	smart-f4ca3623-126c-4ec5-bba5-88edc705ab7d
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976654700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.97665470 0 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_aliasing/latest

---

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.2568682867
Short name	T72
Test name
Test status
Simulation time	504965679 ps
CPU time	10.18 seconds
Started	Aug 14 04:37:09 PM PDT 24
Finished	Aug 14 04:37:19 PM PDT 24
Peak memory	216156 kb
Host	smart-c4e4c62e-2924-4809-93cf-6f6aff9ae807
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568682867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.2568682 867 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_bit_bash/latest

---

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2155225693
Short name	T103
Test name
Test status
Simulation time	19672782 ps
CPU time	1.06 seconds
Started	Aug 14 04:37:44 PM PDT 24
Finished	Aug 14 04:37:45 PM PDT 24
Peak memory	216108 kb
Host	smart-4dedbda3-27e5-423a-b3f5-fa2a7ed64513
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155225693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.2155225 693 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_hw_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.668669277
Short name	T201
Test name
Test status
Simulation time	36399246 ps
CPU time	2.54 seconds
Started	Aug 14 04:37:19 PM PDT 24
Finished	Aug 14 04:37:21 PM PDT 24
Peak memory	221172 kb
Host	smart-648f6cc8-b652-4b8f-8ade-0c8048106fd3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668669277 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.668669277 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_rw.1258861173
Short name	T112
Test name
Test status
Simulation time	48968315 ps
CPU time	1.08 seconds
Started	Aug 14 04:37:47 PM PDT 24
Finished	Aug 14 04:37:48 PM PDT 24
Peak memory	216044 kb
Host	smart-c99ae785-f53e-40e4-95c1-c83796ff448c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258861173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.1258861173 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.2686755901
Short name	T29
Test name
Test status
Simulation time	159991040 ps
CPU time	1.51 seconds
Started	Aug 14 04:37:34 PM PDT 24
Finished	Aug 14 04:37:36 PM PDT 24
Peak memory	216008 kb
Host	smart-b0dbd256-0119-49b8-8504-7153f79e32c0
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686755901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia l_access.2686755901 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_mem_partial_access/latest

---

Test location	/workspace/coverage/cover_reg_top/1.kmac_mem_walk.2874603647
Short name	T110
Test name
Test status
Simulation time	66370351 ps
CPU time	0.74 seconds
Started	Aug 14 04:37:08 PM PDT 24
Finished	Aug 14 04:37:09 PM PDT 24
Peak memory	215832 kb
Host	smart-9809d98c-62c3-4a25-981a-469dbe4e860b
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874603647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.2874603647 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_mem_walk/latest

---

Test location	/workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.815060373
Short name	T94
Test name
Test status
Simulation time	45454348 ps
CPU time	1.52 seconds
Started	Aug 14 04:37:13 PM PDT 24
Finished	Aug 14 04:37:14 PM PDT 24
Peak memory	216076 kb
Host	smart-68dc02e9-d114-46d4-86ca-ef47294b1b38
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815060373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_ outstanding.815060373 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.1731770290
Short name	T118
Test name
Test status
Simulation time	37870810 ps
CPU time	1.1 seconds
Started	Aug 14 04:37:26 PM PDT 24
Finished	Aug 14 04:37:27 PM PDT 24
Peak memory	216112 kb
Host	smart-94abf7c3-8a12-4acb-9e97-d71a8eaf7ac8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731770290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_ errors.1731770290 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.1927412479
Short name	T116
Test name
Test status
Simulation time	169237932 ps
CPU time	1.62 seconds
Started	Aug 14 04:37:28 PM PDT 24
Finished	Aug 14 04:37:30 PM PDT 24
Peak memory	216012 kb
Host	smart-e8dcdd58-9a26-4f85-8047-83fe5be54215
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927412479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac _shadow_reg_errors_with_csr_rw.1927412479 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/1.kmac_tl_errors.3086931249
Short name	T152
Test name
Test status
Simulation time	242090038 ps
CPU time	3.46 seconds
Started	Aug 14 04:37:07 PM PDT 24
Finished	Aug 14 04:37:10 PM PDT 24
Peak memory	216156 kb
Host	smart-7a3f4d1f-a122-48ea-b909-fcd0fe1432ce
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086931249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.3086931249 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.2410588834
Short name	T178
Test name
Test status
Simulation time	202565866 ps
CPU time	2.47 seconds
Started	Aug 14 04:37:26 PM PDT 24
Finished	Aug 14 04:37:29 PM PDT 24
Peak memory	216012 kb
Host	smart-ff98bf69-fa34-4a80-a28a-da26eaecda7c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410588834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.24105 88834 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.832359554
Short name	T158
Test name
Test status
Simulation time	38828624 ps
CPU time	1.49 seconds
Started	Aug 14 04:37:37 PM PDT 24
Finished	Aug 14 04:37:44 PM PDT 24
Peak memory	219104 kb
Host	smart-8759524d-4f67-494a-9b77-1c544b949077
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832359554 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.832359554 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/10.kmac_csr_rw.3420030103
Short name	T98
Test name
Test status
Simulation time	26703943 ps
CPU time	1.17 seconds
Started	Aug 14 04:37:38 PM PDT 24
Finished	Aug 14 04:37:39 PM PDT 24
Peak memory	216008 kb
Host	smart-2facc550-7acb-4d92-af81-46505918aff3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420030103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.3420030103 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/10.kmac_intr_test.855487805
Short name	T3
Test name
Test status
Simulation time	23049745 ps
CPU time	0.77 seconds
Started	Aug 14 04:37:45 PM PDT 24
Finished	Aug 14 04:37:46 PM PDT 24
Peak memory	215860 kb
Host	smart-ba3aa3f5-758f-43a3-aab7-c22e279e8d19
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855487805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.855487805 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1811847199
Short name	T87
Test name
Test status
Simulation time	690841593 ps
CPU time	2.46 seconds
Started	Aug 14 04:37:36 PM PDT 24
Finished	Aug 14 04:37:39 PM PDT 24
Peak memory	216140 kb
Host	smart-8819910a-94f8-4361-820a-e70dbaba3aa2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811847199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs r_outstanding.1811847199 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.606217071
Short name	T54
Test name
Test status
Simulation time	25394153 ps
CPU time	1.02 seconds
Started	Aug 14 04:37:41 PM PDT 24
Finished	Aug 14 04:37:42 PM PDT 24
Peak memory	216180 kb
Host	smart-63334c09-7085-41ed-8b35-0678774cd992
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606217071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_ errors.606217071 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3248642270
Short name	T123
Test name
Test status
Simulation time	368400956 ps
CPU time	1.85 seconds
Started	Aug 14 04:37:44 PM PDT 24
Finished	Aug 14 04:37:46 PM PDT 24
Peak memory	216412 kb
Host	smart-fc065079-7059-4283-a664-ae61dc5f654d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248642270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kma c_shadow_reg_errors_with_csr_rw.3248642270 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.3387035392
Short name	T31
Test name
Test status
Simulation time	647414934 ps
CPU time	2.78 seconds
Started	Aug 14 04:37:26 PM PDT 24
Finished	Aug 14 04:37:29 PM PDT 24
Peak memory	216080 kb
Host	smart-a9a1c42c-79d3-4d5d-a98b-adfe0f1513e3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387035392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.3387 035392 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1290148700
Short name	T166
Test name
Test status
Simulation time	202723436 ps
CPU time	2.26 seconds
Started	Aug 14 04:37:38 PM PDT 24
Finished	Aug 14 04:37:40 PM PDT 24
Peak memory	220596 kb
Host	smart-d0d24998-a818-4546-bad8-fdec6184cec0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290148700 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.1290148700 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/11.kmac_csr_rw.338849621
Short name	T124
Test name
Test status
Simulation time	20629495 ps
CPU time	0.96 seconds
Started	Aug 14 04:37:17 PM PDT 24
Finished	Aug 14 04:37:23 PM PDT 24
Peak memory	215904 kb
Host	smart-407122e6-d0f6-48cc-bd5a-f3847bd00578
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338849621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.338849621 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/11.kmac_intr_test.2441734877
Short name	T192
Test name
Test status
Simulation time	39306744 ps
CPU time	0.83 seconds
Started	Aug 14 04:37:32 PM PDT 24
Finished	Aug 14 04:37:33 PM PDT 24
Peak memory	215872 kb
Host	smart-d1103982-2e2a-4eb4-914f-a9386d394899
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441734877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.2441734877 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.539889845
Short name	T206
Test name
Test status
Simulation time	215258837 ps
CPU time	1.79 seconds
Started	Aug 14 04:37:33 PM PDT 24
Finished	Aug 14 04:37:35 PM PDT 24
Peak memory	215992 kb
Host	smart-490680b0-340e-44de-8c0c-c4c6a4e20a92
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539889845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr _outstanding.539889845 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.1642288044
Short name	T53
Test name
Test status
Simulation time	48358739 ps
CPU time	1.29 seconds
Started	Aug 14 04:37:50 PM PDT 24
Finished	Aug 14 04:37:52 PM PDT 24
Peak memory	216608 kb
Host	smart-31aa5aac-9fd9-437a-a868-dd9c526cc245
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642288044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg _errors.1642288044 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.2278465296
Short name	T49
Test name
Test status
Simulation time	190021187 ps
CPU time	1.6 seconds
Started	Aug 14 04:37:45 PM PDT 24
Finished	Aug 14 04:37:46 PM PDT 24
Peak memory	216152 kb
Host	smart-cc29716b-08b8-40e9-a87f-0ba0d7685988
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278465296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kma c_shadow_reg_errors_with_csr_rw.2278465296 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.12743018
Short name	T13
Test name
Test status
Simulation time	586730822 ps
CPU time	2.98 seconds
Started	Aug 14 04:37:30 PM PDT 24
Finished	Aug 14 04:37:33 PM PDT 24
Peak memory	216100 kb
Host	smart-7b4a1ce8-6c6e-4781-acca-9a367d6048ba
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12743018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.127430 18 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1989016207
Short name	T195
Test name
Test status
Simulation time	24143222 ps
CPU time	1.44 seconds
Started	Aug 14 04:37:40 PM PDT 24
Finished	Aug 14 04:37:41 PM PDT 24
Peak memory	219564 kb
Host	smart-8b0341b2-173f-4ab6-bb74-5ce8bc370c55
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989016207 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.1989016207 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/12.kmac_csr_rw.2520875912
Short name	T99
Test name
Test status
Simulation time	70748980 ps
CPU time	0.97 seconds
Started	Aug 14 04:37:38 PM PDT 24
Finished	Aug 14 04:37:39 PM PDT 24
Peak memory	215880 kb
Host	smart-c7c6502b-cd64-452e-9c2c-39c8347b8000
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520875912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.2520875912 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/12.kmac_intr_test.2891269370
Short name	T84
Test name
Test status
Simulation time	12898271 ps
CPU time	0.8 seconds
Started	Aug 14 04:37:44 PM PDT 24
Finished	Aug 14 04:37:45 PM PDT 24
Peak memory	215804 kb
Host	smart-fa2210cc-39dc-4aa1-b6e3-66957bee2cb0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891269370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.2891269370 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3193369788
Short name	T45
Test name
Test status
Simulation time	118095534 ps
CPU time	2.12 seconds
Started	Aug 14 04:38:04 PM PDT 24
Finished	Aug 14 04:38:06 PM PDT 24
Peak memory	216172 kb
Host	smart-16aae5ff-eb50-4cae-8477-ce8e929036b5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193369788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_cs r_outstanding.3193369788 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2423851747
Short name	T191
Test name
Test status
Simulation time	19621301 ps
CPU time	1.01 seconds
Started	Aug 14 04:37:48 PM PDT 24
Finished	Aug 14 04:37:49 PM PDT 24
Peak memory	216216 kb
Host	smart-29748085-4960-4e49-a8a3-036a03a3c75d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423851747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg _errors.2423851747 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.3543541827
Short name	T114
Test name
Test status
Simulation time	194936050 ps
CPU time	2.64 seconds
Started	Aug 14 04:37:43 PM PDT 24
Finished	Aug 14 04:37:46 PM PDT 24
Peak memory	218860 kb
Host	smart-c36ae767-a68a-4a15-a3e0-5ca73b908a1c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543541827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kma c_shadow_reg_errors_with_csr_rw.3543541827 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/12.kmac_tl_errors.815450774
Short name	T161
Test name
Test status
Simulation time	130962276 ps
CPU time	2.27 seconds
Started	Aug 14 04:37:52 PM PDT 24
Finished	Aug 14 04:37:54 PM PDT 24
Peak memory	216088 kb
Host	smart-776b5659-e0d6-49ad-bbb2-0891858a4539
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815450774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.815450774 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.1876698970
Short name	T67
Test name
Test status
Simulation time	208391371 ps
CPU time	3.17 seconds
Started	Aug 14 04:37:35 PM PDT 24
Finished	Aug 14 04:37:38 PM PDT 24
Peak memory	216048 kb
Host	smart-ac67d664-2283-4160-8b3b-d8a4a27dda51
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876698970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.1876 698970 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3556227843
Short name	T106
Test name
Test status
Simulation time	96935909 ps
CPU time	1.56 seconds
Started	Aug 14 04:37:38 PM PDT 24
Finished	Aug 14 04:37:40 PM PDT 24
Peak memory	217668 kb
Host	smart-dc8df9ea-aa79-4ce0-931d-3692121a42a2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556227843 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.3556227843 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/13.kmac_csr_rw.2615260794
Short name	T164
Test name
Test status
Simulation time	63792896 ps
CPU time	1 seconds
Started	Aug 14 04:37:33 PM PDT 24
Finished	Aug 14 04:37:35 PM PDT 24
Peak memory	216000 kb
Host	smart-d81bced6-9121-49d1-95d4-7232dda767bd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615260794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.2615260794 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.2513698874
Short name	T172
Test name
Test status
Simulation time	229563468 ps
CPU time	2.56 seconds
Started	Aug 14 04:37:45 PM PDT 24
Finished	Aug 14 04:37:48 PM PDT 24
Peak memory	216116 kb
Host	smart-01fb3481-4c25-4016-a261-1e388ccb008b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513698874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs r_outstanding.2513698874 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3131671668
Short name	T102
Test name
Test status
Simulation time	35620535 ps
CPU time	1.05 seconds
Started	Aug 14 04:38:03 PM PDT 24
Finished	Aug 14 04:38:04 PM PDT 24
Peak memory	216320 kb
Host	smart-b2d995e4-de3b-442e-8fd3-b12cb7865e34
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131671668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg _errors.3131671668 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.3417346887
Short name	T5
Test name
Test status
Simulation time	355253972 ps
CPU time	2.49 seconds
Started	Aug 14 04:37:40 PM PDT 24
Finished	Aug 14 04:37:43 PM PDT 24
Peak memory	219496 kb
Host	smart-e4519de8-81e4-4894-8625-afcde9bacd11
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417346887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma c_shadow_reg_errors_with_csr_rw.3417346887 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.12340763
Short name	T34
Test name
Test status
Simulation time	470387680 ps
CPU time	2.94 seconds
Started	Aug 14 04:37:48 PM PDT 24
Finished	Aug 14 04:37:51 PM PDT 24
Peak memory	216108 kb
Host	smart-01aa7047-5e1b-4d0e-bfbf-f81037971969
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12340763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.123407 63 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.3487060652
Short name	T180
Test name
Test status
Simulation time	40416215 ps
CPU time	2.41 seconds
Started	Aug 14 04:37:35 PM PDT 24
Finished	Aug 14 04:37:38 PM PDT 24
Peak memory	220780 kb
Host	smart-e9eb9a2f-41a5-429e-9aa9-d5787d75da16
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487060652 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.3487060652 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/14.kmac_csr_rw.2190521953
Short name	T14
Test name
Test status
Simulation time	15118719 ps
CPU time	0.92 seconds
Started	Aug 14 04:37:41 PM PDT 24
Finished	Aug 14 04:37:42 PM PDT 24
Peak memory	215840 kb
Host	smart-d6bbed1c-59c8-4bc7-bbee-f14eceef3fa6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190521953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.2190521953 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.1259010691
Short name	T37
Test name
Test status
Simulation time	98552455 ps
CPU time	1.56 seconds
Started	Aug 14 04:37:31 PM PDT 24
Finished	Aug 14 04:37:33 PM PDT 24
Peak memory	216144 kb
Host	smart-1a0bc448-a719-4652-96ed-f1773bc5cec3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259010691 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_cs r_outstanding.1259010691 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.1080254204
Short name	T93
Test name
Test status
Simulation time	88322754 ps
CPU time	1.18 seconds
Started	Aug 14 04:37:50 PM PDT 24
Finished	Aug 14 04:37:51 PM PDT 24
Peak memory	216560 kb
Host	smart-1215a214-471b-445e-8afc-2680356f468d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080254204 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg _errors.1080254204 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.4126897993
Short name	T134
Test name
Test status
Simulation time	410168568 ps
CPU time	2.83 seconds
Started	Aug 14 04:37:52 PM PDT 24
Finished	Aug 14 04:37:55 PM PDT 24
Peak memory	218736 kb
Host	smart-abc392c3-0546-4e2e-8ab5-1ab27008ab7b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126897993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kma c_shadow_reg_errors_with_csr_rw.4126897993 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/14.kmac_tl_errors.71052404
Short name	T204
Test name
Test status
Simulation time	103138371 ps
CPU time	3.27 seconds
Started	Aug 14 04:37:42 PM PDT 24
Finished	Aug 14 04:37:45 PM PDT 24
Peak memory	216056 kb
Host	smart-3a4b1f2c-3358-4e2a-974d-d876071c8ce4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71052404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.71052404 +enable_mas king=1 +sw_key_masked=0
Directory	/workspace/14.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.2788581982
Short name	T96
Test name
Test status
Simulation time	283946706 ps
CPU time	2.38 seconds
Started	Aug 14 04:37:52 PM PDT 24
Finished	Aug 14 04:37:55 PM PDT 24
Peak memory	222068 kb
Host	smart-62054e5c-05ee-4aaf-acce-759221dcc864
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788581982 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.2788581982 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/15.kmac_csr_rw.1899005223
Short name	T197
Test name
Test status
Simulation time	30826784 ps
CPU time	1.22 seconds
Started	Aug 14 04:37:32 PM PDT 24
Finished	Aug 14 04:37:34 PM PDT 24
Peak memory	216016 kb
Host	smart-f65ac0f2-ceeb-40bc-a691-7c79ce06a05d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899005223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.1899005223 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/15.kmac_intr_test.2591837435
Short name	T139
Test name
Test status
Simulation time	11964643 ps
CPU time	0.79 seconds
Started	Aug 14 04:37:35 PM PDT 24
Finished	Aug 14 04:37:41 PM PDT 24
Peak memory	215864 kb
Host	smart-1b0119ba-1684-425c-96ae-3a1eb42096bf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591837435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.2591837435 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.129065074
Short name	T80
Test name
Test status
Simulation time	85026597 ps
CPU time	2.4 seconds
Started	Aug 14 04:38:10 PM PDT 24
Finished	Aug 14 04:38:13 PM PDT 24
Peak memory	216192 kb
Host	smart-2a546129-f736-418f-8f4d-08f138ca8bca
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129065074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr _outstanding.129065074 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2837045294
Short name	T146
Test name
Test status
Simulation time	33846594 ps
CPU time	1.06 seconds
Started	Aug 14 04:37:39 PM PDT 24
Finished	Aug 14 04:37:40 PM PDT 24
Peak memory	216164 kb
Host	smart-10f7abec-90ff-421d-949b-5fabde577fe4
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837045294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg _errors.2837045294 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/15.kmac_tl_errors.2377224033
Short name	T20
Test name
Test status
Simulation time	203018766 ps
CPU time	1.58 seconds
Started	Aug 14 04:37:51 PM PDT 24
Finished	Aug 14 04:37:53 PM PDT 24
Peak memory	215996 kb
Host	smart-68b1d6ee-cc44-4f70-977d-fa62c9ea0164
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377224033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.2377224033 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.343900169
Short name	T136
Test name
Test status
Simulation time	117652041 ps
CPU time	2.2 seconds
Started	Aug 14 04:37:46 PM PDT 24
Finished	Aug 14 04:37:48 PM PDT 24
Peak memory	220600 kb
Host	smart-2169f2c8-866a-4422-ac30-aa362fcdac4b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343900169 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.343900169 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/16.kmac_csr_rw.3304896829
Short name	T77
Test name
Test status
Simulation time	19156656 ps
CPU time	0.97 seconds
Started	Aug 14 04:38:19 PM PDT 24
Finished	Aug 14 04:38:20 PM PDT 24
Peak memory	215904 kb
Host	smart-4d631094-ec56-4b00-ba61-76b3a57d999d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304896829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.3304896829 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/16.kmac_intr_test.2362346333
Short name	T200
Test name
Test status
Simulation time	12973906 ps
CPU time	0.86 seconds
Started	Aug 14 04:37:58 PM PDT 24
Finished	Aug 14 04:37:59 PM PDT 24
Peak memory	215772 kb
Host	smart-b720b0e9-44c8-43c6-b601-b7da70ff1de1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362346333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.2362346333 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.3512905603
Short name	T38
Test name
Test status
Simulation time	98931876 ps
CPU time	1.67 seconds
Started	Aug 14 04:37:58 PM PDT 24
Finished	Aug 14 04:37:59 PM PDT 24
Peak memory	216000 kb
Host	smart-18b5828a-f359-44e7-9846-ee0b08e866f2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512905603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_cs r_outstanding.3512905603 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1767147233
Short name	T150
Test name
Test status
Simulation time	208158693 ps
CPU time	2.84 seconds
Started	Aug 14 04:37:40 PM PDT 24
Finished	Aug 14 04:37:43 PM PDT 24
Peak memory	219852 kb
Host	smart-5df6402c-2fec-4c8a-ae0a-579f6d9e8690
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767147233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kma c_shadow_reg_errors_with_csr_rw.1767147233 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/16.kmac_tl_errors.666180035
Short name	T60
Test name
Test status
Simulation time	91538711 ps
CPU time	2.46 seconds
Started	Aug 14 04:37:56 PM PDT 24
Finished	Aug 14 04:37:58 PM PDT 24
Peak memory	216124 kb
Host	smart-6d3be82e-917b-4f73-8718-c8a571b8d48b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666180035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.666180035 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.353846072
Short name	T66
Test name
Test status
Simulation time	192980776 ps
CPU time	4.6 seconds
Started	Aug 14 04:37:46 PM PDT 24
Finished	Aug 14 04:37:50 PM PDT 24
Peak memory	215904 kb
Host	smart-ded8466c-906c-4c60-b574-955612f0e912
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353846072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.35384 6072 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.3629720716
Short name	T127
Test name
Test status
Simulation time	60241412 ps
CPU time	1.75 seconds
Started	Aug 14 04:38:11 PM PDT 24
Finished	Aug 14 04:38:12 PM PDT 24
Peak memory	220044 kb
Host	smart-c8bd9bcd-8058-400b-813f-364892c99e97
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629720716 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.3629720716 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/17.kmac_csr_rw.2445241053
Short name	T147
Test name
Test status
Simulation time	287408010 ps
CPU time	1.04 seconds
Started	Aug 14 04:37:57 PM PDT 24
Finished	Aug 14 04:37:58 PM PDT 24
Peak memory	215900 kb
Host	smart-46db3ac6-6089-41d6-b875-dbce59644b33
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445241053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.2445241053 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/17.kmac_intr_test.3611198813
Short name	T194
Test name
Test status
Simulation time	39960219 ps
CPU time	0.79 seconds
Started	Aug 14 04:38:06 PM PDT 24
Finished	Aug 14 04:38:07 PM PDT 24
Peak memory	215764 kb
Host	smart-045c12f3-7812-41d2-ae0c-c4a5279d2900
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611198813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.3611198813 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3208211792
Short name	T113
Test name
Test status
Simulation time	36765792 ps
CPU time	2.06 seconds
Started	Aug 14 04:37:52 PM PDT 24
Finished	Aug 14 04:37:54 PM PDT 24
Peak memory	216144 kb
Host	smart-61005f50-ed24-435b-9850-998656176fa4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208211792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs r_outstanding.3208211792 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.3291116914
Short name	T205
Test name
Test status
Simulation time	114325653 ps
CPU time	1.06 seconds
Started	Aug 14 04:37:53 PM PDT 24
Finished	Aug 14 04:37:54 PM PDT 24
Peak memory	216452 kb
Host	smart-a7cb41b8-f4a6-4604-9095-eae23396d2e5
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291116914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg _errors.3291116914 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.3544359467
Short name	T50
Test name
Test status
Simulation time	401484433 ps
CPU time	2.82 seconds
Started	Aug 14 04:37:39 PM PDT 24
Finished	Aug 14 04:37:42 PM PDT 24
Peak memory	220056 kb
Host	smart-bd49f0d5-3e1f-4160-aabc-48441cfcc884
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544359467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kma c_shadow_reg_errors_with_csr_rw.3544359467 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/17.kmac_tl_errors.2546431209
Short name	T25
Test name
Test status
Simulation time	48383007 ps
CPU time	2.64 seconds
Started	Aug 14 04:37:46 PM PDT 24
Finished	Aug 14 04:37:49 PM PDT 24
Peak memory	216152 kb
Host	smart-f6ad72ad-7648-4882-9798-b710d97e2e50
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546431209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.2546431209 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.1652380108
Short name	T27
Test name
Test status
Simulation time	1347723390 ps
CPU time	3.05 seconds
Started	Aug 14 04:37:46 PM PDT 24
Finished	Aug 14 04:37:49 PM PDT 24
Peak memory	216084 kb
Host	smart-9ce457e4-6673-4d14-b0d1-0d0d8469dd02
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652380108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.1652 380108 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.4237646493
Short name	T183
Test name
Test status
Simulation time	410887771 ps
CPU time	1.68 seconds
Started	Aug 14 04:38:00 PM PDT 24
Finished	Aug 14 04:38:02 PM PDT 24
Peak memory	219372 kb
Host	smart-3a3decf5-959d-4396-b248-6fa7398c2b87
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237646493 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.4237646493 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/18.kmac_csr_rw.3965973937
Short name	T46
Test name
Test status
Simulation time	24406742 ps
CPU time	0.96 seconds
Started	Aug 14 04:37:54 PM PDT 24
Finished	Aug 14 04:37:55 PM PDT 24
Peak memory	215908 kb
Host	smart-b2a5371b-d548-4c95-bc56-818b318b3ddb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965973937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.3965973937 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/18.kmac_intr_test.3286387954
Short name	T65
Test name
Test status
Simulation time	11413079 ps
CPU time	0.77 seconds
Started	Aug 14 04:37:47 PM PDT 24
Finished	Aug 14 04:37:48 PM PDT 24
Peak memory	215724 kb
Host	smart-8da8bc67-67af-4143-bb0f-05eb64df46a1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286387954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.3286387954 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2043645277
Short name	T145
Test name
Test status
Simulation time	25892608 ps
CPU time	1.45 seconds
Started	Aug 14 04:37:55 PM PDT 24
Finished	Aug 14 04:37:57 PM PDT 24
Peak memory	216012 kb
Host	smart-57fb6f6b-0a7f-46cd-bb76-fc4ae2c1dc38
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043645277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_cs r_outstanding.2043645277 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1295428570
Short name	T56
Test name
Test status
Simulation time	880632037 ps
CPU time	1.29 seconds
Started	Aug 14 04:37:54 PM PDT 24
Finished	Aug 14 04:37:55 PM PDT 24
Peak memory	216412 kb
Host	smart-7d554c7c-013e-4839-9aec-7e8d73fe9cb4
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295428570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg _errors.1295428570 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.4273867647
Short name	T156
Test name
Test status
Simulation time	176043556 ps
CPU time	2.12 seconds
Started	Aug 14 04:37:54 PM PDT 24
Finished	Aug 14 04:37:56 PM PDT 24
Peak memory	219548 kb
Host	smart-bc344218-248c-4432-a7d9-d3fd2b44a48e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273867647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma c_shadow_reg_errors_with_csr_rw.4273867647 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/18.kmac_tl_errors.2617013374
Short name	T209
Test name
Test status
Simulation time	123766204 ps
CPU time	3.09 seconds
Started	Aug 14 04:37:42 PM PDT 24
Finished	Aug 14 04:37:45 PM PDT 24
Peak memory	216100 kb
Host	smart-ce40914e-035a-45ce-b4ce-ea6b19a3b0b9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617013374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.2617013374 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.3131115090
Short name	T82
Test name
Test status
Simulation time	187437860 ps
CPU time	2.62 seconds
Started	Aug 14 04:38:08 PM PDT 24
Finished	Aug 14 04:38:11 PM PDT 24
Peak memory	216108 kb
Host	smart-bafddc9e-acbf-4e53-9fa1-ee8119ed1426
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131115090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.3131 115090 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.3608195031
Short name	T105
Test name
Test status
Simulation time	49035249 ps
CPU time	1.58 seconds
Started	Aug 14 04:37:50 PM PDT 24
Finished	Aug 14 04:37:52 PM PDT 24
Peak memory	219580 kb
Host	smart-92370b4d-b30b-467d-836e-4de8adad5810
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608195031 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.3608195031 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/19.kmac_csr_rw.133008761
Short name	T90
Test name
Test status
Simulation time	57879215 ps
CPU time	1.04 seconds
Started	Aug 14 04:38:12 PM PDT 24
Finished	Aug 14 04:38:13 PM PDT 24
Peak memory	216140 kb
Host	smart-62d6afc7-91b5-4811-83bf-44efacf05193
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133008761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.133008761 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/19.kmac_intr_test.221329433
Short name	T165
Test name
Test status
Simulation time	41150765 ps
CPU time	0.78 seconds
Started	Aug 14 04:38:05 PM PDT 24
Finished	Aug 14 04:38:11 PM PDT 24
Peak memory	215784 kb
Host	smart-d71123df-ec38-497f-8f54-740f37a1134b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221329433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.221329433 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.3449484589
Short name	T167
Test name
Test status
Simulation time	70300547 ps
CPU time	1.77 seconds
Started	Aug 14 04:37:45 PM PDT 24
Finished	Aug 14 04:37:47 PM PDT 24
Peak memory	216108 kb
Host	smart-72269f97-8ae6-4dd1-997f-69e4e8ea6325
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449484589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_cs r_outstanding.3449484589 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.2588359942
Short name	T148
Test name
Test status
Simulation time	36771495 ps
CPU time	1.16 seconds
Started	Aug 14 04:38:10 PM PDT 24
Finished	Aug 14 04:38:12 PM PDT 24
Peak memory	216468 kb
Host	smart-1eba313c-805f-41d1-b435-887967dc8956
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588359942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg _errors.2588359942 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2845349046
Short name	T187
Test name
Test status
Simulation time	401404788 ps
CPU time	2.76 seconds
Started	Aug 14 04:37:48 PM PDT 24
Finished	Aug 14 04:37:51 PM PDT 24
Peak memory	219576 kb
Host	smart-f755dfae-e96e-4360-896e-9aef8a7ae7a4
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845349046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kma c_shadow_reg_errors_with_csr_rw.2845349046 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/19.kmac_tl_errors.3338087214
Short name	T198
Test name
Test status
Simulation time	520216000 ps
CPU time	3.38 seconds
Started	Aug 14 04:37:50 PM PDT 24
Finished	Aug 14 04:37:54 PM PDT 24
Peak memory	216152 kb
Host	smart-3614472a-2dc5-4313-8bc8-c95c846ca707
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338087214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.3338087214 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.4038611003
Short name	T199
Test name
Test status
Simulation time	204385138 ps
CPU time	2.39 seconds
Started	Aug 14 04:38:06 PM PDT 24
Finished	Aug 14 04:38:13 PM PDT 24
Peak memory	216136 kb
Host	smart-f665d27b-cf49-48e6-855a-8d046c884e5c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038611003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.4038 611003 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.3396331493
Short name	T157
Test name
Test status
Simulation time	535321300 ps
CPU time	9.89 seconds
Started	Aug 14 04:37:24 PM PDT 24
Finished	Aug 14 04:37:34 PM PDT 24
Peak memory	215996 kb
Host	smart-d216968d-f64e-4a5d-8669-fbb8a4e1f73e
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396331493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.3396331 493 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_aliasing/latest

---

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.3983065842
Short name	T89
Test name
Test status
Simulation time	294577712 ps
CPU time	8.21 seconds
Started	Aug 14 04:37:32 PM PDT 24
Finished	Aug 14 04:37:40 PM PDT 24
Peak memory	215944 kb
Host	smart-30aa24bc-c2df-4666-9eb0-fa5a48c63b17
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983065842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.3983065 842 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_bit_bash/latest

---

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.2839911531
Short name	T159
Test name
Test status
Simulation time	49472716 ps
CPU time	0.93 seconds
Started	Aug 14 04:37:03 PM PDT 24
Finished	Aug 14 04:37:04 PM PDT 24
Peak memory	215808 kb
Host	smart-0a95c0b6-cdb3-4a51-8f5c-8a5fd86e6016
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839911531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.2839911 531 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_hw_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.754842704
Short name	T160
Test name
Test status
Simulation time	80519732 ps
CPU time	1.53 seconds
Started	Aug 14 04:36:58 PM PDT 24
Finished	Aug 14 04:37:00 PM PDT 24
Peak memory	217116 kb
Host	smart-938bdbdc-9a1c-443b-9d1a-743eaa2c9930
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754842704 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.754842704 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_rw.1088387075
Short name	T215
Test name
Test status
Simulation time	31517449 ps
CPU time	1.23 seconds
Started	Aug 14 04:37:28 PM PDT 24
Finished	Aug 14 04:37:29 PM PDT 24
Peak memory	216156 kb
Host	smart-4b031322-a80e-4ea2-8f2f-5aae8a13aad7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088387075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.1088387075 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/2.kmac_intr_test.751956132
Short name	T177
Test name
Test status
Simulation time	43664583 ps
CPU time	0.77 seconds
Started	Aug 14 04:37:19 PM PDT 24
Finished	Aug 14 04:37:20 PM PDT 24
Peak memory	215720 kb
Host	smart-c37b687e-6e57-4ac6-adac-e77342e8530c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751956132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.751956132 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.595682567
Short name	T111
Test name
Test status
Simulation time	37039856 ps
CPU time	1.41 seconds
Started	Aug 14 04:37:01 PM PDT 24
Finished	Aug 14 04:37:02 PM PDT 24
Peak memory	215996 kb
Host	smart-5c229b20-adcc-4eac-be1b-0cc7f12973fd
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595682567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial _access.595682567 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_mem_partial_access/latest

---

Test location	/workspace/coverage/cover_reg_top/2.kmac_mem_walk.1258915748
Short name	T213
Test name
Test status
Simulation time	17634522 ps
CPU time	0.78 seconds
Started	Aug 14 04:37:28 PM PDT 24
Finished	Aug 14 04:37:29 PM PDT 24
Peak memory	215300 kb
Host	smart-bd32c225-9eda-4572-bbd1-2d7ab485fa5f
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258915748 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.1258915748 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_mem_walk/latest

---

Test location	/workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.1604903486
Short name	T128
Test name
Test status
Simulation time	34297255 ps
CPU time	2.06 seconds
Started	Aug 14 04:37:25 PM PDT 24
Finished	Aug 14 04:37:27 PM PDT 24
Peak memory	216196 kb
Host	smart-b830ab08-bc52-48e2-9900-cb8af617cb1c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604903486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr _outstanding.1604903486 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.4006792738
Short name	T81
Test name
Test status
Simulation time	39608047 ps
CPU time	1 seconds
Started	Aug 14 04:37:12 PM PDT 24
Finished	Aug 14 04:37:13 PM PDT 24
Peak memory	216160 kb
Host	smart-d47724d9-3456-40b7-9027-d87b9c19375c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006792738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_ errors.4006792738 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.2012895202
Short name	T12
Test name
Test status
Simulation time	105102214 ps
CPU time	1.77 seconds
Started	Aug 14 04:37:20 PM PDT 24
Finished	Aug 14 04:37:22 PM PDT 24
Peak memory	218588 kb
Host	smart-1d1c8f7f-98b6-4e7a-80ba-2e1b7e663ca0
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012895202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac _shadow_reg_errors_with_csr_rw.2012895202 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.448990586
Short name	T32
Test name
Test status
Simulation time	279949895 ps
CPU time	2.68 seconds
Started	Aug 14 04:37:24 PM PDT 24
Finished	Aug 14 04:37:27 PM PDT 24
Peak memory	216068 kb
Host	smart-5756f231-6301-4b82-ad29-04ae2b4f1bc2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448990586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.448990 586 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/20.kmac_intr_test.2873954220
Short name	T175
Test name
Test status
Simulation time	17702746 ps
CPU time	0.83 seconds
Started	Aug 14 04:37:55 PM PDT 24
Finished	Aug 14 04:37:55 PM PDT 24
Peak memory	215776 kb
Host	smart-a7710ef8-add7-4efc-9dee-08f81ab99d7d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873954220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.2873954220 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/21.kmac_intr_test.3155540318
Short name	T73
Test name
Test status
Simulation time	41804504 ps
CPU time	0.8 seconds
Started	Aug 14 04:37:52 PM PDT 24
Finished	Aug 14 04:37:53 PM PDT 24
Peak memory	215552 kb
Host	smart-ea054e04-fef6-4d1f-b9cf-47eabcc6c9ea
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155540318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.3155540318 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/22.kmac_intr_test.42966141
Short name	T184
Test name
Test status
Simulation time	41505747 ps
CPU time	0.78 seconds
Started	Aug 14 04:37:48 PM PDT 24
Finished	Aug 14 04:37:49 PM PDT 24
Peak memory	215836 kb
Host	smart-bdd99271-808b-4426-b9c5-8ebba07da326
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42966141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.42966141 +enable_mas king=1 +sw_key_masked=0
Directory	/workspace/22.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/23.kmac_intr_test.2582331630
Short name	T79
Test name
Test status
Simulation time	26375848 ps
CPU time	0.81 seconds
Started	Aug 14 04:37:54 PM PDT 24
Finished	Aug 14 04:37:55 PM PDT 24
Peak memory	215792 kb
Host	smart-a0c286e8-e5df-4025-8373-6b3c77a5e6bd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582331630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.2582331630 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/24.kmac_intr_test.1651298307
Short name	T169
Test name
Test status
Simulation time	13256614 ps
CPU time	0.78 seconds
Started	Aug 14 04:37:46 PM PDT 24
Finished	Aug 14 04:37:47 PM PDT 24
Peak memory	215728 kb
Host	smart-6a1518b7-eb8d-43bb-8bb4-3905e92f582c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651298307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.1651298307 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/25.kmac_intr_test.4184601912
Short name	T88
Test name
Test status
Simulation time	19922203 ps
CPU time	0.78 seconds
Started	Aug 14 04:37:52 PM PDT 24
Finished	Aug 14 04:37:53 PM PDT 24
Peak memory	215848 kb
Host	smart-b4253b29-53c4-4383-8583-db9afdcdfc2f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184601912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.4184601912 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/26.kmac_intr_test.701313972
Short name	T119
Test name
Test status
Simulation time	14151375 ps
CPU time	0.8 seconds
Started	Aug 14 04:37:49 PM PDT 24
Finished	Aug 14 04:37:50 PM PDT 24
Peak memory	215736 kb
Host	smart-a5976442-e53a-4a5d-847f-5e5e2021952c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701313972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.701313972 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/27.kmac_intr_test.1649302333
Short name	T138
Test name
Test status
Simulation time	22083529 ps
CPU time	0.78 seconds
Started	Aug 14 04:37:57 PM PDT 24
Finished	Aug 14 04:37:58 PM PDT 24
Peak memory	215640 kb
Host	smart-b1f05ce6-114d-4653-89f6-21d0c5563e46
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649302333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.1649302333 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/28.kmac_intr_test.506882627
Short name	T104
Test name
Test status
Simulation time	35253690 ps
CPU time	0.79 seconds
Started	Aug 14 04:37:51 PM PDT 24
Finished	Aug 14 04:37:52 PM PDT 24
Peak memory	215836 kb
Host	smart-b7b64f20-f011-4ef1-9c80-91b0408cbdd4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506882627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.506882627 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/29.kmac_intr_test.1189576882
Short name	T76
Test name
Test status
Simulation time	41748887 ps
CPU time	0.79 seconds
Started	Aug 14 04:37:50 PM PDT 24
Finished	Aug 14 04:37:51 PM PDT 24
Peak memory	215752 kb
Host	smart-e0b64c35-17ce-4678-8ee8-3380a5a9000f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189576882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.1189576882 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.100906088
Short name	T186
Test name
Test status
Simulation time	272829874 ps
CPU time	7.97 seconds
Started	Aug 14 04:37:44 PM PDT 24
Finished	Aug 14 04:37:52 PM PDT 24
Peak memory	216164 kb
Host	smart-f7959d41-6c7a-40e0-98d7-6c4b9a2a21de
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100906088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.10090608 8 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_aliasing/latest

---

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.3636379259
Short name	T208
Test name
Test status
Simulation time	1929779804 ps
CPU time	10.04 seconds
Started	Aug 14 04:37:26 PM PDT 24
Finished	Aug 14 04:37:36 PM PDT 24
Peak memory	216020 kb
Host	smart-e166b11a-946d-42aa-8d23-192b99e7721b
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636379259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.3636379 259 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_bit_bash/latest

---

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.3943312765
Short name	T91
Test name
Test status
Simulation time	91964283 ps
CPU time	1.14 seconds
Started	Aug 14 04:37:04 PM PDT 24
Finished	Aug 14 04:37:06 PM PDT 24
Peak memory	216052 kb
Host	smart-739a53a2-ef73-4b11-aa74-fa95b9a17d9e
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943312765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.3943312 765 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_hw_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.208408246
Short name	T23
Test name
Test status
Simulation time	102218788 ps
CPU time	1.86 seconds
Started	Aug 14 04:37:30 PM PDT 24
Finished	Aug 14 04:37:32 PM PDT 24
Peak memory	217536 kb
Host	smart-f70137d0-174e-444d-bfc2-3c43c9dcb773
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208408246 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.208408246 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_rw.3943387849
Short name	T129
Test name
Test status
Simulation time	93205305 ps
CPU time	1.14 seconds
Started	Aug 14 04:37:26 PM PDT 24
Finished	Aug 14 04:37:27 PM PDT 24
Peak memory	216100 kb
Host	smart-7d596793-0ba9-44d8-a89e-18269083e344
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943387849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.3943387849 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/3.kmac_intr_test.3791904268
Short name	T203
Test name
Test status
Simulation time	25526956 ps
CPU time	0.87 seconds
Started	Aug 14 04:37:35 PM PDT 24
Finished	Aug 14 04:37:36 PM PDT 24
Peak memory	215764 kb
Host	smart-41a9836c-8247-4644-b07c-884c0e57d79c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791904268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.3791904268 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.596755440
Short name	T19
Test name
Test status
Simulation time	36612140 ps
CPU time	1.47 seconds
Started	Aug 14 04:37:39 PM PDT 24
Finished	Aug 14 04:37:40 PM PDT 24
Peak memory	216024 kb
Host	smart-be133336-98a2-4384-ba7c-b900a282d395
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596755440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial _access.596755440 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_mem_partial_access/latest

---

Test location	/workspace/coverage/cover_reg_top/3.kmac_mem_walk.134863853
Short name	T71
Test name
Test status
Simulation time	33869330 ps
CPU time	0.72 seconds
Started	Aug 14 04:37:15 PM PDT 24
Finished	Aug 14 04:37:16 PM PDT 24
Peak memory	215800 kb
Host	smart-c9414bd5-4f14-47a0-9dec-772164baaa0d
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134863853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.134863853 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_mem_walk/latest

---

Test location	/workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.1399898672
Short name	T130
Test name
Test status
Simulation time	108450542 ps
CPU time	2.06 seconds
Started	Aug 14 04:37:17 PM PDT 24
Finished	Aug 14 04:37:19 PM PDT 24
Peak memory	216052 kb
Host	smart-b05a658b-a738-4d7a-a28e-61c2cebe2615
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399898672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr _outstanding.1399898672 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.4213341241
Short name	T107
Test name
Test status
Simulation time	29040857 ps
CPU time	1.21 seconds
Started	Aug 14 04:37:04 PM PDT 24
Finished	Aug 14 04:37:05 PM PDT 24
Peak memory	217368 kb
Host	smart-1db37d8a-0204-432d-8bd0-382e5dadfc70
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213341241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_ errors.4213341241 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.2254250798
Short name	T51
Test name
Test status
Simulation time	52809081 ps
CPU time	1.68 seconds
Started	Aug 14 04:37:08 PM PDT 24
Finished	Aug 14 04:37:10 PM PDT 24
Peak memory	218284 kb
Host	smart-ac2ba287-3b15-47b6-83e2-f9eab7224e57
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254250798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac _shadow_reg_errors_with_csr_rw.2254250798 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/3.kmac_tl_errors.614475075
Short name	T24
Test name
Test status
Simulation time	107683706 ps
CPU time	1.99 seconds
Started	Aug 14 04:37:31 PM PDT 24
Finished	Aug 14 04:37:33 PM PDT 24
Peak memory	216112 kb
Host	smart-9e3a73ec-5f27-46e8-a076-b26ebaca6a69
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614475075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.614475075 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.2557909483
Short name	T4
Test name
Test status
Simulation time	240702970 ps
CPU time	4.67 seconds
Started	Aug 14 04:36:58 PM PDT 24
Finished	Aug 14 04:37:02 PM PDT 24
Peak memory	216076 kb
Host	smart-c6ce6703-2f6d-4712-927a-9bc4497844ca
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557909483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.25579 09483 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/30.kmac_intr_test.1517136931
Short name	T207
Test name
Test status
Simulation time	15320232 ps
CPU time	0.77 seconds
Started	Aug 14 04:37:54 PM PDT 24
Finished	Aug 14 04:37:55 PM PDT 24
Peak memory	215460 kb
Host	smart-682d41e8-f996-4d1c-9ddd-e26dd929a1f5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517136931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.1517136931 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/31.kmac_intr_test.600587183
Short name	T78
Test name
Test status
Simulation time	23084695 ps
CPU time	0.81 seconds
Started	Aug 14 04:38:11 PM PDT 24
Finished	Aug 14 04:38:12 PM PDT 24
Peak memory	215856 kb
Host	smart-3d712fb3-d066-4d2f-ac9e-b36068a4567e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600587183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.600587183 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/32.kmac_intr_test.2832065001
Short name	T163
Test name
Test status
Simulation time	18584802 ps
CPU time	0.79 seconds
Started	Aug 14 04:37:54 PM PDT 24
Finished	Aug 14 04:37:55 PM PDT 24
Peak memory	215832 kb
Host	smart-d61ae127-63fd-43e7-8f79-f0ba4007e6af
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832065001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.2832065001 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/33.kmac_intr_test.1378223213
Short name	T182
Test name
Test status
Simulation time	15112150 ps
CPU time	0.77 seconds
Started	Aug 14 04:37:47 PM PDT 24
Finished	Aug 14 04:37:48 PM PDT 24
Peak memory	215752 kb
Host	smart-e24853ec-70cb-40d2-8a44-544316d4ea29
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378223213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.1378223213 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/34.kmac_intr_test.675463552
Short name	T95
Test name
Test status
Simulation time	49513404 ps
CPU time	0.81 seconds
Started	Aug 14 04:38:39 PM PDT 24
Finished	Aug 14 04:38:40 PM PDT 24
Peak memory	215804 kb
Host	smart-2d864917-b55e-4dfc-8363-2b2fa265eabd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675463552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.675463552 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/35.kmac_intr_test.2672255370
Short name	T162
Test name
Test status
Simulation time	111247938 ps
CPU time	0.79 seconds
Started	Aug 14 04:38:20 PM PDT 24
Finished	Aug 14 04:38:21 PM PDT 24
Peak memory	215756 kb
Host	smart-6e3e024d-6f87-448c-b9a6-355ce5d160d4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672255370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.2672255370 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/36.kmac_intr_test.414694465
Short name	T70
Test name
Test status
Simulation time	19829791 ps
CPU time	0.82 seconds
Started	Aug 14 04:38:01 PM PDT 24
Finished	Aug 14 04:38:01 PM PDT 24
Peak memory	215824 kb
Host	smart-399329d3-7a63-4177-a001-027c4ff7835a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414694465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.414694465 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/37.kmac_intr_test.375940526
Short name	T149
Test name
Test status
Simulation time	13459411 ps
CPU time	0.78 seconds
Started	Aug 14 04:37:48 PM PDT 24
Finished	Aug 14 04:37:49 PM PDT 24
Peak memory	215880 kb
Host	smart-198e4d0e-6a27-4d7a-a55b-bdd202716c57
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375940526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.375940526 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/38.kmac_intr_test.2815695995
Short name	T100
Test name
Test status
Simulation time	14534205 ps
CPU time	0.82 seconds
Started	Aug 14 04:37:42 PM PDT 24
Finished	Aug 14 04:37:42 PM PDT 24
Peak memory	215896 kb
Host	smart-628b69df-d316-42e8-afb7-a2bd75b9c28e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815695995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.2815695995 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/39.kmac_intr_test.1829027142
Short name	T211
Test name
Test status
Simulation time	12422708 ps
CPU time	0.78 seconds
Started	Aug 14 04:38:17 PM PDT 24
Finished	Aug 14 04:38:18 PM PDT 24
Peak memory	215736 kb
Host	smart-0a65651b-eb0d-4a7c-affe-4073bd002136
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829027142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.1829027142 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.3228910993
Short name	T126
Test name
Test status
Simulation time	289454463 ps
CPU time	4.67 seconds
Started	Aug 14 04:37:31 PM PDT 24
Finished	Aug 14 04:37:35 PM PDT 24
Peak memory	216000 kb
Host	smart-04b0396c-b21a-4e9a-aa57-9b6b4c2a32cd
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228910993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.3228910 993 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_aliasing/latest

---

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.1023431287
Short name	T214
Test name
Test status
Simulation time	3696879815 ps
CPU time	19.08 seconds
Started	Aug 14 04:37:26 PM PDT 24
Finished	Aug 14 04:37:45 PM PDT 24
Peak memory	216172 kb
Host	smart-09fc47d5-6bcf-4ac8-8362-06d1af90c3f4
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023431287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.1023431 287 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_bit_bash/latest

---

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.3670527868
Short name	T132
Test name
Test status
Simulation time	85273172 ps
CPU time	0.95 seconds
Started	Aug 14 04:37:34 PM PDT 24
Finished	Aug 14 04:37:36 PM PDT 24
Peak memory	215800 kb
Host	smart-243e901f-4816-4a68-ad59-3f42536e075e
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670527868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.3670527 868 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_hw_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.670467848
Short name	T17
Test name
Test status
Simulation time	251277385 ps
CPU time	1.51 seconds
Started	Aug 14 04:37:17 PM PDT 24
Finished	Aug 14 04:37:19 PM PDT 24
Peak memory	217300 kb
Host	smart-bf344119-e50d-49e6-880a-8f9b01b401fc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670467848 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.670467848 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_rw.3653975358
Short name	T40
Test name
Test status
Simulation time	77020894 ps
CPU time	0.98 seconds
Started	Aug 14 04:37:49 PM PDT 24
Finished	Aug 14 04:37:50 PM PDT 24
Peak memory	215804 kb
Host	smart-3ed40562-be39-4321-b002-849b439291e2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653975358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.3653975358 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/4.kmac_intr_test.610906735
Short name	T176
Test name
Test status
Simulation time	18144908 ps
CPU time	0.75 seconds
Started	Aug 14 04:37:31 PM PDT 24
Finished	Aug 14 04:37:32 PM PDT 24
Peak memory	215856 kb
Host	smart-afbe4df9-7707-4893-aaf0-7d2711ea975f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610906735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.610906735 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/4.kmac_mem_walk.702281581
Short name	T202
Test name
Test status
Simulation time	11502067 ps
CPU time	0.78 seconds
Started	Aug 14 04:37:34 PM PDT 24
Finished	Aug 14 04:37:35 PM PDT 24
Peak memory	215784 kb
Host	smart-74a62cf7-8269-439a-8286-4589b04f361b
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702281581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.702281581 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_mem_walk/latest

---

Test location	/workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.2658992314
Short name	T120
Test name
Test status
Simulation time	439252574 ps
CPU time	2.57 seconds
Started	Aug 14 04:37:27 PM PDT 24
Finished	Aug 14 04:37:30 PM PDT 24
Peak memory	216084 kb
Host	smart-7f870243-b13d-4726-b426-1d7298b20537
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658992314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr _outstanding.2658992314 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.1022312856
Short name	T115
Test name
Test status
Simulation time	43450689 ps
CPU time	1.03 seconds
Started	Aug 14 04:37:44 PM PDT 24
Finished	Aug 14 04:37:45 PM PDT 24
Peak memory	215928 kb
Host	smart-f6118a60-01cb-4e90-9526-3dbf8fafd77a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022312856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_ errors.1022312856 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.1612228741
Short name	T117
Test name
Test status
Simulation time	193676335 ps
CPU time	2.59 seconds
Started	Aug 14 04:37:34 PM PDT 24
Finished	Aug 14 04:37:37 PM PDT 24
Peak memory	218676 kb
Host	smart-6ba34472-db87-4f28-befa-1d8ab62a69f7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612228741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac _shadow_reg_errors_with_csr_rw.1612228741 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/4.kmac_tl_errors.3463922070
Short name	T153
Test name
Test status
Simulation time	57202474 ps
CPU time	3.19 seconds
Started	Aug 14 04:37:39 PM PDT 24
Finished	Aug 14 04:37:43 PM PDT 24
Peak memory	216232 kb
Host	smart-a77f2abc-1839-4a9b-bdd3-a09ba5ce80e8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463922070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.3463922070 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.4148483286
Short name	T30
Test name
Test status
Simulation time	306264932 ps
CPU time	4.59 seconds
Started	Aug 14 04:37:37 PM PDT 24
Finished	Aug 14 04:37:42 PM PDT 24
Peak memory	215948 kb
Host	smart-7a7b21b6-ee93-4860-92cb-a931c555febd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148483286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.41484 83286 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/40.kmac_intr_test.2204324871
Short name	T144
Test name
Test status
Simulation time	38024380 ps
CPU time	0.8 seconds
Started	Aug 14 04:37:46 PM PDT 24
Finished	Aug 14 04:37:47 PM PDT 24
Peak memory	215844 kb
Host	smart-6e460588-7559-408b-9538-e16d45e14113
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204324871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.2204324871 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/41.kmac_intr_test.218062829
Short name	T170
Test name
Test status
Simulation time	14880690 ps
CPU time	0.82 seconds
Started	Aug 14 04:37:43 PM PDT 24
Finished	Aug 14 04:37:44 PM PDT 24
Peak memory	215560 kb
Host	smart-e528bb23-459f-44fd-987c-cda1853c75c5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218062829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.218062829 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/42.kmac_intr_test.1559583625
Short name	T125
Test name
Test status
Simulation time	31411768 ps
CPU time	0.82 seconds
Started	Aug 14 04:37:48 PM PDT 24
Finished	Aug 14 04:37:49 PM PDT 24
Peak memory	215772 kb
Host	smart-507adc56-ae03-4af2-b259-feff43dbf1b5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559583625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.1559583625 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/43.kmac_intr_test.4002526174
Short name	T69
Test name
Test status
Simulation time	13789398 ps
CPU time	0.78 seconds
Started	Aug 14 04:37:45 PM PDT 24
Finished	Aug 14 04:37:46 PM PDT 24
Peak memory	215496 kb
Host	smart-fcd0276b-ff8d-4d9d-bc55-fe05327b8256
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002526174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.4002526174 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/44.kmac_intr_test.51476169
Short name	T121
Test name
Test status
Simulation time	44201970 ps
CPU time	0.75 seconds
Started	Aug 14 04:37:46 PM PDT 24
Finished	Aug 14 04:37:47 PM PDT 24
Peak memory	215824 kb
Host	smart-481fd9a2-93e6-4c10-b877-58d6e496575a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51476169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.51476169 +enable_mas king=1 +sw_key_masked=0
Directory	/workspace/44.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/45.kmac_intr_test.2700162919
Short name	T44
Test name
Test status
Simulation time	57017138 ps
CPU time	0.8 seconds
Started	Aug 14 04:37:45 PM PDT 24
Finished	Aug 14 04:37:46 PM PDT 24
Peak memory	215736 kb
Host	smart-8afecd72-9447-4183-be7b-e3121bef3e10
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700162919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.2700162919 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/46.kmac_intr_test.3451123703
Short name	T64
Test name
Test status
Simulation time	19295662 ps
CPU time	0.78 seconds
Started	Aug 14 04:37:43 PM PDT 24
Finished	Aug 14 04:37:43 PM PDT 24
Peak memory	215836 kb
Host	smart-058fd817-b63a-457c-9373-63b1b77136bf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451123703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.3451123703 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/47.kmac_intr_test.3799856663
Short name	T109
Test name
Test status
Simulation time	121680005 ps
CPU time	0.81 seconds
Started	Aug 14 04:37:50 PM PDT 24
Finished	Aug 14 04:37:51 PM PDT 24
Peak memory	215844 kb
Host	smart-9236444b-ee1a-43fe-b19f-b7574eab6359
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799856663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.3799856663 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/48.kmac_intr_test.4100189361
Short name	T62
Test name
Test status
Simulation time	13241135 ps
CPU time	0.77 seconds
Started	Aug 14 04:37:52 PM PDT 24
Finished	Aug 14 04:37:52 PM PDT 24
Peak memory	215760 kb
Host	smart-f3a3facb-ea0f-4982-8faa-48578209afe7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100189361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.4100189361 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/49.kmac_intr_test.4156203967
Short name	T43
Test name
Test status
Simulation time	37289417 ps
CPU time	0.78 seconds
Started	Aug 14 04:37:50 PM PDT 24
Finished	Aug 14 04:37:51 PM PDT 24
Peak memory	215724 kb
Host	smart-19a17d60-4d33-4dc8-bbf1-aad4ecca018d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156203967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.4156203967 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.411990430
Short name	T141
Test name
Test status
Simulation time	148010323 ps
CPU time	1.67 seconds
Started	Aug 14 04:37:32 PM PDT 24
Finished	Aug 14 04:37:33 PM PDT 24
Peak memory	220748 kb
Host	smart-1de14a66-c8b4-4f42-9fec-a8fc5454e751
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411990430 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.411990430 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/5.kmac_csr_rw.1103821162
Short name	T174
Test name
Test status
Simulation time	100927813 ps
CPU time	1.17 seconds
Started	Aug 14 04:37:29 PM PDT 24
Finished	Aug 14 04:37:30 PM PDT 24
Peak memory	216044 kb
Host	smart-58b03f0f-381e-43fb-8428-d56483f187d0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103821162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.1103821162 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/5.kmac_intr_test.4053608069
Short name	T131
Test name
Test status
Simulation time	39776833 ps
CPU time	0.81 seconds
Started	Aug 14 04:37:43 PM PDT 24
Finished	Aug 14 04:37:44 PM PDT 24
Peak memory	215776 kb
Host	smart-8412f7d0-2a93-4953-aa04-649b7f564a17
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053608069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.4053608069 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.2106995414
Short name	T173
Test name
Test status
Simulation time	461753670 ps
CPU time	2.65 seconds
Started	Aug 14 04:37:36 PM PDT 24
Finished	Aug 14 04:37:39 PM PDT 24
Peak memory	216104 kb
Host	smart-c4fdd9db-2f25-4baa-9e9a-d8d24a364bba
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106995414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr _outstanding.2106995414 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.3370615233
Short name	T171
Test name
Test status
Simulation time	67784844 ps
CPU time	0.8 seconds
Started	Aug 14 04:37:25 PM PDT 24
Finished	Aug 14 04:37:26 PM PDT 24
Peak memory	215772 kb
Host	smart-60fe38ba-5558-47bb-af74-09200eeadefd
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370615233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_ errors.3370615233 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.3753061068
Short name	T135
Test name
Test status
Simulation time	123102299 ps
CPU time	2.27 seconds
Started	Aug 14 04:37:33 PM PDT 24
Finished	Aug 14 04:37:35 PM PDT 24
Peak memory	216420 kb
Host	smart-70556d2f-aa0e-4251-901a-557b01120628
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753061068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac _shadow_reg_errors_with_csr_rw.3753061068 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/5.kmac_tl_errors.81562852
Short name	T188
Test name
Test status
Simulation time	305691480 ps
CPU time	2.21 seconds
Started	Aug 14 04:37:40 PM PDT 24
Finished	Aug 14 04:37:42 PM PDT 24
Peak memory	216100 kb
Host	smart-9d7ff30f-45c3-4ea6-99da-42fb380602f8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81562852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.81562852 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/5.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.2662929338
Short name	T35
Test name
Test status
Simulation time	99737166 ps
CPU time	2.49 seconds
Started	Aug 14 04:37:36 PM PDT 24
Finished	Aug 14 04:37:39 PM PDT 24
Peak memory	216248 kb
Host	smart-ffb36b01-70ec-4d1c-82cb-c235eb851f80
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662929338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.26629 29338 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.219100849
Short name	T21
Test name
Test status
Simulation time	71991761 ps
CPU time	1.58 seconds
Started	Aug 14 04:37:37 PM PDT 24
Finished	Aug 14 04:37:39 PM PDT 24
Peak memory	218960 kb
Host	smart-48a79b6b-4612-494c-af7e-9dc4cb0b7ca7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219100849 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.219100849 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/6.kmac_csr_rw.3262588955
Short name	T97
Test name
Test status
Simulation time	208705352 ps
CPU time	1.22 seconds
Started	Aug 14 04:37:19 PM PDT 24
Finished	Aug 14 04:37:21 PM PDT 24
Peak memory	216096 kb
Host	smart-904c54e9-f165-4d72-ad6b-7bd901ca8520
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262588955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.3262588955 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/6.kmac_intr_test.1625629043
Short name	T108
Test name
Test status
Simulation time	28804793 ps
CPU time	0.79 seconds
Started	Aug 14 04:37:32 PM PDT 24
Finished	Aug 14 04:37:33 PM PDT 24
Peak memory	215776 kb
Host	smart-0e8df053-568f-40ab-9402-6aa4b00f86f8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625629043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.1625629043 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.1820358136
Short name	T39
Test name
Test status
Simulation time	94533370 ps
CPU time	1.7 seconds
Started	Aug 14 04:37:34 PM PDT 24
Finished	Aug 14 04:37:36 PM PDT 24
Peak memory	216148 kb
Host	smart-284e0c89-aaf0-48ab-a2c2-6f2e82f8e370
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820358136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr _outstanding.1820358136 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.4275570066
Short name	T55
Test name
Test status
Simulation time	35303951 ps
CPU time	1.04 seconds
Started	Aug 14 04:37:28 PM PDT 24
Finished	Aug 14 04:37:29 PM PDT 24
Peak memory	216416 kb
Host	smart-4656495a-2b71-4657-928a-c00621795bc8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275570066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_ errors.4275570066 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/6.kmac_tl_errors.4157336777
Short name	T58
Test name
Test status
Simulation time	66400605 ps
CPU time	2.95 seconds
Started	Aug 14 04:37:31 PM PDT 24
Finished	Aug 14 04:37:34 PM PDT 24
Peak memory	216240 kb
Host	smart-6665dfa5-3090-4f4e-b198-3bd45a3f75ba
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157336777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.4157336777 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.975019609
Short name	T140
Test name
Test status
Simulation time	62548470 ps
CPU time	1.59 seconds
Started	Aug 14 04:37:25 PM PDT 24
Finished	Aug 14 04:37:27 PM PDT 24
Peak memory	217872 kb
Host	smart-e9b77158-ce67-446c-a161-0c6081c04048
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975019609 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.975019609 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/7.kmac_csr_rw.3713991819
Short name	T47
Test name
Test status
Simulation time	70397099 ps
CPU time	1 seconds
Started	Aug 14 04:37:29 PM PDT 24
Finished	Aug 14 04:37:31 PM PDT 24
Peak memory	215764 kb
Host	smart-cf46685b-4ef7-41b2-ac2a-da2a4155138b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713991819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.3713991819 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/7.kmac_intr_test.593512277
Short name	T83
Test name
Test status
Simulation time	17205647 ps
CPU time	0.8 seconds
Started	Aug 14 04:37:44 PM PDT 24
Finished	Aug 14 04:37:45 PM PDT 24
Peak memory	215724 kb
Host	smart-486bd48b-2b5c-4c37-9ecc-bf1cc41ceb8c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593512277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.593512277 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.334151377
Short name	T181
Test name
Test status
Simulation time	166457898 ps
CPU time	2.27 seconds
Started	Aug 14 04:37:33 PM PDT 24
Finished	Aug 14 04:37:35 PM PDT 24
Peak memory	216088 kb
Host	smart-3e4b0d22-a170-4888-bacf-77034a812e05
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334151377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_ outstanding.334151377 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.3505919542
Short name	T122
Test name
Test status
Simulation time	117508317 ps
CPU time	1.38 seconds
Started	Aug 14 04:37:45 PM PDT 24
Finished	Aug 14 04:37:46 PM PDT 24
Peak memory	216568 kb
Host	smart-88154ae9-2682-41b6-8883-16107a63fba3
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505919542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_ errors.3505919542 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/7.kmac_tl_errors.2723169317
Short name	T212
Test name
Test status
Simulation time	164772621 ps
CPU time	3.82 seconds
Started	Aug 14 04:37:45 PM PDT 24
Finished	Aug 14 04:37:49 PM PDT 24
Peak memory	216224 kb
Host	smart-13f3ef8f-fa88-4e46-9d65-956d4ad17db7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723169317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.2723169317 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.1064292518
Short name	T68
Test name
Test status
Simulation time	1375647058 ps
CPU time	4.75 seconds
Started	Aug 14 04:37:30 PM PDT 24
Finished	Aug 14 04:37:35 PM PDT 24
Peak memory	216152 kb
Host	smart-d03999b0-85f4-4fbc-89d3-da344f65a72c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064292518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.10642 92518 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2896645624
Short name	T18
Test name
Test status
Simulation time	654186769 ps
CPU time	2.4 seconds
Started	Aug 14 04:37:32 PM PDT 24
Finished	Aug 14 04:37:34 PM PDT 24
Peak memory	220916 kb
Host	smart-e4098cf7-ad37-4972-8549-d03e42352ecd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896645624 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.2896645624 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/8.kmac_csr_rw.2314219862
Short name	T193
Test name
Test status
Simulation time	115060875 ps
CPU time	1.19 seconds
Started	Aug 14 04:37:38 PM PDT 24
Finished	Aug 14 04:37:39 PM PDT 24
Peak memory	215976 kb
Host	smart-a9a68dd6-1508-48a2-93d2-4154c48ba000
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314219862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.2314219862 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/8.kmac_intr_test.709053803
Short name	T9
Test name
Test status
Simulation time	14936512 ps
CPU time	0.84 seconds
Started	Aug 14 04:37:27 PM PDT 24
Finished	Aug 14 04:37:28 PM PDT 24
Peak memory	215716 kb
Host	smart-191aab9f-35dd-4217-9701-15bfe7e9e0e4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709053803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.709053803 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.3374686684
Short name	T85
Test name
Test status
Simulation time	43383176 ps
CPU time	2.3 seconds
Started	Aug 14 04:37:42 PM PDT 24
Finished	Aug 14 04:37:44 PM PDT 24
Peak memory	216196 kb
Host	smart-46861935-d0c1-43f4-851f-e740c5e9fa7e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374686684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr _outstanding.3374686684 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.287680422
Short name	T210
Test name
Test status
Simulation time	63567063 ps
CPU time	1.06 seconds
Started	Aug 14 04:37:24 PM PDT 24
Finished	Aug 14 04:37:25 PM PDT 24
Peak memory	216312 kb
Host	smart-4e944319-2338-404c-9636-75ca541c2fc4
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287680422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_e rrors.287680422 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/8.kmac_tl_errors.3952354432
Short name	T59
Test name
Test status
Simulation time	30054129 ps
CPU time	1.82 seconds
Started	Aug 14 04:37:25 PM PDT 24
Finished	Aug 14 04:37:27 PM PDT 24
Peak memory	216172 kb
Host	smart-2d079dfb-022f-4f91-ba50-8bf72d8be88f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952354432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.3952354432 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.961431180
Short name	T155
Test name
Test status
Simulation time	330256465 ps
CPU time	3.97 seconds
Started	Aug 14 04:37:35 PM PDT 24
Finished	Aug 14 04:37:39 PM PDT 24
Peak memory	216000 kb
Host	smart-b4f18f15-c64e-463a-bffd-70f6a70bedca
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961431180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.961431 180 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2657370507
Short name	T142
Test name
Test status
Simulation time	51856491 ps
CPU time	1.75 seconds
Started	Aug 14 04:37:43 PM PDT 24
Finished	Aug 14 04:37:45 PM PDT 24
Peak memory	220460 kb
Host	smart-8643facc-6825-4fbb-9e4d-d52457d25b2e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657370507 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.2657370507 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/9.kmac_csr_rw.2335493744
Short name	T189
Test name
Test status
Simulation time	66756511 ps
CPU time	0.96 seconds
Started	Aug 14 04:37:35 PM PDT 24
Finished	Aug 14 04:37:36 PM PDT 24
Peak memory	215796 kb
Host	smart-42924c0f-6a9a-4d4c-8cf5-ee9518edf157
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335493744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.2335493744 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/9.kmac_intr_test.1323016654
Short name	T196
Test name
Test status
Simulation time	17355262 ps
CPU time	0.78 seconds
Started	Aug 14 04:37:38 PM PDT 24
Finished	Aug 14 04:37:39 PM PDT 24
Peak memory	215828 kb
Host	smart-0d8e6dd6-f6a1-4b91-a430-b10bb2ef3936
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323016654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.1323016654 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.401298854
Short name	T48
Test name
Test status
Simulation time	224918414 ps
CPU time	2.6 seconds
Started	Aug 14 04:37:24 PM PDT 24
Finished	Aug 14 04:37:26 PM PDT 24
Peak memory	216116 kb
Host	smart-da87b3a6-37f3-43f4-9bcf-8935099c200e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401298854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_ outstanding.401298854 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.2695332613
Short name	T101
Test name
Test status
Simulation time	63742441 ps
CPU time	1.23 seconds
Started	Aug 14 04:37:50 PM PDT 24
Finished	Aug 14 04:37:56 PM PDT 24
Peak memory	216316 kb
Host	smart-610bf61c-8b18-42b0-be55-d3d311ae9d46
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695332613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_ errors.2695332613 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.3822878230
Short name	T143
Test name
Test status
Simulation time	61116208 ps
CPU time	2.62 seconds
Started	Aug 14 04:37:34 PM PDT 24
Finished	Aug 14 04:37:37 PM PDT 24
Peak memory	219796 kb
Host	smart-672eb37e-96b1-4eb8-bbaf-8f0bb8a90246
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822878230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac _shadow_reg_errors_with_csr_rw.3822878230 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/9.kmac_tl_errors.567813773
Short name	T61
Test name
Test status
Simulation time	415904242 ps
CPU time	2.83 seconds
Started	Aug 14 04:37:35 PM PDT 24
Finished	Aug 14 04:37:38 PM PDT 24
Peak memory	216160 kb
Host	smart-63afd8e1-9e88-4686-ba96-6acc45af10b1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567813773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.567813773 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.2096120517
Short name	T36
Test name
Test status
Simulation time	433496662 ps
CPU time	4.21 seconds
Started	Aug 14 04:37:42 PM PDT 24
Finished	Aug 14 04:37:47 PM PDT 24
Peak memory	216068 kb
Host	smart-c631d64a-e0c8-4d4f-a6e5-8bcb3b41d6ab
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096120517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.20961 20517 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_tl_intg_err/latest