Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 284 1 T3 4 T9 7 T10 7
all_values[1] 284 1 T3 4 T9 7 T10 7
all_values[2] 284 1 T3 4 T9 7 T10 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 456 1 T3 5 T9 11 T10 11
auto[1] 396 1 T3 7 T9 10 T10 10


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 372 1 T3 6 T9 7 T10 5
auto[1] 480 1 T3 6 T9 14 T10 16


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 481 1 T3 9 T9 9 T10 10
auto[1] 371 1 T3 3 T9 12 T10 11


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 63 1 T3 2 T9 1 T10 1
all_values[0] auto[0] auto[0] auto[1] 18 1 T9 1 T10 1 T44 1
all_values[0] auto[0] auto[1] auto[0] 61 1 T3 2 T11 3 T44 1
all_values[0] auto[0] auto[1] auto[1] 32 1 T10 3 T11 1 T64 1
all_values[0] auto[1] auto[0] auto[1] 60 1 T9 4 T11 1 T43 1
all_values[0] auto[1] auto[1] auto[1] 50 1 T9 1 T10 2 T11 1
all_values[1] auto[0] auto[0] auto[0] 79 1 T3 2 T9 1 T11 1
all_values[1] auto[0] auto[1] auto[0] 74 1 T9 2 T10 1 T11 2
all_values[1] auto[1] auto[0] auto[1] 64 1 T9 1 T10 3 T43 2
all_values[1] auto[1] auto[1] auto[1] 67 1 T3 2 T9 3 T10 3
all_values[2] auto[0] auto[0] auto[0] 60 1 T9 2 T10 3 T11 2
all_values[2] auto[0] auto[0] auto[1] 31 1 T9 1 T10 1 T44 1
all_values[2] auto[0] auto[1] auto[0] 35 1 T9 1 T43 1 T65 2
all_values[2] auto[0] auto[1] auto[1] 28 1 T3 3 T11 1 T44 1
all_values[2] auto[1] auto[0] auto[1] 81 1 T3 1 T10 2 T11 3
all_values[2] auto[1] auto[1] auto[1] 49 1 T9 3 T10 1 T11 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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