Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 44526543 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 44256146 1 T1 4181 T2 60726 T3 2632



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 49308502 1 T1 3077 T2 67794 T3 3611
values[0x0] 19125962 1 T1 939 T2 16454 T3 808
values[0x1] 20348225 1 T1 931 T2 17720 T3 900



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 34187878 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 54594811 1 T1 4392 T2 70352 T3 3303



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 303214 1 T2 408 T3 15 T7 43
valid_sources[0x01] 283571 1 T2 394 T3 22 T7 39
valid_sources[0x02] 381677 1 T2 400 T3 33 T7 50
valid_sources[0x03] 534871 1 T1 1 T2 406 T3 25
valid_sources[0x04] 344366 1 T2 442 T3 25 T7 41
valid_sources[0x05] 282041 1 T2 378 T3 25 T7 31
valid_sources[0x06] 282177 1 T2 350 T3 21 T7 38
valid_sources[0x07] 341802 1 T1 2 T2 419 T3 21
valid_sources[0x08] 900061 1 T2 407 T3 25 T7 32
valid_sources[0x09] 290866 1 T2 424 T3 21 T7 38
valid_sources[0x0a] 281869 1 T2 420 T3 18 T7 35
valid_sources[0x0b] 282460 1 T1 1 T2 347 T3 24
valid_sources[0x0c] 407106 1 T1 1 T2 392 T3 25
valid_sources[0x0d] 288069 1 T2 372 T3 26 T7 36
valid_sources[0x0e] 280566 1 T2 429 T3 16 T7 42
valid_sources[0x0f] 282164 1 T2 385 T3 16 T7 37
valid_sources[0x10] 285375 1 T2 381 T3 19 T7 35
valid_sources[0x11] 284163 1 T2 433 T3 25 T7 32
valid_sources[0x12] 286377 1 T2 380 T3 29 T7 32
valid_sources[0x13] 282783 1 T2 430 T3 4 T7 55
valid_sources[0x14] 284330 1 T2 368 T3 20 T7 40
valid_sources[0x15] 508650 1 T1 1 T2 374 T3 21
valid_sources[0x16] 283392 1 T2 400 T3 21 T7 39
valid_sources[0x17] 282609 1 T2 362 T3 28 T7 41
valid_sources[0x18] 284148 1 T2 352 T3 24 T7 37
valid_sources[0x19] 285751 1 T1 1 T2 427 T3 17
valid_sources[0x1a] 284371 1 T2 400 T3 13 T7 43
valid_sources[0x1b] 282521 1 T2 380 T3 15 T7 36
valid_sources[0x1c] 283267 1 T2 403 T3 21 T7 38
valid_sources[0x1d] 404903 1 T1 1 T2 397 T3 18
valid_sources[0x1e] 505793 1 T2 410 T3 8 T7 48
valid_sources[0x1f] 289870 1 T1 4907 T2 397 T3 14
valid_sources[0x20] 281603 1 T2 378 T3 22 T7 29
valid_sources[0x21] 283711 1 T2 385 T3 18 T7 61
valid_sources[0x22] 305015 1 T2 406 T3 16 T7 50
valid_sources[0x23] 281680 1 T2 378 T3 23 T7 37
valid_sources[0x24] 413944 1 T2 454 T3 19 T7 44
valid_sources[0x25] 772683 1 T2 381 T3 26 T7 52
valid_sources[0x26] 285620 1 T2 420 T3 16 T7 42
valid_sources[0x27] 398867 1 T1 1 T2 379 T3 18
valid_sources[0x28] 281793 1 T2 389 T3 19 T7 42
valid_sources[0x29] 284400 1 T2 395 T3 22 T7 35
valid_sources[0x2a] 284953 1 T2 420 T3 19 T7 20
valid_sources[0x2b] 285267 1 T2 386 T3 23 T7 36
valid_sources[0x2c] 421248 1 T2 435 T3 23 T7 40
valid_sources[0x2d] 281430 1 T2 404 T3 19 T7 42
valid_sources[0x2e] 279647 1 T1 1 T2 357 T3 28
valid_sources[0x2f] 293394 1 T2 386 T3 23 T7 40
valid_sources[0x30] 279453 1 T2 404 T3 18 T7 34
valid_sources[0x31] 280104 1 T2 382 T3 25 T7 28
valid_sources[0x32] 282371 1 T2 366 T3 26 T7 36
valid_sources[0x33] 334659 1 T2 421 T3 27 T7 42
valid_sources[0x34] 284916 1 T2 402 T3 17 T7 37
valid_sources[0x35] 278991 1 T2 378 T3 26 T7 40
valid_sources[0x36] 284318 1 T2 418 T3 31 T7 43
valid_sources[0x37] 282717 1 T2 404 T3 20 T7 43
valid_sources[0x38] 285779 1 T2 402 T3 22 T7 32
valid_sources[0x39] 283280 1 T2 392 T3 20 T7 42
valid_sources[0x3a] 282683 1 T2 402 T3 28 T7 46
valid_sources[0x3b] 285178 1 T2 354 T3 20 T7 54
valid_sources[0x3c] 284520 1 T2 399 T3 16 T7 37
valid_sources[0x3d] 285401 1 T2 381 T3 25 T7 50
valid_sources[0x3e] 640549 1 T2 427 T3 25 T7 45
valid_sources[0x3f] 282581 1 T2 400 T3 24 T7 36
valid_sources[0x40] 284472 1 T2 415 T3 17 T7 51
valid_sources[0x41] 318657 1 T2 417 T3 14 T7 32
valid_sources[0x42] 282753 1 T2 415 T3 16 T7 49
valid_sources[0x43] 284217 1 T2 426 T3 20 T7 29
valid_sources[0x44] 280645 1 T2 425 T3 21 T7 30
valid_sources[0x45] 286076 1 T2 376 T3 12 T7 35
valid_sources[0x46] 282047 1 T2 410 T3 30 T7 22
valid_sources[0x47] 708149 1 T1 1 T2 385 T3 10
valid_sources[0x48] 290375 1 T1 1 T2 412 T3 29
valid_sources[0x49] 281484 1 T2 385 T3 22 T7 36
valid_sources[0x4a] 379499 1 T2 417 T3 13 T7 30
valid_sources[0x4b] 284231 1 T2 440 T3 23 T7 39
valid_sources[0x4c] 289801 1 T2 397 T3 20 T7 43
valid_sources[0x4d] 312499 1 T2 403 T3 24 T7 34
valid_sources[0x4e] 300663 1 T2 385 T3 13 T7 42
valid_sources[0x4f] 281023 1 T2 360 T3 17 T7 39
valid_sources[0x50] 277215 1 T2 433 T3 23 T7 39
valid_sources[0x51] 283676 1 T1 1 T2 368 T3 20
valid_sources[0x52] 284996 1 T1 1 T2 401 T3 23
valid_sources[0x53] 284681 1 T2 388 T3 14 T7 38
valid_sources[0x54] 280143 1 T2 374 T3 22 T7 49
valid_sources[0x55] 282272 1 T1 1 T2 400 T3 18
valid_sources[0x56] 279678 1 T2 380 T3 9 T7 36
valid_sources[0x57] 539387 1 T2 390 T3 22 T7 29
valid_sources[0x58] 289436 1 T2 387 T3 14 T7 45
valid_sources[0x59] 286506 1 T2 378 T3 21 T7 46
valid_sources[0x5a] 288824 1 T2 388 T3 21 T7 36
valid_sources[0x5b] 408718 1 T1 1 T2 418 T3 20
valid_sources[0x5c] 283800 1 T2 394 T3 13 T7 34
valid_sources[0x5d] 281713 1 T1 1 T2 384 T3 23
valid_sources[0x5e] 922137 1 T1 1 T2 434 T3 16
valid_sources[0x5f] 279281 1 T2 388 T3 28 T7 29
valid_sources[0x60] 433288 1 T2 385 T3 13 T7 39
valid_sources[0x61] 361744 1 T2 392 T3 18 T7 28
valid_sources[0x62] 282854 1 T2 393 T3 24 T7 40
valid_sources[0x63] 281654 1 T2 402 T3 27 T7 38
valid_sources[0x64] 285401 1 T2 388 T3 30 T7 43
valid_sources[0x65] 282524 1 T2 413 T3 16 T7 28
valid_sources[0x66] 279907 1 T2 380 T3 23 T7 41
valid_sources[0x67] 404652 1 T2 374 T3 29 T7 19
valid_sources[0x68] 282736 1 T2 419 T3 20 T7 31
valid_sources[0x69] 283212 1 T2 400 T3 16 T7 34
valid_sources[0x6a] 279725 1 T2 412 T3 18 T7 46
valid_sources[0x6b] 278991 1 T2 402 T3 23 T7 53
valid_sources[0x6c] 281552 1 T1 1 T2 350 T3 24
valid_sources[0x6d] 346022 1 T1 2 T2 373 T3 21
valid_sources[0x6e] 285260 1 T2 388 T3 23 T7 37
valid_sources[0x6f] 284359 1 T1 1 T2 362 T3 23
valid_sources[0x70] 284188 1 T2 403 T3 20 T7 33
valid_sources[0x71] 282529 1 T2 388 T3 21 T7 39
valid_sources[0x72] 436070 1 T2 415 T3 21 T7 42
valid_sources[0x73] 527770 1 T2 408 T3 27 T7 39
valid_sources[0x74] 340164 1 T2 417 T3 31 T7 31
valid_sources[0x75] 279688 1 T2 372 T3 24 T7 39
valid_sources[0x76] 277721 1 T2 390 T3 27 T7 36
valid_sources[0x77] 280384 1 T2 381 T3 17 T7 43
valid_sources[0x78] 278564 1 T2 389 T3 24 T7 40
valid_sources[0x79] 283090 1 T2 410 T3 22 T7 22
valid_sources[0x7a] 284316 1 T2 404 T3 15 T7 36
valid_sources[0x7b] 1209682 1 T2 421 T3 22 T7 30
valid_sources[0x7c] 350341 1 T2 389 T3 21 T7 48
valid_sources[0x7d] 459610 1 T2 399 T3 26 T7 49
valid_sources[0x7e] 301145 1 T2 387 T3 13 T7 57
valid_sources[0x7f] 281895 1 T2 402 T3 16 T7 45
valid_sources[0x80] 369930 1 T2 387 T3 19 T7 39



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 19595636 1 T1 2636 T2 41701 T3 1691
values[0x0] all_enables biggest_size 12949264 1 T1 805 T2 10035 T3 488
values[0x1] all_enables biggest_size 11711246 1 T1 740 T2 8990 T3 453

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%