Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

44543152

1

T1

766

T2

41242

T3

2687

full_word

44257190

1

T1

4181

T2

60726

T3

2632

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	88800032	1			T1	4947		T2	101968		T3	5319
auto[TlIntgErrCmd]	107	1			T84	2		T115	6		T119	4
auto[TlIntgErrData]	102	1			T84	4		T115	4		T119	6
auto[TlIntgErrBoth]	101	1			T84	4		T115	10		T137	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49313014

1

T1

3077

T2

67794

T3

3611

auto[1]

39487328

1

T1

1870

T2

34174

T3

1708

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	29716922	1			T1	441		T2	26093		T3	1920
auto[TlIntgErrNone]	partial	auto[1]	14825949	1			T1	325		T2	15149		T3	767
auto[TlIntgErrNone]	full_word	auto[0]	19595953	1			T1	2636		T2	41701		T3	1691
auto[TlIntgErrNone]	full_word	auto[1]	24661208	1			T1	1545		T2	19025		T3	941
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T84	1		T115	1		T119	2
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T84	1		T115	4		T119	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T153	1		T161	1		T173	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T115	1		T161	1		T174	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T84	3		T115	1		T119	2
auto[TlIntgErrData]	partial	auto[1]	48	1			T84	1		T115	1		T119	3
auto[TlIntgErrData]	full_word	auto[0]	9	1			T115	2		T119	1		T138	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T138	1		T153	1		T156	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T84	1		T115	3		T137	4
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T84	3		T115	7		T137	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T137	1		T175	1		T161	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T139	1		T174	1		-	-