Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	542858536	56064	0	0
RunThenComplete_M	542858536	675553	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	542858536	56064	0	0
T1	56261	30	0	0
T2	989599	105	0	0
T3	15094	4	0	0
T4	123138	16	0	0
T7	132324	13	0	0
T8	300487	93	0	0
T15	367174	283	0	0
T20	0	185	0	0
T22	193704	53	0	0
T33	1000	0	0	0
T34	257987	88	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	542858536	675553	0	0
T1	56261	78	0	0
T2	989599	540	0	0
T3	15094	20	0	0
T4	123138	48	0	0
T7	132324	53	0	0
T8	300487	471	0	0
T15	367174	2800	0	0
T20	0	996	0	0
T22	193704	304	0	0
T33	1000	0	0	0
T34	257987	486	0	0