Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	544250360	54264543	0	0
DepthKnown_A	544250360	544033410	0	0
RvalidKnown_A	544250360	544033410	0	0
WreadyKnown_A	544250360	544033410	0	0
gen_passthru_fifo.paramCheckPass	870	870	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544250360	54264543	0	0
T1	56261	2358	0	0
T2	989599	53609	0	0
T3	15094	3242	0	0
T4	123138	1979	0	0
T7	132324	5133	0	0
T8	300487	40795	0	0
T15	367174	305588	0	0
T22	193704	38101	0	0
T33	1000	19	0	0
T34	257987	60159	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544250360	544033410	0	0
T1	56261	56201	0	0
T2	989599	989506	0	0
T3	15094	15015	0	0
T4	123138	123075	0	0
T7	132324	132233	0	0
T8	300487	300395	0	0
T15	367174	367131	0	0
T22	193704	193652	0	0
T33	1000	947	0	0
T34	257987	257926	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544250360	544033410	0	0
T1	56261	56201	0	0
T2	989599	989506	0	0
T3	15094	15015	0	0
T4	123138	123075	0	0
T7	132324	132233	0	0
T8	300487	300395	0	0
T15	367174	367131	0	0
T22	193704	193652	0	0
T33	1000	947	0	0
T34	257987	257926	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544250360	544033410	0	0
T1	56261	56201	0	0
T2	989599	989506	0	0
T3	15094	15015	0	0
T4	123138	123075	0	0
T7	132324	132233	0	0
T8	300487	300395	0	0
T15	367174	367131	0	0
T22	193704	193652	0	0
T33	1000	947	0	0
T34	257987	257926	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	870	870	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T22	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	544250360	91488029	0	0
DepthKnown_A	544250360	544033410	0	0
RvalidKnown_A	544250360	544033410	0	0
WreadyKnown_A	544250360	544033410	0	0
gen_passthru_fifo.paramCheckPass	870	870	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544250360	91488029	0	0
T1	56261	2358	0	0
T2	989599	165912	0	0
T3	15094	3242	0	0
T4	123138	1979	0	0
T7	132324	16093	0	0
T8	300487	40795	0	0
T15	367174	305588	0	0
T22	193704	38101	0	0
T33	1000	19	0	0
T34	257987	60159	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544250360	544033410	0	0
T1	56261	56201	0	0
T2	989599	989506	0	0
T3	15094	15015	0	0
T4	123138	123075	0	0
T7	132324	132233	0	0
T8	300487	300395	0	0
T15	367174	367131	0	0
T22	193704	193652	0	0
T33	1000	947	0	0
T34	257987	257926	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544250360	544033410	0	0
T1	56261	56201	0	0
T2	989599	989506	0	0
T3	15094	15015	0	0
T4	123138	123075	0	0
T7	132324	132233	0	0
T8	300487	300395	0	0
T15	367174	367131	0	0
T22	193704	193652	0	0
T33	1000	947	0	0
T34	257987	257926	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544250360	544033410	0	0
T1	56261	56201	0	0
T2	989599	989506	0	0
T3	15094	15015	0	0
T4	123138	123075	0	0
T7	132324	132233	0	0
T8	300487	300395	0	0
T15	367174	367131	0	0
T22	193704	193652	0	0
T33	1000	947	0	0
T34	257987	257926	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	870	870	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T22	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0