Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	544250360	3201	0	0
entropy_period_rd_A	544250360	2064	0	0
intr_enable_rd_A	544250360	2850	0	0
prefix_0_rd_A	544250360	1981	0	0
prefix_10_rd_A	544250360	1933	0	0
prefix_1_rd_A	544250360	1778	0	0
prefix_2_rd_A	544250360	1953	0	0
prefix_3_rd_A	544250360	1907	0	0
prefix_4_rd_A	544250360	1889	0	0
prefix_5_rd_A	544250360	1787	0	0
prefix_6_rd_A	544250360	1867	0	0
prefix_7_rd_A	544250360	1819	0	0
prefix_8_rd_A	544250360	1809	0	0
prefix_9_rd_A	544250360	1931	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544250360	3201	0	0
T84	9688	1	0	0
T98	5444	49	0	0
T99	7369	2	0	0
T115	22270	4	0	0
T116	10765	195	0	0
T120	8872	227	0	0
T121	2675	118	0	0
T122	4709	283	0	0
T137	18488	1	0	0
T138	22146	3	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544250360	2064	0	0
T85	13435	47	0	0
T99	7369	25	0	0
T115	22270	123	0	0
T138	22146	46	0	0
T152	1990	9	0	0
T153	23930	100	0	0
T154	1681	4	0	0
T155	2114	2	0	0
T156	22507	69	0	0
T157	6201	14	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544250360	2850	0	0
T99	7369	17	0	0
T115	22270	167	0	0
T126	864	8	0	0
T127	1268	23	0	0
T138	22146	109	0	0
T152	1990	2	0	0
T153	23930	164	0	0
T158	1316	15	0	0
T159	1271	15	0	0
T160	1685	34	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544250360	1981	0	0
T85	13435	40	0	0
T99	7369	14	0	0
T115	22270	88	0	0
T130	5411	10	0	0
T138	22146	31	0	0
T153	23930	69	0	0
T155	2114	6	0	0
T156	22507	46	0	0
T157	6201	39	0	0
T161	12219	30	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544250360	1933	0	0
T85	13435	41	0	0
T99	7369	10	0	0
T115	22270	100	0	0
T138	22146	32	0	0
T152	1990	1	0	0
T153	23930	69	0	0
T154	1681	2	0	0
T155	2114	6	0	0
T156	22507	37	0	0
T157	6201	27	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544250360	1778	0	0
T85	13435	32	0	0
T99	7369	24	0	0
T115	22270	94	0	0
T130	5411	5	0	0
T138	22146	33	0	0
T152	1990	4	0	0
T153	23930	75	0	0
T155	2114	8	0	0
T156	22507	42	0	0
T162	1719	2	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544250360	1953	0	0
T85	13435	28	0	0
T99	7369	12	0	0
T115	22270	90	0	0
T130	5411	12	0	0
T138	22146	30	0	0
T152	1990	1	0	0
T153	23930	86	0	0
T155	2114	7	0	0
T156	22507	39	0	0
T157	6201	38	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544250360	1907	0	0
T85	13435	12	0	0
T99	7369	12	0	0
T115	22270	91	0	0
T138	22146	17	0	0
T153	23930	79	0	0
T154	1681	4	0	0
T155	2114	1	0	0
T156	22507	35	0	0
T157	6201	10	0	0
T162	1719	1	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544250360	1889	0	0
T85	13435	33	0	0
T99	7369	8	0	0
T115	22270	68	0	0
T130	5411	4	0	0
T138	22146	49	0	0
T152	1990	9	0	0
T153	23930	94	0	0
T155	2114	3	0	0
T156	22507	35	0	0
T157	6201	16	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544250360	1787	0	0
T85	13435	33	0	0
T99	7369	7	0	0
T115	22270	75	0	0
T138	22146	23	0	0
T152	1990	7	0	0
T153	23930	57	0	0
T154	1681	6	0	0
T155	2114	5	0	0
T156	22507	40	0	0
T162	1719	3	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544250360	1867	0	0
T85	13435	36	0	0
T98	5444	9	0	0
T99	7369	16	0	0
T115	22270	77	0	0
T138	22146	44	0	0
T152	1990	8	0	0
T153	23930	74	0	0
T154	1681	3	0	0
T155	2114	7	0	0
T162	1719	10	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544250360	1819	0	0
T85	13435	19	0	0
T99	7369	4	0	0
T115	22270	99	0	0
T130	5411	9	0	0
T138	22146	45	0	0
T152	1990	5	0	0
T153	23930	76	0	0
T155	2114	2	0	0
T156	22507	21	0	0
T157	6201	1	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544250360	1809	0	0
T85	13435	20	0	0
T99	7369	19	0	0
T115	22270	82	0	0
T138	22146	17	0	0
T152	1990	3	0	0
T153	23930	52	0	0
T155	2114	3	0	0
T156	22507	46	0	0
T157	6201	24	0	0
T162	1719	3	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544250360	1931	0	0
T85	13435	28	0	0
T99	7369	18	0	0
T115	22270	75	0	0
T130	5411	4	0	0
T138	22146	47	0	0
T152	1990	2	0	0
T153	23930	63	0	0
T155	2114	3	0	0
T156	22507	36	0	0
T157	6201	42	0	0