Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14431087	1			T1	3880		T2	174942		T36	1515
all_values[1]	14431087	1			T1	3880		T2	174942		T36	1515
all_values[2]	14431087	1			T1	3880		T2	174942		T36	1515

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

408412

1

T1

274

T36

18

T7

2

auto[1]

42884849

1

T1

11366

T2

524826

T36

4527

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43095378

1

T1

11541

T2

524421

T36

3915

auto[1]

197883

1

T1

99

T2

405

T36

630

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	160310	1			T7	2		T38	13430		T39	5
all_values[0]	auto[0]	auto[1]	1272	1			T38	14		T39	2		T45	6
all_values[0]	auto[1]	auto[0]	14204816	1			T1	3847		T2	174807		T36	1305
all_values[0]	auto[1]	auto[1]	64689	1			T1	33		T2	135		T36	210
all_values[1]	auto[0]	auto[0]	121050	1			T1	272		T36	16		T39	5
all_values[1]	auto[0]	auto[1]	879	1			T1	2		T36	2		T39	2
all_values[1]	auto[1]	auto[0]	14244076	1			T1	3575		T2	174807		T36	1289
all_values[1]	auto[1]	auto[1]	65082	1			T1	31		T2	135		T36	208
all_values[2]	auto[0]	auto[0]	124021	1			T38	2366		T20	158		T22	602
all_values[2]	auto[0]	auto[1]	880	1			T38	2		T20	1		T22	2
all_values[2]	auto[1]	auto[0]	14241105	1			T1	3847		T2	174807		T36	1305
all_values[2]	auto[1]	auto[1]	65081	1			T1	33		T2	135		T36	210