Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	14431087	1			T1	3880		T2	174942		T36	1515
all_pins[1]	14431087	1			T1	3880		T2	174942		T36	1515
all_pins[2]	14431087	1			T1	3880		T2	174942		T36	1515

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	42960155	1			T1	7750		T2	524691		T36	4335
values[0x1]	333106	1			T1	3890		T2	135		T36	210
transitions[0x0=>0x1]	331403	1			T1	3863		T2	135		T36	210
transitions[0x1=>0x0]	331424	1			T1	3864		T2	135		T36	210

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	14366398	1			T1	3847		T2	174807		T36	1305
all_pins[0]	values[0x1]	64689	1			T1	33		T2	135		T36	210
all_pins[0]	transitions[0x0=>0x1]	64678	1			T1	33		T2	135		T36	210
all_pins[0]	transitions[0x1=>0x0]	5545	1			T1	2		T62	88		T63	66
all_pins[1]	values[0x0]	14425531	1			T1	3878		T2	174942		T36	1515
all_pins[1]	values[0x1]	5556	1			T1	2		T62	88		T63	66
all_pins[1]	transitions[0x0=>0x1]	5412	1			T62	88		T63	66		T81	33
all_pins[1]	transitions[0x1=>0x0]	262717	1			T1	3853		T20	364		T22	281
all_pins[2]	values[0x0]	14168226	1			T1	25		T2	174942		T36	1515
all_pins[2]	values[0x1]	262861	1			T1	3855		T20	364		T22	281
all_pins[2]	transitions[0x0=>0x1]	261313	1			T1	3830		T20	364		T22	281
all_pins[2]	transitions[0x1=>0x0]	63162	1			T1	9		T2	135		T36	210