Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	600	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5025	1			T2	9		T38	2		T8	4
len_601_800	11309	1			T1	12		T2	38		T38	8
len_401_600	7477	1			T1	6		T2	19		T38	2
len_201_400	3907	1			T1	5		T2	12		T38	4
len_65_200	6378	1			T2	11		T36	72		T38	2
len_min_for_xof_require_squeeze	63	1			T36	1		T18	1		T144	1
len_keccak_block_sizes[72]	79	1			T36	1		T45	1		T63	1
len_keccak_block_sizes[104]	56	1			T39	3		T43	1		T201	1
len_keccak_block_sizes[136]	61	1			T36	1		T62	1		T45	1
len_keccak_block_sizes[144]	35	1			T39	1		T45	1		T17	1
len_keccak_block_sizes[168]	30	1			T45	1		T17	1		T202	1
len_datapath_width	978	1			T2	1		T36	5		T39	3
len_2_63	13251	1			T1	11		T2	3		T36	65
len_1	47	1			T36	1		T39	1		T45	1