Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5809273 |
1 |
|
|
T1 |
4366 |
|
T2 |
14642 |
|
T36 |
4963 |
auto[1] |
5809219 |
1 |
|
|
T1 |
4366 |
|
T2 |
14642 |
|
T36 |
4963 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
11560002 |
1 |
|
|
T1 |
8696 |
|
T2 |
29152 |
|
T36 |
9726 |
triple_byte_access |
19466 |
1 |
|
|
T1 |
12 |
|
T2 |
50 |
|
T36 |
72 |
halfword_access |
19760 |
1 |
|
|
T1 |
12 |
|
T2 |
46 |
|
T36 |
52 |
byte_access |
19264 |
1 |
|
|
T1 |
12 |
|
T2 |
36 |
|
T36 |
76 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
5780028 |
1 |
|
|
T1 |
4348 |
|
T2 |
14576 |
|
T36 |
4863 |
auto[0] |
triple_byte_access |
9733 |
1 |
|
|
T1 |
6 |
|
T2 |
25 |
|
T36 |
36 |
auto[0] |
halfword_access |
9880 |
1 |
|
|
T1 |
6 |
|
T2 |
23 |
|
T36 |
26 |
auto[0] |
byte_access |
9632 |
1 |
|
|
T1 |
6 |
|
T2 |
18 |
|
T36 |
38 |
auto[1] |
word_access |
5779974 |
1 |
|
|
T1 |
4348 |
|
T2 |
14576 |
|
T36 |
4863 |
auto[1] |
triple_byte_access |
9733 |
1 |
|
|
T1 |
6 |
|
T2 |
25 |
|
T36 |
36 |
auto[1] |
halfword_access |
9880 |
1 |
|
|
T1 |
6 |
|
T2 |
23 |
|
T36 |
26 |
auto[1] |
byte_access |
9632 |
1 |
|
|
T1 |
6 |
|
T2 |
18 |
|
T36 |
38 |