Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.18 97.89 92.58 99.89 76.76 95.53 98.89 97.73


Total test records in report: 866
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html
T764 /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.614100277 Aug 16 06:05:33 PM PDT 24 Aug 16 06:05:36 PM PDT 24 87399665 ps
T765 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.623517030 Aug 16 06:05:08 PM PDT 24 Aug 16 06:05:09 PM PDT 24 29173056 ps
T766 /workspace/coverage/cover_reg_top/22.kmac_intr_test.2407460252 Aug 16 06:05:34 PM PDT 24 Aug 16 06:05:35 PM PDT 24 115490648 ps
T189 /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.2233159174 Aug 16 06:05:18 PM PDT 24 Aug 16 06:05:21 PM PDT 24 195232849 ps
T767 /workspace/coverage/cover_reg_top/11.kmac_csr_rw.672901796 Aug 16 06:05:07 PM PDT 24 Aug 16 06:05:09 PM PDT 24 31022656 ps
T768 /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.2587573647 Aug 16 06:04:43 PM PDT 24 Aug 16 06:05:03 PM PDT 24 5749435186 ps
T769 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.3244674585 Aug 16 06:05:14 PM PDT 24 Aug 16 06:05:16 PM PDT 24 90922994 ps
T770 /workspace/coverage/cover_reg_top/38.kmac_intr_test.3411858835 Aug 16 06:05:34 PM PDT 24 Aug 16 06:05:34 PM PDT 24 23695722 ps
T771 /workspace/coverage/cover_reg_top/49.kmac_intr_test.3045300246 Aug 16 06:05:43 PM PDT 24 Aug 16 06:05:44 PM PDT 24 28083928 ps
T772 /workspace/coverage/cover_reg_top/1.kmac_intr_test.3002945682 Aug 16 06:04:35 PM PDT 24 Aug 16 06:04:36 PM PDT 24 15117850 ps
T140 /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.2171001818 Aug 16 06:04:26 PM PDT 24 Aug 16 06:04:28 PM PDT 24 113017067 ps
T178 /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.3722516307 Aug 16 06:04:45 PM PDT 24 Aug 16 06:04:49 PM PDT 24 353616410 ps
T773 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.141731135 Aug 16 06:05:01 PM PDT 24 Aug 16 06:05:02 PM PDT 24 92332026 ps
T774 /workspace/coverage/cover_reg_top/10.kmac_tl_errors.3936652864 Aug 16 06:05:12 PM PDT 24 Aug 16 06:05:14 PM PDT 24 56782634 ps
T775 /workspace/coverage/cover_reg_top/9.kmac_intr_test.293706026 Aug 16 06:05:12 PM PDT 24 Aug 16 06:05:13 PM PDT 24 15535821 ps
T776 /workspace/coverage/cover_reg_top/13.kmac_intr_test.4253589025 Aug 16 06:05:16 PM PDT 24 Aug 16 06:05:17 PM PDT 24 16748206 ps
T777 /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.1928891766 Aug 16 06:05:07 PM PDT 24 Aug 16 06:05:09 PM PDT 24 272352564 ps
T778 /workspace/coverage/cover_reg_top/11.kmac_intr_test.3017133496 Aug 16 06:05:09 PM PDT 24 Aug 16 06:05:10 PM PDT 24 21726790 ps
T779 /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.4276159989 Aug 16 06:05:10 PM PDT 24 Aug 16 06:05:13 PM PDT 24 193645425 ps
T190 /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.104424777 Aug 16 06:04:49 PM PDT 24 Aug 16 06:04:53 PM PDT 24 208495829 ps
T780 /workspace/coverage/cover_reg_top/8.kmac_tl_errors.3831049086 Aug 16 06:04:58 PM PDT 24 Aug 16 06:05:01 PM PDT 24 1785644771 ps
T781 /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.533660084 Aug 16 06:05:25 PM PDT 24 Aug 16 06:05:27 PM PDT 24 36908640 ps
T782 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2501583023 Aug 16 06:05:05 PM PDT 24 Aug 16 06:05:07 PM PDT 24 104894487 ps
T783 /workspace/coverage/cover_reg_top/0.kmac_csr_rw.3635092106 Aug 16 06:04:27 PM PDT 24 Aug 16 06:04:29 PM PDT 24 18247838 ps
T784 /workspace/coverage/cover_reg_top/12.kmac_intr_test.3749462819 Aug 16 06:05:15 PM PDT 24 Aug 16 06:05:16 PM PDT 24 98970109 ps
T785 /workspace/coverage/cover_reg_top/2.kmac_intr_test.754220290 Aug 16 06:04:40 PM PDT 24 Aug 16 06:04:41 PM PDT 24 29465010 ps
T786 /workspace/coverage/cover_reg_top/31.kmac_intr_test.2387455945 Aug 16 06:05:34 PM PDT 24 Aug 16 06:05:35 PM PDT 24 48739974 ps
T787 /workspace/coverage/cover_reg_top/1.kmac_tl_errors.1635509550 Aug 16 06:04:37 PM PDT 24 Aug 16 06:04:39 PM PDT 24 247820257 ps
T788 /workspace/coverage/cover_reg_top/3.kmac_csr_rw.2407796416 Aug 16 06:04:44 PM PDT 24 Aug 16 06:04:45 PM PDT 24 70103311 ps
T789 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.3068156339 Aug 16 06:05:09 PM PDT 24 Aug 16 06:05:11 PM PDT 24 188357870 ps
T790 /workspace/coverage/cover_reg_top/9.kmac_tl_errors.3181508792 Aug 16 06:05:07 PM PDT 24 Aug 16 06:05:09 PM PDT 24 121879801 ps
T791 /workspace/coverage/cover_reg_top/6.kmac_tl_errors.1545703603 Aug 16 06:04:58 PM PDT 24 Aug 16 06:05:01 PM PDT 24 216310306 ps
T792 /workspace/coverage/cover_reg_top/16.kmac_intr_test.3820568516 Aug 16 06:05:24 PM PDT 24 Aug 16 06:05:25 PM PDT 24 14067180 ps
T793 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.1149014048 Aug 16 06:05:08 PM PDT 24 Aug 16 06:05:11 PM PDT 24 117584929 ps
T794 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.831831019 Aug 16 06:05:12 PM PDT 24 Aug 16 06:05:15 PM PDT 24 401425396 ps
T181 /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.1782836377 Aug 16 06:05:18 PM PDT 24 Aug 16 06:05:22 PM PDT 24 562451875 ps
T795 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3246558442 Aug 16 06:05:16 PM PDT 24 Aug 16 06:05:17 PM PDT 24 46399438 ps
T796 /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1791337348 Aug 16 06:05:07 PM PDT 24 Aug 16 06:05:09 PM PDT 24 125757153 ps
T797 /workspace/coverage/cover_reg_top/18.kmac_intr_test.866012281 Aug 16 06:05:29 PM PDT 24 Aug 16 06:05:30 PM PDT 24 18082888 ps
T798 /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.3237337445 Aug 16 06:05:07 PM PDT 24 Aug 16 06:05:08 PM PDT 24 74959104 ps
T799 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.1238743955 Aug 16 06:05:07 PM PDT 24 Aug 16 06:05:08 PM PDT 24 59613024 ps
T800 /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.2098628388 Aug 16 06:05:08 PM PDT 24 Aug 16 06:05:12 PM PDT 24 199629560 ps
T801 /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2453520754 Aug 16 06:05:01 PM PDT 24 Aug 16 06:05:03 PM PDT 24 25416697 ps
T802 /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2781303836 Aug 16 06:05:23 PM PDT 24 Aug 16 06:05:25 PM PDT 24 70044255 ps
T803 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.151866557 Aug 16 06:05:25 PM PDT 24 Aug 16 06:05:26 PM PDT 24 34867245 ps
T182 /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.3278924987 Aug 16 06:05:11 PM PDT 24 Aug 16 06:05:14 PM PDT 24 102283384 ps
T804 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2745116260 Aug 16 06:05:25 PM PDT 24 Aug 16 06:05:26 PM PDT 24 32377856 ps
T805 /workspace/coverage/cover_reg_top/19.kmac_intr_test.4289743945 Aug 16 06:05:33 PM PDT 24 Aug 16 06:05:33 PM PDT 24 26192076 ps
T806 /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2072888463 Aug 16 06:05:06 PM PDT 24 Aug 16 06:05:08 PM PDT 24 133450518 ps
T185 /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.1387054441 Aug 16 06:05:25 PM PDT 24 Aug 16 06:05:30 PM PDT 24 103148701 ps
T807 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3036176474 Aug 16 06:05:24 PM PDT 24 Aug 16 06:05:26 PM PDT 24 169657272 ps
T808 /workspace/coverage/cover_reg_top/44.kmac_intr_test.4011130221 Aug 16 06:05:39 PM PDT 24 Aug 16 06:05:40 PM PDT 24 24608698 ps
T809 /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.2804320678 Aug 16 06:04:50 PM PDT 24 Aug 16 06:04:52 PM PDT 24 46130018 ps
T810 /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.2639132280 Aug 16 06:04:43 PM PDT 24 Aug 16 06:04:44 PM PDT 24 26425586 ps
T811 /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.3385630548 Aug 16 06:04:57 PM PDT 24 Aug 16 06:05:01 PM PDT 24 567680819 ps
T812 /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.3945782326 Aug 16 06:04:45 PM PDT 24 Aug 16 06:04:49 PM PDT 24 379608051 ps
T813 /workspace/coverage/cover_reg_top/7.kmac_csr_rw.1180921846 Aug 16 06:05:03 PM PDT 24 Aug 16 06:05:04 PM PDT 24 61993678 ps
T814 /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.1097617225 Aug 16 06:05:06 PM PDT 24 Aug 16 06:05:08 PM PDT 24 81327804 ps
T815 /workspace/coverage/cover_reg_top/14.kmac_intr_test.2924925295 Aug 16 06:05:19 PM PDT 24 Aug 16 06:05:20 PM PDT 24 25642235 ps
T816 /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.969504199 Aug 16 06:05:25 PM PDT 24 Aug 16 06:05:28 PM PDT 24 1019403429 ps
T817 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.4148576673 Aug 16 06:04:25 PM PDT 24 Aug 16 06:04:26 PM PDT 24 109546111 ps
T818 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.1387195838 Aug 16 06:04:42 PM PDT 24 Aug 16 06:04:45 PM PDT 24 733768622 ps
T819 /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.1852889900 Aug 16 06:05:29 PM PDT 24 Aug 16 06:05:31 PM PDT 24 218200726 ps
T820 /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.143153329 Aug 16 06:04:33 PM PDT 24 Aug 16 06:04:36 PM PDT 24 152494901 ps
T821 /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.4055412664 Aug 16 06:04:41 PM PDT 24 Aug 16 06:04:46 PM PDT 24 206128456 ps
T822 /workspace/coverage/cover_reg_top/24.kmac_intr_test.80027839 Aug 16 06:05:36 PM PDT 24 Aug 16 06:05:36 PM PDT 24 36423752 ps
T823 /workspace/coverage/cover_reg_top/17.kmac_tl_errors.142703303 Aug 16 06:05:26 PM PDT 24 Aug 16 06:05:29 PM PDT 24 350265438 ps
T824 /workspace/coverage/cover_reg_top/25.kmac_intr_test.1057789138 Aug 16 06:05:33 PM PDT 24 Aug 16 06:05:34 PM PDT 24 90429104 ps
T825 /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.1862747552 Aug 16 06:04:49 PM PDT 24 Aug 16 06:04:50 PM PDT 24 23127475 ps
T826 /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1345974839 Aug 16 06:05:25 PM PDT 24 Aug 16 06:05:26 PM PDT 24 92682445 ps
T827 /workspace/coverage/cover_reg_top/21.kmac_intr_test.403929791 Aug 16 06:05:33 PM PDT 24 Aug 16 06:05:34 PM PDT 24 65085845 ps
T828 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.3978747543 Aug 16 06:04:25 PM PDT 24 Aug 16 06:04:27 PM PDT 24 39620781 ps
T829 /workspace/coverage/cover_reg_top/13.kmac_tl_errors.2799317667 Aug 16 06:05:16 PM PDT 24 Aug 16 06:05:18 PM PDT 24 59738871 ps
T830 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1965599962 Aug 16 06:05:24 PM PDT 24 Aug 16 06:05:27 PM PDT 24 103785727 ps
T831 /workspace/coverage/cover_reg_top/0.kmac_tl_errors.604418073 Aug 16 06:04:24 PM PDT 24 Aug 16 06:04:28 PM PDT 24 271116433 ps
T832 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.2669804323 Aug 16 06:04:59 PM PDT 24 Aug 16 06:05:02 PM PDT 24 1403183914 ps
T833 /workspace/coverage/cover_reg_top/48.kmac_intr_test.2238853566 Aug 16 06:05:44 PM PDT 24 Aug 16 06:05:45 PM PDT 24 42088026 ps
T834 /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.628047703 Aug 16 06:04:23 PM PDT 24 Aug 16 06:04:36 PM PDT 24 3009370696 ps
T835 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.1373940446 Aug 16 06:05:24 PM PDT 24 Aug 16 06:05:26 PM PDT 24 104512824 ps
T180 /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.4045294881 Aug 16 06:05:27 PM PDT 24 Aug 16 06:05:32 PM PDT 24 997499024 ps
T836 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.2863155224 Aug 16 06:04:49 PM PDT 24 Aug 16 06:04:51 PM PDT 24 95996397 ps
T141 /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.1667384924 Aug 16 06:04:34 PM PDT 24 Aug 16 06:04:35 PM PDT 24 502790137 ps
T837 /workspace/coverage/cover_reg_top/0.kmac_mem_walk.2821979347 Aug 16 06:04:30 PM PDT 24 Aug 16 06:04:31 PM PDT 24 34452136 ps
T838 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.1603310177 Aug 16 06:05:32 PM PDT 24 Aug 16 06:05:33 PM PDT 24 300889636 ps
T839 /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.2232039230 Aug 16 06:04:36 PM PDT 24 Aug 16 06:04:43 PM PDT 24 136379318 ps
T840 /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.708268335 Aug 16 06:04:42 PM PDT 24 Aug 16 06:04:46 PM PDT 24 83737863 ps
T841 /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.1828648029 Aug 16 06:04:49 PM PDT 24 Aug 16 06:04:51 PM PDT 24 520510828 ps
T842 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.70220904 Aug 16 06:05:26 PM PDT 24 Aug 16 06:05:28 PM PDT 24 223471557 ps
T843 /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.1650659657 Aug 16 06:05:23 PM PDT 24 Aug 16 06:05:25 PM PDT 24 29692040 ps
T179 /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.782723965 Aug 16 06:05:23 PM PDT 24 Aug 16 06:05:26 PM PDT 24 151117147 ps
T844 /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.592119264 Aug 16 06:04:33 PM PDT 24 Aug 16 06:04:53 PM PDT 24 1517507134 ps
T845 /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.1395557449 Aug 16 06:04:44 PM PDT 24 Aug 16 06:04:46 PM PDT 24 200028388 ps
T846 /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.2676851452 Aug 16 06:05:15 PM PDT 24 Aug 16 06:05:18 PM PDT 24 122823231 ps
T183 /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.1997083515 Aug 16 06:04:27 PM PDT 24 Aug 16 06:04:30 PM PDT 24 268202020 ps
T142 /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.503347955 Aug 16 06:04:47 PM PDT 24 Aug 16 06:04:49 PM PDT 24 505223496 ps
T184 /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.1144927284 Aug 16 06:05:33 PM PDT 24 Aug 16 06:05:39 PM PDT 24 535118936 ps
T847 /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.3251231255 Aug 16 06:04:44 PM PDT 24 Aug 16 06:04:47 PM PDT 24 82076564 ps
T848 /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.2688753868 Aug 16 06:04:27 PM PDT 24 Aug 16 06:04:29 PM PDT 24 25745089 ps
T849 /workspace/coverage/cover_reg_top/12.kmac_csr_rw.4256674862 Aug 16 06:05:15 PM PDT 24 Aug 16 06:05:16 PM PDT 24 47654940 ps
T850 /workspace/coverage/cover_reg_top/5.kmac_tl_errors.1729872911 Aug 16 06:04:51 PM PDT 24 Aug 16 06:04:54 PM PDT 24 318228072 ps
T851 /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.3327960944 Aug 16 06:04:26 PM PDT 24 Aug 16 06:04:32 PM PDT 24 4127793224 ps
T852 /workspace/coverage/cover_reg_top/35.kmac_intr_test.1654553100 Aug 16 06:05:35 PM PDT 24 Aug 16 06:05:36 PM PDT 24 21892067 ps
T853 /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.3325418999 Aug 16 06:04:52 PM PDT 24 Aug 16 06:05:00 PM PDT 24 286884245 ps
T854 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.1004590090 Aug 16 06:04:59 PM PDT 24 Aug 16 06:05:01 PM PDT 24 65060449 ps
T855 /workspace/coverage/cover_reg_top/4.kmac_intr_test.3664371882 Aug 16 06:04:50 PM PDT 24 Aug 16 06:04:51 PM PDT 24 13686904 ps
T856 /workspace/coverage/cover_reg_top/3.kmac_mem_walk.2668702229 Aug 16 06:04:41 PM PDT 24 Aug 16 06:04:42 PM PDT 24 11688688 ps
T857 /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.2533607404 Aug 16 06:04:27 PM PDT 24 Aug 16 06:04:29 PM PDT 24 75942596 ps
T858 /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.289470383 Aug 16 06:05:32 PM PDT 24 Aug 16 06:05:34 PM PDT 24 83692048 ps
T859 /workspace/coverage/cover_reg_top/45.kmac_intr_test.3393955228 Aug 16 06:05:40 PM PDT 24 Aug 16 06:05:41 PM PDT 24 191058684 ps
T860 /workspace/coverage/cover_reg_top/3.kmac_tl_errors.1307088685 Aug 16 06:04:40 PM PDT 24 Aug 16 06:04:42 PM PDT 24 35714078 ps
T861 /workspace/coverage/cover_reg_top/42.kmac_intr_test.1154517275 Aug 16 06:05:38 PM PDT 24 Aug 16 06:05:39 PM PDT 24 37872416 ps
T862 /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.963116306 Aug 16 06:04:44 PM PDT 24 Aug 16 06:04:47 PM PDT 24 409996470 ps
T863 /workspace/coverage/cover_reg_top/5.kmac_intr_test.1783292609 Aug 16 06:04:58 PM PDT 24 Aug 16 06:04:59 PM PDT 24 45006105 ps
T864 /workspace/coverage/cover_reg_top/7.kmac_tl_errors.3370184393 Aug 16 06:04:59 PM PDT 24 Aug 16 06:05:02 PM PDT 24 142486327 ps
T865 /workspace/coverage/cover_reg_top/6.kmac_intr_test.1361912670 Aug 16 06:05:01 PM PDT 24 Aug 16 06:05:02 PM PDT 24 15705567 ps
T866 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.1248209988 Aug 16 06:05:16 PM PDT 24 Aug 16 06:05:18 PM PDT 24 102939042 ps

Test location /workspace/coverage/default/5.kmac_mubi.3363595662
Short name T1
Test name
Test status
Simulation time 3635184752 ps
CPU time 67.42 seconds
Started Aug 16 06:06:17 PM PDT 24
Finished Aug 16 06:07:25 PM PDT 24
Peak memory 247364 kb
Host smart-51af92a6-83d6-4734-a4f7-1aa7c291d046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363595662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.3363595662 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_mubi/latest

Test location /workspace/coverage/default/48.kmac_entropy_refresh.2720777740
Short name T18
Test name
Test status
Simulation time 26431174595 ps
CPU time 407.8 seconds
Started Aug 16 06:10:20 PM PDT 24
Finished Aug 16 06:17:08 PM PDT 24
Peak memory 506696 kb
Host smart-fa25d587-0996-437a-8738-0c28b1e32c10
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720777740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.2
720777740 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_entropy_refresh/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.3054699813
Short name T116
Test name
Test status
Simulation time 465998838 ps
CPU time 5.08 seconds
Started Aug 16 06:05:12 PM PDT 24
Finished Aug 16 06:05:18 PM PDT 24
Peak memory 216060 kb
Host smart-3d6d912e-72a7-48d5-8d11-9915d3ae78c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054699813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.3054
699813 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/35.kmac_lc_escalation.133220289
Short name T12
Test name
Test status
Simulation time 60635223 ps
CPU time 1.67 seconds
Started Aug 16 06:08:53 PM PDT 24
Finished Aug 16 06:08:54 PM PDT 24
Peak memory 226652 kb
Host smart-d4d0abff-311e-42fe-92b6-68d00521a012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133220289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.133220289 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/35.kmac_lc_escalation/latest

Test location /workspace/coverage/default/3.kmac_stress_all_with_rand_reset.3548001308
Short name T26
Test name
Test status
Simulation time 12493432706 ps
CPU time 89.27 seconds
Started Aug 16 06:06:07 PM PDT 24
Finished Aug 16 06:07:36 PM PDT 24
Peak memory 259188 kb
Host smart-c8df7bb5-870d-49bd-9086-3d45f5906573
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3548001308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all_with_rand_reset.3548001308 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.kmac_sec_cm.676229976
Short name T32
Test name
Test status
Simulation time 9704805600 ps
CPU time 44.4 seconds
Started Aug 16 06:06:08 PM PDT 24
Finished Aug 16 06:06:53 PM PDT 24
Peak memory 256708 kb
Host smart-02ee2bac-77c5-46b6-9258-fb7bdc2b3a65
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676229976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.676229976 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/3.kmac_sec_cm/latest

Test location /workspace/coverage/default/37.kmac_error.1291061447
Short name T22
Test name
Test status
Simulation time 9716344565 ps
CPU time 337.24 seconds
Started Aug 16 06:09:15 PM PDT 24
Finished Aug 16 06:14:53 PM PDT 24
Peak memory 487516 kb
Host smart-71445ee5-49aa-4077-841c-59618b64413a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291061447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.1291061447 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_error/latest

Test location /workspace/coverage/default/34.kmac_key_error.1083718566
Short name T5
Test name
Test status
Simulation time 173567075 ps
CPU time 1.82 seconds
Started Aug 16 06:08:56 PM PDT 24
Finished Aug 16 06:08:58 PM PDT 24
Peak memory 226216 kb
Host smart-19cd5aa6-e42d-4401-ba1d-8b7d67d0594e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083718566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.1083718566 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_key_error/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1927193549
Short name T91
Test name
Test status
Simulation time 998561374 ps
CPU time 2.74 seconds
Started Aug 16 06:04:52 PM PDT 24
Finished Aug 16 06:04:55 PM PDT 24
Peak memory 219000 kb
Host smart-cba2288e-d155-475a-a727-1ad6122ac397
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927193549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac
_shadow_reg_errors_with_csr_rw.1927193549 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/2.kmac_lc_escalation.822699647
Short name T29
Test name
Test status
Simulation time 101090726 ps
CPU time 2.2 seconds
Started Aug 16 06:06:01 PM PDT 24
Finished Aug 16 06:06:04 PM PDT 24
Peak memory 226756 kb
Host smart-a7041ea1-0d84-48b3-be31-0495986b772a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822699647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.822699647 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_lc_escalation/latest

Test location /workspace/coverage/default/13.kmac_lc_escalation.346493670
Short name T48
Test name
Test status
Simulation time 50044206 ps
CPU time 1.41 seconds
Started Aug 16 06:07:10 PM PDT 24
Finished Aug 16 06:07:11 PM PDT 24
Peak memory 226684 kb
Host smart-18fc153a-3d4c-4055-9f84-6d33381e4c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346493670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.346493670 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/13.kmac_lc_escalation/latest

Test location /workspace/coverage/default/0.kmac_entropy_ready_error.3682480374
Short name T490
Test name
Test status
Simulation time 4766255299 ps
CPU time 52.6 seconds
Started Aug 16 06:05:42 PM PDT 24
Finished Aug 16 06:06:34 PM PDT 24
Peak memory 224344 kb
Host smart-29e7bd22-f9d8-499b-aabe-652ad5b9ecaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682480374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.3682480374 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_ready_error/latest

Test location /workspace/coverage/cover_reg_top/46.kmac_intr_test.922618721
Short name T164
Test name
Test status
Simulation time 13102568 ps
CPU time 0.78 seconds
Started Aug 16 06:05:44 PM PDT 24
Finished Aug 16 06:05:45 PM PDT 24
Peak memory 215696 kb
Host smart-793af583-46c4-4306-8919-e903cd527529
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922618721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.922618721 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/46.kmac_intr_test/latest

Test location /workspace/coverage/default/15.kmac_edn_timeout_error.3876328134
Short name T70
Test name
Test status
Simulation time 47819127 ps
CPU time 0.87 seconds
Started Aug 16 06:07:19 PM PDT 24
Finished Aug 16 06:07:20 PM PDT 24
Peak memory 218152 kb
Host smart-df4224a6-3dda-493d-9628-f5524b7c192e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3876328134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.3876328134 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/0.kmac_lc_escalation.2424255843
Short name T52
Test name
Test status
Simulation time 563679705 ps
CPU time 29.66 seconds
Started Aug 16 06:05:44 PM PDT 24
Finished Aug 16 06:06:13 PM PDT 24
Peak memory 252544 kb
Host smart-da9ae3af-0aea-493b-a5d6-d0a1d3182678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424255843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.2424255843 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/0.kmac_lc_escalation/latest

Test location /workspace/coverage/default/0.kmac_entropy_mode_error.3835723626
Short name T314
Test name
Test status
Simulation time 113139449 ps
CPU time 1.16 seconds
Started Aug 16 06:05:43 PM PDT 24
Finished Aug 16 06:05:44 PM PDT 24
Peak memory 222044 kb
Host smart-9451a1dc-3df6-4661-9691-90eac6cfb47f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3835723626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.3835723626 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/39.kmac_smoke.1893797069
Short name T45
Test name
Test status
Simulation time 12047183739 ps
CPU time 54.33 seconds
Started Aug 16 06:09:23 PM PDT 24
Finished Aug 16 06:10:17 PM PDT 24
Peak memory 223724 kb
Host smart-a3a6c63b-07a9-4dad-ac27-fc6ca137e41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893797069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.1893797069 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_smoke/latest

Test location /workspace/coverage/default/25.kmac_lc_escalation.1367074297
Short name T67
Test name
Test status
Simulation time 34987434 ps
CPU time 1.2 seconds
Started Aug 16 06:08:09 PM PDT 24
Finished Aug 16 06:08:10 PM PDT 24
Peak memory 226616 kb
Host smart-389ee0bc-08e7-4e42-9b78-f5043e2d5846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367074297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.1367074297 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/25.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.4160097279
Short name T88
Test name
Test status
Simulation time 28709372 ps
CPU time 1.11 seconds
Started Aug 16 06:04:50 PM PDT 24
Finished Aug 16 06:04:51 PM PDT 24
Peak memory 216404 kb
Host smart-c8c81c38-d6c3-48c0-96b3-3426b82f18c2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160097279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_
errors.4160097279 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.2171001818
Short name T140
Test name
Test status
Simulation time 113017067 ps
CPU time 1.23 seconds
Started Aug 16 06:04:26 PM PDT 24
Finished Aug 16 06:04:28 PM PDT 24
Peak memory 216056 kb
Host smart-3681b28d-12c2-46f4-9d51-1329e615bb2f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171001818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia
l_access.2171001818 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mem_partial_access/latest

Test location /workspace/coverage/default/32.kmac_lc_escalation.2064299948
Short name T11
Test name
Test status
Simulation time 254928483 ps
CPU time 1.36 seconds
Started Aug 16 06:08:37 PM PDT 24
Finished Aug 16 06:08:38 PM PDT 24
Peak memory 226644 kb
Host smart-c4ef27bd-4280-4dc6-a935-e3aa08f01766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064299948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.2064299948 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/32.kmac_lc_escalation/latest

Test location /workspace/coverage/default/15.kmac_burst_write.942909152
Short name T81
Test name
Test status
Simulation time 22414070518 ps
CPU time 944.31 seconds
Started Aug 16 06:07:11 PM PDT 24
Finished Aug 16 06:22:56 PM PDT 24
Peak memory 243200 kb
Host smart-9de31848-026d-4845-8b50-45a090de310b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942909152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.942909152
+enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_burst_write/latest

Test location /workspace/coverage/default/6.kmac_error.1061910316
Short name T161
Test name
Test status
Simulation time 19178208059 ps
CPU time 474.19 seconds
Started Aug 16 06:06:19 PM PDT 24
Finished Aug 16 06:14:13 PM PDT 24
Peak memory 391068 kb
Host smart-b8f5b4c5-8afe-4805-9445-f23bc045ced7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061910316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.1061910316 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_error/latest

Test location /workspace/coverage/default/1.kmac_alert_test.2300167022
Short name T248
Test name
Test status
Simulation time 38755861 ps
CPU time 0.83 seconds
Started Aug 16 06:05:49 PM PDT 24
Finished Aug 16 06:05:50 PM PDT 24
Peak memory 218244 kb
Host smart-94a50390-9673-4a2a-8800-23eb15feb6ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300167022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.2300167022 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_alert_test/latest

Test location /workspace/coverage/default/12.kmac_lc_escalation.3448189832
Short name T31
Test name
Test status
Simulation time 39549720 ps
CPU time 1.37 seconds
Started Aug 16 06:07:13 PM PDT 24
Finished Aug 16 06:07:14 PM PDT 24
Peak memory 226684 kb
Host smart-9fedf484-77d4-4ad4-aff3-09aba9feebc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448189832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.3448189832 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/12.kmac_lc_escalation/latest

Test location /workspace/coverage/default/9.kmac_lc_escalation.388582917
Short name T73
Test name
Test status
Simulation time 44874113 ps
CPU time 1.42 seconds
Started Aug 16 06:06:36 PM PDT 24
Finished Aug 16 06:06:38 PM PDT 24
Peak memory 222732 kb
Host smart-f94d12ea-8a81-45ea-90cf-48b0b1205169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388582917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.388582917 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_lc_escalation/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_256.2776586934
Short name T111
Test name
Test status
Simulation time 50134700740 ps
CPU time 165.88 seconds
Started Aug 16 06:05:51 PM PDT 24
Finished Aug 16 06:08:38 PM PDT 24
Peak memory 354724 kb
Host smart-b93ff0cf-d990-4ff3-b2a0-40ee2fa08250
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2776586934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.2776586934 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/21.kmac_entropy_refresh.27318097
Short name T17
Test name
Test status
Simulation time 12554422244 ps
CPU time 347.17 seconds
Started Aug 16 06:07:47 PM PDT 24
Finished Aug 16 06:13:34 PM PDT 24
Peak memory 460448 kb
Host smart-163fdd39-2498-4e63-81da-61e5d3845ff9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27318097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.273
18097 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_entropy_refresh/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_intr_test.2072903024
Short name T168
Test name
Test status
Simulation time 41985730 ps
CPU time 0.78 seconds
Started Aug 16 06:04:27 PM PDT 24
Finished Aug 16 06:04:28 PM PDT 24
Peak memory 215760 kb
Host smart-c91a6460-f4d3-4e9e-9942-7dc36d0dff78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072903024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.2072903024 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_intr_test/latest

Test location /workspace/coverage/default/41.kmac_app.4059853919
Short name T43
Test name
Test status
Simulation time 7181355197 ps
CPU time 238.46 seconds
Started Aug 16 06:09:34 PM PDT 24
Finished Aug 16 06:13:33 PM PDT 24
Peak memory 305500 kb
Host smart-e38a3963-4598-4d9e-bd68-53324d6207a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059853919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.4059853919 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/41.kmac_app/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.782723965
Short name T179
Test name
Test status
Simulation time 151117147 ps
CPU time 2.56 seconds
Started Aug 16 06:05:23 PM PDT 24
Finished Aug 16 06:05:26 PM PDT 24
Peak memory 216260 kb
Host smart-a3108abd-a9fe-4a53-8b7a-fe93ead5937a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782723965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.78272
3965 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.1387054441
Short name T185
Test name
Test status
Simulation time 103148701 ps
CPU time 4.08 seconds
Started Aug 16 06:05:25 PM PDT 24
Finished Aug 16 06:05:30 PM PDT 24
Peak memory 216016 kb
Host smart-02d1b07c-9cd2-447f-9ad1-d2b0ea5350ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387054441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.1387
054441 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/17.kmac_stress_all.2659526356
Short name T15
Test name
Test status
Simulation time 26025148901 ps
CPU time 2168.78 seconds
Started Aug 16 06:07:30 PM PDT 24
Finished Aug 16 06:43:40 PM PDT 24
Peak memory 744472 kb
Host smart-7fc83412-5192-49d1-902b-d2e42bc1bf77
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2659526356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.2659526356 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.1997083515
Short name T183
Test name
Test status
Simulation time 268202020 ps
CPU time 3.29 seconds
Started Aug 16 06:04:27 PM PDT 24
Finished Aug 16 06:04:30 PM PDT 24
Peak memory 216104 kb
Host smart-e5e17f6a-3fa8-4875-8f8b-7d91735ebad8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997083515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.19970
83515 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_intr_test.656691145
Short name T752
Test name
Test status
Simulation time 50393214 ps
CPU time 0.78 seconds
Started Aug 16 06:05:14 PM PDT 24
Finished Aug 16 06:05:15 PM PDT 24
Peak memory 215708 kb
Host smart-2d220490-2294-41e2-a2fe-40d8762013cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656691145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.656691145 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/10.kmac_intr_test/latest

Test location /workspace/coverage/default/13.kmac_app.2435546671
Short name T174
Test name
Test status
Simulation time 5918699839 ps
CPU time 94.95 seconds
Started Aug 16 06:07:11 PM PDT 24
Finished Aug 16 06:08:46 PM PDT 24
Peak memory 252140 kb
Host smart-015c1e88-9ba7-4ff8-ab1f-ca3ed04d7f0f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435546671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.2435546671 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/13.kmac_app/latest

Test location /workspace/coverage/default/36.kmac_app.963821725
Short name T8
Test name
Test status
Simulation time 1338237539 ps
CPU time 38.87 seconds
Started Aug 16 06:09:02 PM PDT 24
Finished Aug 16 06:09:41 PM PDT 24
Peak memory 251844 kb
Host smart-c364ba85-ab71-4772-bc44-5c7be52c7eb3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963821725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.963821725 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/36.kmac_app/latest

Test location /workspace/coverage/default/0.kmac_error.37870373
Short name T44
Test name
Test status
Simulation time 6520821774 ps
CPU time 246.6 seconds
Started Aug 16 06:05:41 PM PDT 24
Finished Aug 16 06:09:47 PM PDT 24
Peak memory 407360 kb
Host smart-8abece8c-1e21-4b14-99e3-54a31a0b3422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37870373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.37870373 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_error/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.3327960944
Short name T851
Test name
Test status
Simulation time 4127793224 ps
CPU time 6.4 seconds
Started Aug 16 06:04:26 PM PDT 24
Finished Aug 16 06:04:32 PM PDT 24
Peak memory 216088 kb
Host smart-0727314d-9500-48b1-afaa-8c515e8cebe9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327960944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.3327960
944 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.628047703
Short name T834
Test name
Test status
Simulation time 3009370696 ps
CPU time 13.11 seconds
Started Aug 16 06:04:23 PM PDT 24
Finished Aug 16 06:04:36 PM PDT 24
Peak memory 216216 kb
Host smart-e3f392ef-c9a0-45aa-9a93-97212a1facf0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628047703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.62804770
3 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.2688753868
Short name T848
Test name
Test status
Simulation time 25745089 ps
CPU time 0.94 seconds
Started Aug 16 06:04:27 PM PDT 24
Finished Aug 16 06:04:29 PM PDT 24
Peak memory 215900 kb
Host smart-2ec27a5e-3b8b-42b1-adb9-af64c9cd205e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688753868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.2688753
868 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.4210557098
Short name T742
Test name
Test status
Simulation time 120822200 ps
CPU time 1.46 seconds
Started Aug 16 06:04:30 PM PDT 24
Finished Aug 16 06:04:31 PM PDT 24
Peak memory 219452 kb
Host smart-817b2d71-0ce4-495c-bb32-6c1299f4dbc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210557098 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.4210557098 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_rw.3635092106
Short name T783
Test name
Test status
Simulation time 18247838 ps
CPU time 1 seconds
Started Aug 16 06:04:27 PM PDT 24
Finished Aug 16 06:04:29 PM PDT 24
Peak memory 215832 kb
Host smart-ca82fcf4-6df7-4236-8474-e5ed5621acdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635092106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.3635092106 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_walk.2821979347
Short name T837
Test name
Test status
Simulation time 34452136 ps
CPU time 0.75 seconds
Started Aug 16 06:04:30 PM PDT 24
Finished Aug 16 06:04:31 PM PDT 24
Peak memory 215676 kb
Host smart-58aaee4b-3df1-4317-9713-3efb72273b0f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821979347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.2821979347
+enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.2533607404
Short name T857
Test name
Test status
Simulation time 75942596 ps
CPU time 1.46 seconds
Started Aug 16 06:04:27 PM PDT 24
Finished Aug 16 06:04:29 PM PDT 24
Peak memory 216164 kb
Host smart-f39e0607-d5ed-444a-8605-85c50fedb00c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533607404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr
_outstanding.2533607404 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.4148576673
Short name T817
Test name
Test status
Simulation time 109546111 ps
CPU time 1.09 seconds
Started Aug 16 06:04:25 PM PDT 24
Finished Aug 16 06:04:26 PM PDT 24
Peak memory 216292 kb
Host smart-a56cff7f-efab-4718-9b36-29f48f8d22d7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148576673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_
errors.4148576673 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.3978747543
Short name T828
Test name
Test status
Simulation time 39620781 ps
CPU time 1.69 seconds
Started Aug 16 06:04:25 PM PDT 24
Finished Aug 16 06:04:27 PM PDT 24
Peak memory 219752 kb
Host smart-70cca3b4-9379-450a-9cb9-a43905bed039
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978747543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac
_shadow_reg_errors_with_csr_rw.3978747543 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_errors.604418073
Short name T831
Test name
Test status
Simulation time 271116433 ps
CPU time 3.49 seconds
Started Aug 16 06:04:24 PM PDT 24
Finished Aug 16 06:04:28 PM PDT 24
Peak memory 216148 kb
Host smart-c11b0ea2-d46a-4570-9eba-2c729755593e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604418073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.604418073 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/0.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.2232039230
Short name T839
Test name
Test status
Simulation time 136379318 ps
CPU time 7.59 seconds
Started Aug 16 06:04:36 PM PDT 24
Finished Aug 16 06:04:43 PM PDT 24
Peak memory 216124 kb
Host smart-74cc7483-263f-4ae2-8bb1-85be3cd914c2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232039230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.2232039
230 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.592119264
Short name T844
Test name
Test status
Simulation time 1517507134 ps
CPU time 19.98 seconds
Started Aug 16 06:04:33 PM PDT 24
Finished Aug 16 06:04:53 PM PDT 24
Peak memory 216096 kb
Host smart-522edf9d-ab40-4171-be81-b333221692a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592119264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.59211926
4 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.1496622234
Short name T152
Test name
Test status
Simulation time 60773008 ps
CPU time 1.13 seconds
Started Aug 16 06:04:34 PM PDT 24
Finished Aug 16 06:04:35 PM PDT 24
Peak memory 216092 kb
Host smart-3ae72db2-6cc8-4daf-8ac4-c0c246b31626
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496622234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.1496622
234 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.4247918842
Short name T737
Test name
Test status
Simulation time 335784133 ps
CPU time 2.42 seconds
Started Aug 16 06:04:35 PM PDT 24
Finished Aug 16 06:04:38 PM PDT 24
Peak memory 221948 kb
Host smart-5d98feb3-9a36-4281-aa02-8cdf4a4ac61d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247918842 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.4247918842 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_rw.2296106796
Short name T733
Test name
Test status
Simulation time 16308884 ps
CPU time 1.17 seconds
Started Aug 16 06:04:36 PM PDT 24
Finished Aug 16 06:04:37 PM PDT 24
Peak memory 216000 kb
Host smart-0b902154-5473-4b51-bfc1-328ced630d98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296106796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.2296106796 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_intr_test.3002945682
Short name T772
Test name
Test status
Simulation time 15117850 ps
CPU time 0.8 seconds
Started Aug 16 06:04:35 PM PDT 24
Finished Aug 16 06:04:36 PM PDT 24
Peak memory 215848 kb
Host smart-c3b50ee2-e9ac-4573-88ce-04863ac00513
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002945682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.3002945682 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.1667384924
Short name T141
Test name
Test status
Simulation time 502790137 ps
CPU time 1.23 seconds
Started Aug 16 06:04:34 PM PDT 24
Finished Aug 16 06:04:35 PM PDT 24
Peak memory 216064 kb
Host smart-88b6ab90-de4b-4244-8584-63dafe6ad6e6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667384924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia
l_access.1667384924 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_walk.4164211920
Short name T756
Test name
Test status
Simulation time 39312033 ps
CPU time 0.76 seconds
Started Aug 16 06:04:31 PM PDT 24
Finished Aug 16 06:04:32 PM PDT 24
Peak memory 215832 kb
Host smart-6383b90f-5d07-4115-aa2e-675ff0a38d7b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164211920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.4164211920
+enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.2971708550
Short name T729
Test name
Test status
Simulation time 50705234 ps
CPU time 1.51 seconds
Started Aug 16 06:04:35 PM PDT 24
Finished Aug 16 06:04:37 PM PDT 24
Peak memory 216028 kb
Host smart-4676b1fb-6d6c-4a3a-bc82-5e0215b6be1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971708550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr
_outstanding.2971708550 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.104612416
Short name T92
Test name
Test status
Simulation time 65228292 ps
CPU time 0.97 seconds
Started Aug 16 06:04:24 PM PDT 24
Finished Aug 16 06:04:25 PM PDT 24
Peak memory 216220 kb
Host smart-fd963fe6-0b48-40c9-a302-a6e6a4858fd4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104612416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_e
rrors.104612416 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.532062906
Short name T84
Test name
Test status
Simulation time 84317720 ps
CPU time 2.7 seconds
Started Aug 16 06:04:24 PM PDT 24
Finished Aug 16 06:04:27 PM PDT 24
Peak memory 216316 kb
Host smart-a3d22cf1-7e55-47d7-9fb9-a2560331a4df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532062906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_
shadow_reg_errors_with_csr_rw.532062906 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_errors.1635509550
Short name T787
Test name
Test status
Simulation time 247820257 ps
CPU time 2.25 seconds
Started Aug 16 06:04:37 PM PDT 24
Finished Aug 16 06:04:39 PM PDT 24
Peak memory 216224 kb
Host smart-93adb46f-c340-41db-a9a9-63613ad61fc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635509550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.1635509550 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.143153329
Short name T820
Test name
Test status
Simulation time 152494901 ps
CPU time 3.08 seconds
Started Aug 16 06:04:33 PM PDT 24
Finished Aug 16 06:04:36 PM PDT 24
Peak memory 216092 kb
Host smart-fea913b5-5bd7-4258-92c7-63e04b94953d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143153329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.143153
329 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1791337348
Short name T796
Test name
Test status
Simulation time 125757153 ps
CPU time 2.18 seconds
Started Aug 16 06:05:07 PM PDT 24
Finished Aug 16 06:05:09 PM PDT 24
Peak memory 221172 kb
Host smart-4efb88cb-0f4b-4691-8c2f-73f2e7544a3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791337348 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.1791337348 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_rw.2745218141
Short name T154
Test name
Test status
Simulation time 61042319 ps
CPU time 1.24 seconds
Started Aug 16 06:05:07 PM PDT 24
Finished Aug 16 06:05:08 PM PDT 24
Peak memory 216084 kb
Host smart-897001a5-f38d-4709-a076-3bbe9fc85849
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745218141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.2745218141 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.2874357297
Short name T758
Test name
Test status
Simulation time 37857461 ps
CPU time 2.26 seconds
Started Aug 16 06:05:09 PM PDT 24
Finished Aug 16 06:05:11 PM PDT 24
Peak memory 216156 kb
Host smart-d0b5b72c-e45f-485f-9d43-95357a918353
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874357297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs
r_outstanding.2874357297 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.1238743955
Short name T799
Test name
Test status
Simulation time 59613024 ps
CPU time 1.01 seconds
Started Aug 16 06:05:07 PM PDT 24
Finished Aug 16 06:05:08 PM PDT 24
Peak memory 216124 kb
Host smart-282eb878-756f-43f1-9ebb-8f305c1834ee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238743955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg
_errors.1238743955 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3168514260
Short name T745
Test name
Test status
Simulation time 47019529 ps
CPU time 2.26 seconds
Started Aug 16 06:05:10 PM PDT 24
Finished Aug 16 06:05:12 PM PDT 24
Peak memory 219476 kb
Host smart-fcfb492a-c497-41e2-9412-0a1c57abab4c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168514260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kma
c_shadow_reg_errors_with_csr_rw.3168514260 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_errors.3936652864
Short name T774
Test name
Test status
Simulation time 56782634 ps
CPU time 1.69 seconds
Started Aug 16 06:05:12 PM PDT 24
Finished Aug 16 06:05:14 PM PDT 24
Peak memory 215996 kb
Host smart-c3ecbed0-002d-432b-92a4-4e18af62f11b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936652864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.3936652864 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.2098628388
Short name T800
Test name
Test status
Simulation time 199629560 ps
CPU time 4.26 seconds
Started Aug 16 06:05:08 PM PDT 24
Finished Aug 16 06:05:12 PM PDT 24
Peak memory 216020 kb
Host smart-b6d547d8-be84-4d64-851e-370ce4a93715
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098628388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.2098
628388 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.3237337445
Short name T798
Test name
Test status
Simulation time 74959104 ps
CPU time 1.71 seconds
Started Aug 16 06:05:07 PM PDT 24
Finished Aug 16 06:05:08 PM PDT 24
Peak memory 219892 kb
Host smart-0a1ce4a8-b0bb-4481-bcfc-3e6fc7c77ecd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237337445 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.3237337445 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_rw.672901796
Short name T767
Test name
Test status
Simulation time 31022656 ps
CPU time 1.16 seconds
Started Aug 16 06:05:07 PM PDT 24
Finished Aug 16 06:05:09 PM PDT 24
Peak memory 216064 kb
Host smart-b01a6dcf-d82b-4962-ae94-4647fb5c9c43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672901796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.672901796 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/11.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_intr_test.3017133496
Short name T778
Test name
Test status
Simulation time 21726790 ps
CPU time 0.79 seconds
Started Aug 16 06:05:09 PM PDT 24
Finished Aug 16 06:05:10 PM PDT 24
Peak memory 215824 kb
Host smart-8dfd7ddb-84e1-4cf2-8d8d-3a5c8f4c0089
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017133496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.3017133496 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.4234811961
Short name T715
Test name
Test status
Simulation time 28665695 ps
CPU time 1.5 seconds
Started Aug 16 06:05:07 PM PDT 24
Finished Aug 16 06:05:09 PM PDT 24
Peak memory 216164 kb
Host smart-b7c7dee6-0dee-4915-b57a-67db325f0e7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234811961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs
r_outstanding.4234811961 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.623517030
Short name T765
Test name
Test status
Simulation time 29173056 ps
CPU time 1.07 seconds
Started Aug 16 06:05:08 PM PDT 24
Finished Aug 16 06:05:09 PM PDT 24
Peak memory 216312 kb
Host smart-007b132e-ee27-46c4-b2e8-597ebc0e156f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623517030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_
errors.623517030 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.831831019
Short name T794
Test name
Test status
Simulation time 401425396 ps
CPU time 2.6 seconds
Started Aug 16 06:05:12 PM PDT 24
Finished Aug 16 06:05:15 PM PDT 24
Peak memory 218460 kb
Host smart-a5cd7463-9502-4455-a5bd-e1e3a7ecff5f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831831019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac
_shadow_reg_errors_with_csr_rw.831831019 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_errors.4152653997
Short name T127
Test name
Test status
Simulation time 127281644 ps
CPU time 2.01 seconds
Started Aug 16 06:05:11 PM PDT 24
Finished Aug 16 06:05:13 PM PDT 24
Peak memory 216228 kb
Host smart-da303c92-e4f4-4a9f-b1f2-23f731e57783
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152653997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.4152653997 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.4276159989
Short name T779
Test name
Test status
Simulation time 193645425 ps
CPU time 2.81 seconds
Started Aug 16 06:05:10 PM PDT 24
Finished Aug 16 06:05:13 PM PDT 24
Peak memory 216068 kb
Host smart-e35c3d28-6bbe-41df-a6b6-12e285e55c00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276159989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.4276
159989 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2049090174
Short name T125
Test name
Test status
Simulation time 32973309 ps
CPU time 2.22 seconds
Started Aug 16 06:05:37 PM PDT 24
Finished Aug 16 06:05:40 PM PDT 24
Peak memory 221408 kb
Host smart-01a4fabb-ee5c-474d-8fa5-6563c5ae3631
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049090174 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.2049090174 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_rw.4256674862
Short name T849
Test name
Test status
Simulation time 47654940 ps
CPU time 1.05 seconds
Started Aug 16 06:05:15 PM PDT 24
Finished Aug 16 06:05:16 PM PDT 24
Peak memory 216084 kb
Host smart-003d3df3-6318-45d0-b9eb-ad4c8cb68982
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256674862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.4256674862 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_intr_test.3749462819
Short name T784
Test name
Test status
Simulation time 98970109 ps
CPU time 0.81 seconds
Started Aug 16 06:05:15 PM PDT 24
Finished Aug 16 06:05:16 PM PDT 24
Peak memory 215808 kb
Host smart-4299fb7e-b721-4014-882a-64c89fcc78ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749462819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.3749462819 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.2676851452
Short name T846
Test name
Test status
Simulation time 122823231 ps
CPU time 2.85 seconds
Started Aug 16 06:05:15 PM PDT 24
Finished Aug 16 06:05:18 PM PDT 24
Peak memory 216124 kb
Host smart-c745ae9c-40a4-408a-bb0d-d553af9852af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676851452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_cs
r_outstanding.2676851452 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2501583023
Short name T782
Test name
Test status
Simulation time 104894487 ps
CPU time 1.18 seconds
Started Aug 16 06:05:05 PM PDT 24
Finished Aug 16 06:05:07 PM PDT 24
Peak memory 216416 kb
Host smart-b1176a21-940b-4db8-89ad-0a9814e21299
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501583023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg
_errors.2501583023 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.3007506238
Short name T754
Test name
Test status
Simulation time 393315638 ps
CPU time 3.08 seconds
Started Aug 16 06:05:15 PM PDT 24
Finished Aug 16 06:05:19 PM PDT 24
Peak memory 219776 kb
Host smart-e0d05d8e-dd8b-431c-8eb7-90a4d2d00690
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007506238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kma
c_shadow_reg_errors_with_csr_rw.3007506238 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_errors.1374294506
Short name T760
Test name
Test status
Simulation time 443660388 ps
CPU time 2.6 seconds
Started Aug 16 06:05:12 PM PDT 24
Finished Aug 16 06:05:15 PM PDT 24
Peak memory 216200 kb
Host smart-556aa812-fff2-4cc8-93ba-bd106e0ae149
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374294506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.1374294506 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1579079582
Short name T722
Test name
Test status
Simulation time 176578139 ps
CPU time 1.56 seconds
Started Aug 16 06:05:20 PM PDT 24
Finished Aug 16 06:05:21 PM PDT 24
Peak memory 218724 kb
Host smart-04cfc2ab-7278-4d30-85fd-778fff0f5b35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579079582 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.1579079582 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_rw.3729090185
Short name T153
Test name
Test status
Simulation time 44442411 ps
CPU time 1.11 seconds
Started Aug 16 06:05:13 PM PDT 24
Finished Aug 16 06:05:14 PM PDT 24
Peak memory 216032 kb
Host smart-ca83b93d-7e4b-4b04-930e-4e1826ab29f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729090185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.3729090185 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_intr_test.4253589025
Short name T776
Test name
Test status
Simulation time 16748206 ps
CPU time 0.81 seconds
Started Aug 16 06:05:16 PM PDT 24
Finished Aug 16 06:05:17 PM PDT 24
Peak memory 215560 kb
Host smart-dcd1a0fd-1011-4008-9233-d78346a89cc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253589025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.4253589025 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3048737842
Short name T159
Test name
Test status
Simulation time 120834018 ps
CPU time 1.69 seconds
Started Aug 16 06:05:18 PM PDT 24
Finished Aug 16 06:05:20 PM PDT 24
Peak memory 216104 kb
Host smart-a4d8bb77-eb9b-43ac-ad21-e09b6ec52c25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048737842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs
r_outstanding.3048737842 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3246558442
Short name T795
Test name
Test status
Simulation time 46399438 ps
CPU time 1.16 seconds
Started Aug 16 06:05:16 PM PDT 24
Finished Aug 16 06:05:17 PM PDT 24
Peak memory 216388 kb
Host smart-21ccdb76-ba2f-4f9b-bd3f-d3a3b76638b7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246558442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg
_errors.3246558442 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.1248209988
Short name T866
Test name
Test status
Simulation time 102939042 ps
CPU time 1.77 seconds
Started Aug 16 06:05:16 PM PDT 24
Finished Aug 16 06:05:18 PM PDT 24
Peak memory 219728 kb
Host smart-e5303350-4d6d-4cd4-846b-306e5c6d698c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248209988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma
c_shadow_reg_errors_with_csr_rw.1248209988 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_errors.2799317667
Short name T829
Test name
Test status
Simulation time 59738871 ps
CPU time 1.95 seconds
Started Aug 16 06:05:16 PM PDT 24
Finished Aug 16 06:05:18 PM PDT 24
Peak memory 216092 kb
Host smart-3e7544c9-6ecb-48ec-bd50-11c020c770ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799317667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.2799317667 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.1782836377
Short name T181
Test name
Test status
Simulation time 562451875 ps
CPU time 4.02 seconds
Started Aug 16 06:05:18 PM PDT 24
Finished Aug 16 06:05:22 PM PDT 24
Peak memory 216152 kb
Host smart-b0980764-7dfa-4a72-8573-ce250dc7157a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782836377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.1782
836377 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.653837909
Short name T749
Test name
Test status
Simulation time 125478072 ps
CPU time 1.85 seconds
Started Aug 16 06:05:27 PM PDT 24
Finished Aug 16 06:05:29 PM PDT 24
Peak memory 221016 kb
Host smart-b070388e-1e4c-44dd-a9a2-381752b31b52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653837909 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.653837909 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_rw.2329168112
Short name T757
Test name
Test status
Simulation time 48968892 ps
CPU time 1.06 seconds
Started Aug 16 06:05:27 PM PDT 24
Finished Aug 16 06:05:28 PM PDT 24
Peak memory 216084 kb
Host smart-7e48826c-edc2-4d02-8f7b-36766f47e2ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329168112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.2329168112 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_intr_test.2924925295
Short name T815
Test name
Test status
Simulation time 25642235 ps
CPU time 0.8 seconds
Started Aug 16 06:05:19 PM PDT 24
Finished Aug 16 06:05:20 PM PDT 24
Peak memory 215700 kb
Host smart-08bc78dc-9eb6-4c90-bccf-dc5624c373f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924925295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.2924925295 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.1650659657
Short name T843
Test name
Test status
Simulation time 29692040 ps
CPU time 1.52 seconds
Started Aug 16 06:05:23 PM PDT 24
Finished Aug 16 06:05:25 PM PDT 24
Peak memory 216084 kb
Host smart-50ee1f03-d87e-41d2-8e73-4fdc04fffb04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650659657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_cs
r_outstanding.1650659657 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2088310985
Short name T93
Test name
Test status
Simulation time 47952648 ps
CPU time 1.4 seconds
Started Aug 16 06:05:15 PM PDT 24
Finished Aug 16 06:05:16 PM PDT 24
Peak memory 217576 kb
Host smart-a8012571-572a-4915-81c6-1e6197362ef9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088310985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg
_errors.2088310985 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.3244674585
Short name T769
Test name
Test status
Simulation time 90922994 ps
CPU time 2.28 seconds
Started Aug 16 06:05:14 PM PDT 24
Finished Aug 16 06:05:16 PM PDT 24
Peak memory 219260 kb
Host smart-efac6531-914e-446a-9add-82e35765aac6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244674585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kma
c_shadow_reg_errors_with_csr_rw.3244674585 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_errors.736614621
Short name T755
Test name
Test status
Simulation time 61638503 ps
CPU time 3.97 seconds
Started Aug 16 06:05:14 PM PDT 24
Finished Aug 16 06:05:18 PM PDT 24
Peak memory 216176 kb
Host smart-0efda88d-e3d5-4918-8e99-30cdee5707fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736614621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.736614621 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/14.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.2233159174
Short name T189
Test name
Test status
Simulation time 195232849 ps
CPU time 2.98 seconds
Started Aug 16 06:05:18 PM PDT 24
Finished Aug 16 06:05:21 PM PDT 24
Peak memory 215964 kb
Host smart-4bdeaf41-a311-4275-b40b-93070d46cd06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233159174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.2233
159174 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1345974839
Short name T826
Test name
Test status
Simulation time 92682445 ps
CPU time 1.74 seconds
Started Aug 16 06:05:25 PM PDT 24
Finished Aug 16 06:05:26 PM PDT 24
Peak memory 221344 kb
Host smart-4795b9e6-ea5c-4143-bce9-399aab0575e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345974839 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.1345974839 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_rw.2637514686
Short name T721
Test name
Test status
Simulation time 31639777 ps
CPU time 0.97 seconds
Started Aug 16 06:05:27 PM PDT 24
Finished Aug 16 06:05:28 PM PDT 24
Peak memory 215804 kb
Host smart-1b54dbdb-782a-4f1d-8812-d7f95f37073b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637514686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.2637514686 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_intr_test.3042732590
Short name T735
Test name
Test status
Simulation time 27198632 ps
CPU time 0.82 seconds
Started Aug 16 06:05:28 PM PDT 24
Finished Aug 16 06:05:29 PM PDT 24
Peak memory 215708 kb
Host smart-4d3524ff-9d12-40cf-b502-af2edb811de3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042732590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.3042732590 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2722703519
Short name T150
Test name
Test status
Simulation time 228914672 ps
CPU time 1.62 seconds
Started Aug 16 06:05:23 PM PDT 24
Finished Aug 16 06:05:24 PM PDT 24
Peak memory 216044 kb
Host smart-205a09b7-725e-4da9-8449-d7e8e9061451
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722703519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_cs
r_outstanding.2722703519 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.151866557
Short name T803
Test name
Test status
Simulation time 34867245 ps
CPU time 1.18 seconds
Started Aug 16 06:05:25 PM PDT 24
Finished Aug 16 06:05:26 PM PDT 24
Peak memory 216316 kb
Host smart-0ff5bf8c-19db-42ff-8930-74ad2ba6449f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151866557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_
errors.151866557 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.1373940446
Short name T835
Test name
Test status
Simulation time 104512824 ps
CPU time 1.8 seconds
Started Aug 16 06:05:24 PM PDT 24
Finished Aug 16 06:05:26 PM PDT 24
Peak memory 216404 kb
Host smart-0d76cb0e-043c-4530-a9ca-c58f6c306883
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373940446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kma
c_shadow_reg_errors_with_csr_rw.1373940446 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_errors.1765743050
Short name T123
Test name
Test status
Simulation time 554309927 ps
CPU time 3.69 seconds
Started Aug 16 06:05:24 PM PDT 24
Finished Aug 16 06:05:28 PM PDT 24
Peak memory 216132 kb
Host smart-caa6bbdf-5f97-4367-b542-5182eb21a14b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765743050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.1765743050 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.4045294881
Short name T180
Test name
Test status
Simulation time 997499024 ps
CPU time 4.8 seconds
Started Aug 16 06:05:27 PM PDT 24
Finished Aug 16 06:05:32 PM PDT 24
Peak memory 215972 kb
Host smart-71c0ea3f-b9cc-40d8-88cd-b9595079b84a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045294881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.4045
294881 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2781303836
Short name T802
Test name
Test status
Simulation time 70044255 ps
CPU time 1.65 seconds
Started Aug 16 06:05:23 PM PDT 24
Finished Aug 16 06:05:25 PM PDT 24
Peak memory 217564 kb
Host smart-cfd94113-2c85-4ede-a826-b6bafc9f6b57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781303836 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.2781303836 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_rw.1897734089
Short name T759
Test name
Test status
Simulation time 72618828 ps
CPU time 0.93 seconds
Started Aug 16 06:05:23 PM PDT 24
Finished Aug 16 06:05:24 PM PDT 24
Peak memory 215832 kb
Host smart-25c93621-3a4e-40f2-ae09-cf0d10a04b72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897734089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.1897734089 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_intr_test.3820568516
Short name T792
Test name
Test status
Simulation time 14067180 ps
CPU time 0.82 seconds
Started Aug 16 06:05:24 PM PDT 24
Finished Aug 16 06:05:25 PM PDT 24
Peak memory 215732 kb
Host smart-2dc8b23d-cc7f-4199-b612-d31e3499f045
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820568516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.3820568516 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.1852889900
Short name T819
Test name
Test status
Simulation time 218200726 ps
CPU time 1.64 seconds
Started Aug 16 06:05:29 PM PDT 24
Finished Aug 16 06:05:31 PM PDT 24
Peak memory 215944 kb
Host smart-5e79e55e-bf27-4a87-a4ee-19f96c3a7cfc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852889900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_cs
r_outstanding.1852889900 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.2411089082
Short name T94
Test name
Test status
Simulation time 163634173 ps
CPU time 1.37 seconds
Started Aug 16 06:05:24 PM PDT 24
Finished Aug 16 06:05:26 PM PDT 24
Peak memory 216696 kb
Host smart-cefb1b97-e21b-4af4-8d60-0a1932a4921d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411089082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg
_errors.2411089082 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.70220904
Short name T842
Test name
Test status
Simulation time 223471557 ps
CPU time 1.93 seconds
Started Aug 16 06:05:26 PM PDT 24
Finished Aug 16 06:05:28 PM PDT 24
Peak memory 219352 kb
Host smart-211e5993-7a81-426e-a50c-230ea45c41df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70220904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_
shadow_reg_errors_with_csr_rw.70220904 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_errors.2037112864
Short name T122
Test name
Test status
Simulation time 197566332 ps
CPU time 3.34 seconds
Started Aug 16 06:05:25 PM PDT 24
Finished Aug 16 06:05:29 PM PDT 24
Peak memory 216168 kb
Host smart-91d41791-077d-4b8d-ba76-9247e37c4d6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037112864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.2037112864 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.4119793452
Short name T736
Test name
Test status
Simulation time 137230377 ps
CPU time 2.44 seconds
Started Aug 16 06:05:28 PM PDT 24
Finished Aug 16 06:05:31 PM PDT 24
Peak memory 222332 kb
Host smart-315545a9-4e5d-48da-b234-c685adccf809
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119793452 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.4119793452 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_rw.1589504116
Short name T724
Test name
Test status
Simulation time 16289112 ps
CPU time 0.98 seconds
Started Aug 16 06:05:22 PM PDT 24
Finished Aug 16 06:05:23 PM PDT 24
Peak memory 215932 kb
Host smart-ec9110c1-9154-4674-bd3a-d5831f5d31c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589504116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.1589504116 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_intr_test.1928416877
Short name T121
Test name
Test status
Simulation time 13932580 ps
CPU time 0.78 seconds
Started Aug 16 06:05:29 PM PDT 24
Finished Aug 16 06:05:30 PM PDT 24
Peak memory 215732 kb
Host smart-572ebcb3-9d33-41e8-ad5c-ffce85fa9129
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928416877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.1928416877 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.1019544514
Short name T716
Test name
Test status
Simulation time 52396607 ps
CPU time 1.59 seconds
Started Aug 16 06:05:27 PM PDT 24
Finished Aug 16 06:05:29 PM PDT 24
Peak memory 215964 kb
Host smart-a6fb0e31-8b48-4135-b1bc-da550a13baf2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019544514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs
r_outstanding.1019544514 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2745116260
Short name T804
Test name
Test status
Simulation time 32377856 ps
CPU time 1.24 seconds
Started Aug 16 06:05:25 PM PDT 24
Finished Aug 16 06:05:26 PM PDT 24
Peak memory 217492 kb
Host smart-a3433290-41df-4a5a-adad-15ca34b4f710
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745116260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg
_errors.2745116260 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1965599962
Short name T830
Test name
Test status
Simulation time 103785727 ps
CPU time 2.75 seconds
Started Aug 16 06:05:24 PM PDT 24
Finished Aug 16 06:05:27 PM PDT 24
Peak memory 218748 kb
Host smart-19262624-ba18-41a4-ae0c-eaa6cf615a12
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965599962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kma
c_shadow_reg_errors_with_csr_rw.1965599962 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_errors.142703303
Short name T823
Test name
Test status
Simulation time 350265438 ps
CPU time 2.64 seconds
Started Aug 16 06:05:26 PM PDT 24
Finished Aug 16 06:05:29 PM PDT 24
Peak memory 216064 kb
Host smart-4e936869-4696-4eb2-b342-9abd3a46253b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142703303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.142703303 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/17.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.969504199
Short name T816
Test name
Test status
Simulation time 1019403429 ps
CPU time 3.09 seconds
Started Aug 16 06:05:25 PM PDT 24
Finished Aug 16 06:05:28 PM PDT 24
Peak memory 216080 kb
Host smart-f676ee99-8e97-4d0d-967d-ac9698ac6708
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969504199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.96950
4199 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.614100277
Short name T764
Test name
Test status
Simulation time 87399665 ps
CPU time 2.53 seconds
Started Aug 16 06:05:33 PM PDT 24
Finished Aug 16 06:05:36 PM PDT 24
Peak memory 217828 kb
Host smart-e4c2a203-ca03-440f-b420-e1ca52a0add8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614100277 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.614100277 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_rw.1960286440
Short name T747
Test name
Test status
Simulation time 16866690 ps
CPU time 0.92 seconds
Started Aug 16 06:05:30 PM PDT 24
Finished Aug 16 06:05:31 PM PDT 24
Peak memory 215780 kb
Host smart-7c6e7a12-c224-4ff3-b928-c170ee18a9f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960286440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.1960286440 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_intr_test.866012281
Short name T797
Test name
Test status
Simulation time 18082888 ps
CPU time 0.86 seconds
Started Aug 16 06:05:29 PM PDT 24
Finished Aug 16 06:05:30 PM PDT 24
Peak memory 215712 kb
Host smart-7641fff1-0c18-4704-8e7a-d12d5d4fabc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866012281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.866012281 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/18.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.533660084
Short name T781
Test name
Test status
Simulation time 36908640 ps
CPU time 1.46 seconds
Started Aug 16 06:05:25 PM PDT 24
Finished Aug 16 06:05:27 PM PDT 24
Peak memory 216032 kb
Host smart-eb8481cd-94ff-4061-94f5-cc0bcafedf24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533660084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr
_outstanding.533660084 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1273185951
Short name T85
Test name
Test status
Simulation time 34513739 ps
CPU time 1.08 seconds
Started Aug 16 06:05:24 PM PDT 24
Finished Aug 16 06:05:25 PM PDT 24
Peak memory 216236 kb
Host smart-cc4e9a7f-1d7f-405e-9ccf-70ae03d126ae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273185951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg
_errors.1273185951 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3036176474
Short name T807
Test name
Test status
Simulation time 169657272 ps
CPU time 2.3 seconds
Started Aug 16 06:05:24 PM PDT 24
Finished Aug 16 06:05:26 PM PDT 24
Peak memory 219684 kb
Host smart-14e007bf-2064-47f3-b09a-97fc20a8e29e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036176474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma
c_shadow_reg_errors_with_csr_rw.3036176474 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_errors.4213274519
Short name T158
Test name
Test status
Simulation time 180231751 ps
CPU time 2.41 seconds
Started Aug 16 06:05:32 PM PDT 24
Finished Aug 16 06:05:34 PM PDT 24
Peak memory 216092 kb
Host smart-782c92be-53df-4969-87c0-fe1abce775bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213274519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.4213274519 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.4128016410
Short name T740
Test name
Test status
Simulation time 84373785 ps
CPU time 1.53 seconds
Started Aug 16 06:05:37 PM PDT 24
Finished Aug 16 06:05:39 PM PDT 24
Peak memory 220176 kb
Host smart-2754200a-c3b2-4bf7-90b5-e0d74b2d9c53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128016410 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.4128016410 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_rw.3434318636
Short name T732
Test name
Test status
Simulation time 49900150 ps
CPU time 1 seconds
Started Aug 16 06:05:34 PM PDT 24
Finished Aug 16 06:05:35 PM PDT 24
Peak memory 215920 kb
Host smart-9111c0c9-602c-4873-b379-c8d057d33c4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434318636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.3434318636 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_intr_test.4289743945
Short name T805
Test name
Test status
Simulation time 26192076 ps
CPU time 0.78 seconds
Started Aug 16 06:05:33 PM PDT 24
Finished Aug 16 06:05:33 PM PDT 24
Peak memory 215776 kb
Host smart-626688f2-a29b-4905-87b0-b9e421493e4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289743945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.4289743945 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.289470383
Short name T858
Test name
Test status
Simulation time 83692048 ps
CPU time 1.59 seconds
Started Aug 16 06:05:32 PM PDT 24
Finished Aug 16 06:05:34 PM PDT 24
Peak memory 216092 kb
Host smart-0a6a1f5e-81f8-42b7-b9a9-74d66d818d42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289470383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr
_outstanding.289470383 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.1603310177
Short name T838
Test name
Test status
Simulation time 300889636 ps
CPU time 1.29 seconds
Started Aug 16 06:05:32 PM PDT 24
Finished Aug 16 06:05:33 PM PDT 24
Peak memory 216468 kb
Host smart-93244968-e869-4b9b-b4e5-4ec30ba3e5e9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603310177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg
_errors.1603310177 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.444666827
Short name T89
Test name
Test status
Simulation time 135421798 ps
CPU time 2.94 seconds
Started Aug 16 06:05:33 PM PDT 24
Finished Aug 16 06:05:36 PM PDT 24
Peak memory 219992 kb
Host smart-b5a35b8d-b519-460b-bfa0-63b00b332ff3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444666827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac
_shadow_reg_errors_with_csr_rw.444666827 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_errors.2990057190
Short name T128
Test name
Test status
Simulation time 539862924 ps
CPU time 3.69 seconds
Started Aug 16 06:05:33 PM PDT 24
Finished Aug 16 06:05:37 PM PDT 24
Peak memory 216064 kb
Host smart-ec975bbe-7a2c-4f28-b3b4-62896073baff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990057190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.2990057190 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.1144927284
Short name T184
Test name
Test status
Simulation time 535118936 ps
CPU time 5.75 seconds
Started Aug 16 06:05:33 PM PDT 24
Finished Aug 16 06:05:39 PM PDT 24
Peak memory 215924 kb
Host smart-7859f170-5540-42b6-80ee-521bb896b5b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144927284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.1144
927284 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.708268335
Short name T840
Test name
Test status
Simulation time 83737863 ps
CPU time 4.22 seconds
Started Aug 16 06:04:42 PM PDT 24
Finished Aug 16 06:04:46 PM PDT 24
Peak memory 216032 kb
Host smart-95e5913f-f977-45bf-88b4-0ea7e2d34e20
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708268335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.70826833
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.761093551
Short name T191
Test name
Test status
Simulation time 508750510 ps
CPU time 9.63 seconds
Started Aug 16 06:04:41 PM PDT 24
Finished Aug 16 06:04:51 PM PDT 24
Peak memory 216128 kb
Host smart-46880046-5566-433c-870e-bef881f8eb0d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761093551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.76109355
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.3073188203
Short name T119
Test name
Test status
Simulation time 116721168 ps
CPU time 1.06 seconds
Started Aug 16 06:04:41 PM PDT 24
Finished Aug 16 06:04:42 PM PDT 24
Peak memory 216088 kb
Host smart-e9796009-3e9e-4a7e-9f4f-8bcaf5dfc6dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073188203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.3073188
203 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.3251231255
Short name T847
Test name
Test status
Simulation time 82076564 ps
CPU time 2.32 seconds
Started Aug 16 06:04:44 PM PDT 24
Finished Aug 16 06:04:47 PM PDT 24
Peak memory 219700 kb
Host smart-d6096b10-eaac-419b-8214-78eaebd776d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251231255 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.3251231255 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_rw.1544954796
Short name T151
Test name
Test status
Simulation time 31179256 ps
CPU time 1.14 seconds
Started Aug 16 06:04:44 PM PDT 24
Finished Aug 16 06:04:45 PM PDT 24
Peak memory 215884 kb
Host smart-5c3c7add-6a2d-4cbc-8e15-4f54840b49fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544954796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.1544954796 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_intr_test.754220290
Short name T785
Test name
Test status
Simulation time 29465010 ps
CPU time 0.79 seconds
Started Aug 16 06:04:40 PM PDT 24
Finished Aug 16 06:04:41 PM PDT 24
Peak memory 215724 kb
Host smart-33f27489-d053-4ee2-b0be-1e5d8270ed9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754220290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.754220290 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/2.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.55907652
Short name T138
Test name
Test status
Simulation time 77432069 ps
CPU time 1.37 seconds
Started Aug 16 06:04:41 PM PDT 24
Finished Aug 16 06:04:42 PM PDT 24
Peak memory 216008 kb
Host smart-eeb4f03f-6de7-47a3-ac53-564a5fe9346c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55907652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial_
access.55907652 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_walk.4226050355
Short name T730
Test name
Test status
Simulation time 17371379 ps
CPU time 0.72 seconds
Started Aug 16 06:04:40 PM PDT 24
Finished Aug 16 06:04:41 PM PDT 24
Peak memory 215692 kb
Host smart-eb9abd9e-1118-47f4-a724-3267a3a996ac
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226050355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.4226050355
+enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.963116306
Short name T862
Test name
Test status
Simulation time 409996470 ps
CPU time 2.74 seconds
Started Aug 16 06:04:44 PM PDT 24
Finished Aug 16 06:04:47 PM PDT 24
Peak memory 215960 kb
Host smart-0250f122-2a78-452e-a0b2-c5f498c5d58f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963116306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_
outstanding.963116306 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.1616061755
Short name T192
Test name
Test status
Simulation time 105090547 ps
CPU time 1.18 seconds
Started Aug 16 06:04:53 PM PDT 24
Finished Aug 16 06:04:54 PM PDT 24
Peak memory 216412 kb
Host smart-2d6f47a8-6b6f-42ea-9ebe-9dc9e94bd457
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616061755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_
errors.1616061755 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.3244200921
Short name T95
Test name
Test status
Simulation time 78671570 ps
CPU time 1.88 seconds
Started Aug 16 06:04:42 PM PDT 24
Finished Aug 16 06:04:44 PM PDT 24
Peak memory 219768 kb
Host smart-6f832acd-af4e-4154-96de-a55a626e3e1c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244200921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac
_shadow_reg_errors_with_csr_rw.3244200921 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_errors.1447908192
Short name T124
Test name
Test status
Simulation time 179591311 ps
CPU time 1.69 seconds
Started Aug 16 06:04:42 PM PDT 24
Finished Aug 16 06:04:44 PM PDT 24
Peak memory 216100 kb
Host smart-077316b7-b651-4523-a4eb-f9bd6c13eeac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447908192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.1447908192 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.3722516307
Short name T178
Test name
Test status
Simulation time 353616410 ps
CPU time 4.14 seconds
Started Aug 16 06:04:45 PM PDT 24
Finished Aug 16 06:04:49 PM PDT 24
Peak memory 216160 kb
Host smart-50a779d5-5bd1-49a3-b0b7-c7ef6d87ec29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722516307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.37225
16307 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.kmac_intr_test.549541033
Short name T739
Test name
Test status
Simulation time 18466490 ps
CPU time 0.82 seconds
Started Aug 16 06:05:32 PM PDT 24
Finished Aug 16 06:05:33 PM PDT 24
Peak memory 215868 kb
Host smart-982e293d-8ac3-40a8-b27c-b777d9ae645d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549541033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.549541033 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/20.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.kmac_intr_test.403929791
Short name T827
Test name
Test status
Simulation time 65085845 ps
CPU time 0.83 seconds
Started Aug 16 06:05:33 PM PDT 24
Finished Aug 16 06:05:34 PM PDT 24
Peak memory 215800 kb
Host smart-48e46bc0-9740-499c-b7dc-3a631f2ecfd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403929791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.403929791 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/21.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.kmac_intr_test.2407460252
Short name T766
Test name
Test status
Simulation time 115490648 ps
CPU time 0.8 seconds
Started Aug 16 06:05:34 PM PDT 24
Finished Aug 16 06:05:35 PM PDT 24
Peak memory 215840 kb
Host smart-1281a973-c676-426e-9848-01d4883b3841
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407460252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.2407460252 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.kmac_intr_test.2446292573
Short name T165
Test name
Test status
Simulation time 36443031 ps
CPU time 0.8 seconds
Started Aug 16 06:05:32 PM PDT 24
Finished Aug 16 06:05:33 PM PDT 24
Peak memory 215688 kb
Host smart-83df217a-f1ce-48d4-93c6-12f1564c0f50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446292573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.2446292573 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.kmac_intr_test.80027839
Short name T822
Test name
Test status
Simulation time 36423752 ps
CPU time 0.81 seconds
Started Aug 16 06:05:36 PM PDT 24
Finished Aug 16 06:05:36 PM PDT 24
Peak memory 215824 kb
Host smart-dd85b7ff-fbf2-4651-a6b9-ddf71f09978d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80027839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.80027839 +enable_mas
king=1 +sw_key_masked=0
Directory /workspace/24.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.kmac_intr_test.1057789138
Short name T824
Test name
Test status
Simulation time 90429104 ps
CPU time 0.82 seconds
Started Aug 16 06:05:33 PM PDT 24
Finished Aug 16 06:05:34 PM PDT 24
Peak memory 215876 kb
Host smart-b7fd2bb9-a5ae-4fce-a19b-258a87e9a227
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057789138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.1057789138 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.kmac_intr_test.2974726955
Short name T727
Test name
Test status
Simulation time 17869161 ps
CPU time 0.81 seconds
Started Aug 16 06:05:40 PM PDT 24
Finished Aug 16 06:05:40 PM PDT 24
Peak memory 215756 kb
Host smart-9d9447af-86c6-4f85-b0ae-0540fbb79477
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974726955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.2974726955 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.kmac_intr_test.3713413733
Short name T156
Test name
Test status
Simulation time 27091029 ps
CPU time 0.79 seconds
Started Aug 16 06:05:33 PM PDT 24
Finished Aug 16 06:05:34 PM PDT 24
Peak memory 215768 kb
Host smart-085d3379-d5ad-4ec4-9384-2a43826743f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713413733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.3713413733 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.kmac_intr_test.733707688
Short name T171
Test name
Test status
Simulation time 19959443 ps
CPU time 0.78 seconds
Started Aug 16 06:05:34 PM PDT 24
Finished Aug 16 06:05:35 PM PDT 24
Peak memory 215836 kb
Host smart-2bde702f-df4f-4746-a8c8-26357d8410ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733707688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.733707688 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/28.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.kmac_intr_test.3311402139
Short name T120
Test name
Test status
Simulation time 49898866 ps
CPU time 0.79 seconds
Started Aug 16 06:05:31 PM PDT 24
Finished Aug 16 06:05:32 PM PDT 24
Peak memory 215700 kb
Host smart-535a4c31-830a-411b-a31a-8e3a28c48099
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311402139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.3311402139 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.4055412664
Short name T821
Test name
Test status
Simulation time 206128456 ps
CPU time 5.03 seconds
Started Aug 16 06:04:41 PM PDT 24
Finished Aug 16 06:04:46 PM PDT 24
Peak memory 216000 kb
Host smart-43ce2294-f564-48d8-84f3-14e34898f021
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055412664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.4055412
664 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.2587573647
Short name T768
Test name
Test status
Simulation time 5749435186 ps
CPU time 20.01 seconds
Started Aug 16 06:04:43 PM PDT 24
Finished Aug 16 06:05:03 PM PDT 24
Peak memory 216116 kb
Host smart-02b9af6f-18cd-4b14-8545-9d7308944619
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587573647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.2587573
647 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.2639132280
Short name T810
Test name
Test status
Simulation time 26425586 ps
CPU time 0.93 seconds
Started Aug 16 06:04:43 PM PDT 24
Finished Aug 16 06:04:44 PM PDT 24
Peak memory 215908 kb
Host smart-210b560b-9e39-43ff-8f86-5232b85ae3a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639132280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.2639132
280 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.2804320678
Short name T809
Test name
Test status
Simulation time 46130018 ps
CPU time 1.73 seconds
Started Aug 16 06:04:50 PM PDT 24
Finished Aug 16 06:04:52 PM PDT 24
Peak memory 221232 kb
Host smart-cff20cc9-f0a6-41bb-93eb-39ef66f76d3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804320678 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.2804320678 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_rw.2407796416
Short name T788
Test name
Test status
Simulation time 70103311 ps
CPU time 0.92 seconds
Started Aug 16 06:04:44 PM PDT 24
Finished Aug 16 06:04:45 PM PDT 24
Peak memory 215644 kb
Host smart-a054d7e2-ace9-4f4a-8559-9e080e507771
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407796416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.2407796416 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_intr_test.1401381254
Short name T170
Test name
Test status
Simulation time 18631215 ps
CPU time 0.79 seconds
Started Aug 16 06:04:42 PM PDT 24
Finished Aug 16 06:04:43 PM PDT 24
Peak memory 215840 kb
Host smart-86f6b660-2c3f-40b5-80c6-016d9eefb72c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401381254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.1401381254 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.855927016
Short name T139
Test name
Test status
Simulation time 175928797 ps
CPU time 1.27 seconds
Started Aug 16 06:04:42 PM PDT 24
Finished Aug 16 06:04:43 PM PDT 24
Peak memory 216072 kb
Host smart-4ab08591-6639-4099-b495-1ac87d4f3cb9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855927016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial
_access.855927016 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_walk.2668702229
Short name T856
Test name
Test status
Simulation time 11688688 ps
CPU time 0.76 seconds
Started Aug 16 06:04:41 PM PDT 24
Finished Aug 16 06:04:42 PM PDT 24
Peak memory 215448 kb
Host smart-ae6b2913-b44f-4418-ae44-b53e1aaa5766
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668702229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.2668702229
+enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.1395557449
Short name T845
Test name
Test status
Simulation time 200028388 ps
CPU time 1.66 seconds
Started Aug 16 06:04:44 PM PDT 24
Finished Aug 16 06:04:46 PM PDT 24
Peak memory 216104 kb
Host smart-cecbe493-1654-4fb7-945b-83dc752c764e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395557449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr
_outstanding.1395557449 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.959132438
Short name T90
Test name
Test status
Simulation time 93566520 ps
CPU time 1.23 seconds
Started Aug 16 06:04:43 PM PDT 24
Finished Aug 16 06:04:44 PM PDT 24
Peak memory 216420 kb
Host smart-92cfa157-cc65-4ffb-83fb-f99988f742f5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959132438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_e
rrors.959132438 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.1387195838
Short name T818
Test name
Test status
Simulation time 733768622 ps
CPU time 3.24 seconds
Started Aug 16 06:04:42 PM PDT 24
Finished Aug 16 06:04:45 PM PDT 24
Peak memory 219984 kb
Host smart-0e887e0c-33c4-4255-ad93-b8c1a43e620d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387195838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac
_shadow_reg_errors_with_csr_rw.1387195838 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_errors.1307088685
Short name T860
Test name
Test status
Simulation time 35714078 ps
CPU time 1.99 seconds
Started Aug 16 06:04:40 PM PDT 24
Finished Aug 16 06:04:42 PM PDT 24
Peak memory 216280 kb
Host smart-50021563-ea13-4e41-a571-fd92308f93be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307088685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.1307088685 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.3945782326
Short name T812
Test name
Test status
Simulation time 379608051 ps
CPU time 4.28 seconds
Started Aug 16 06:04:45 PM PDT 24
Finished Aug 16 06:04:49 PM PDT 24
Peak memory 215948 kb
Host smart-b17c55f0-3adf-4c8b-9b2c-945430d35e39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945782326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.39457
82326 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.kmac_intr_test.2857744157
Short name T741
Test name
Test status
Simulation time 29936977 ps
CPU time 0.82 seconds
Started Aug 16 06:05:33 PM PDT 24
Finished Aug 16 06:05:33 PM PDT 24
Peak memory 215784 kb
Host smart-c1c03699-bf86-490b-b216-04b255fa01f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857744157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.2857744157 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.kmac_intr_test.2387455945
Short name T786
Test name
Test status
Simulation time 48739974 ps
CPU time 0.82 seconds
Started Aug 16 06:05:34 PM PDT 24
Finished Aug 16 06:05:35 PM PDT 24
Peak memory 215812 kb
Host smart-be518522-cbdf-4f81-bb5d-cfd54dd57e2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387455945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.2387455945 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.kmac_intr_test.1885155697
Short name T718
Test name
Test status
Simulation time 31272037 ps
CPU time 0.82 seconds
Started Aug 16 06:05:32 PM PDT 24
Finished Aug 16 06:05:33 PM PDT 24
Peak memory 215840 kb
Host smart-895de5c0-ac3b-427d-a434-d4ba1a166ad3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885155697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.1885155697 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.kmac_intr_test.1605629753
Short name T169
Test name
Test status
Simulation time 64817870 ps
CPU time 0.82 seconds
Started Aug 16 06:05:33 PM PDT 24
Finished Aug 16 06:05:34 PM PDT 24
Peak memory 215776 kb
Host smart-e0996105-4c1e-4706-819f-ce8914d621f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605629753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.1605629753 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.kmac_intr_test.1886723628
Short name T155
Test name
Test status
Simulation time 157814378 ps
CPU time 0.77 seconds
Started Aug 16 06:05:40 PM PDT 24
Finished Aug 16 06:05:41 PM PDT 24
Peak memory 215744 kb
Host smart-f3cc97e1-143e-434f-88eb-4102c140012b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886723628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.1886723628 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.kmac_intr_test.1654553100
Short name T852
Test name
Test status
Simulation time 21892067 ps
CPU time 0.79 seconds
Started Aug 16 06:05:35 PM PDT 24
Finished Aug 16 06:05:36 PM PDT 24
Peak memory 215832 kb
Host smart-0d7cec10-3aed-4eb1-b158-5b868bd46173
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654553100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.1654553100 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.kmac_intr_test.2994257074
Short name T753
Test name
Test status
Simulation time 54068018 ps
CPU time 0.8 seconds
Started Aug 16 06:05:33 PM PDT 24
Finished Aug 16 06:05:34 PM PDT 24
Peak memory 215748 kb
Host smart-6fbeae56-9543-41b9-a2a0-dec82a6b9e48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994257074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.2994257074 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.kmac_intr_test.3022965191
Short name T751
Test name
Test status
Simulation time 12961661 ps
CPU time 0.79 seconds
Started Aug 16 06:05:34 PM PDT 24
Finished Aug 16 06:05:35 PM PDT 24
Peak memory 215572 kb
Host smart-0036be3e-7cf0-4474-a318-07bcbe4f5989
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022965191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.3022965191 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.kmac_intr_test.3411858835
Short name T770
Test name
Test status
Simulation time 23695722 ps
CPU time 0.79 seconds
Started Aug 16 06:05:34 PM PDT 24
Finished Aug 16 06:05:34 PM PDT 24
Peak memory 215848 kb
Host smart-c23af8dd-1907-4793-8e1a-3c6bd3e25d84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411858835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.3411858835 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.kmac_intr_test.2752846591
Short name T726
Test name
Test status
Simulation time 66638494 ps
CPU time 0.85 seconds
Started Aug 16 06:05:32 PM PDT 24
Finished Aug 16 06:05:33 PM PDT 24
Peak memory 215780 kb
Host smart-fde188e8-8fbc-4840-9d7c-af06a9ae40e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752846591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.2752846591 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.3325418999
Short name T853
Test name
Test status
Simulation time 286884245 ps
CPU time 8.07 seconds
Started Aug 16 06:04:52 PM PDT 24
Finished Aug 16 06:05:00 PM PDT 24
Peak memory 215952 kb
Host smart-23b53138-1fd6-4a0b-b6fd-df25dfbb8085
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325418999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.3325418
999 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.22751573
Short name T717
Test name
Test status
Simulation time 1168697669 ps
CPU time 16.01 seconds
Started Aug 16 06:04:51 PM PDT 24
Finished Aug 16 06:05:08 PM PDT 24
Peak memory 216068 kb
Host smart-9c9e0bab-d701-4087-97c1-55059472f11e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22751573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.22751573
+enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.1862747552
Short name T825
Test name
Test status
Simulation time 23127475 ps
CPU time 0.95 seconds
Started Aug 16 06:04:49 PM PDT 24
Finished Aug 16 06:04:50 PM PDT 24
Peak memory 215892 kb
Host smart-fd40ddd5-f0af-4b83-abdb-c8c26425c1d6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862747552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.1862747
552 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.3920891673
Short name T160
Test name
Test status
Simulation time 77283075 ps
CPU time 2.4 seconds
Started Aug 16 06:04:47 PM PDT 24
Finished Aug 16 06:04:49 PM PDT 24
Peak memory 222816 kb
Host smart-d8624dbd-8b90-4a0e-8e07-3ff32c275550
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920891673 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.3920891673 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_rw.1886585061
Short name T748
Test name
Test status
Simulation time 22399607 ps
CPU time 0.96 seconds
Started Aug 16 06:04:48 PM PDT 24
Finished Aug 16 06:04:49 PM PDT 24
Peak memory 215816 kb
Host smart-ff957322-c6c7-41ba-9db5-fb18da6a28a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886585061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.1886585061 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_intr_test.3664371882
Short name T855
Test name
Test status
Simulation time 13686904 ps
CPU time 0.81 seconds
Started Aug 16 06:04:50 PM PDT 24
Finished Aug 16 06:04:51 PM PDT 24
Peak memory 215852 kb
Host smart-fd209bdb-c4b3-4a9d-be24-53080e636e53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664371882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.3664371882 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.503347955
Short name T142
Test name
Test status
Simulation time 505223496 ps
CPU time 1.55 seconds
Started Aug 16 06:04:47 PM PDT 24
Finished Aug 16 06:04:49 PM PDT 24
Peak memory 215944 kb
Host smart-f99498d7-aa3b-4fc9-918f-102fd54781a6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503347955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial
_access.503347955 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_walk.3464629970
Short name T762
Test name
Test status
Simulation time 35072485 ps
CPU time 0.77 seconds
Started Aug 16 06:04:52 PM PDT 24
Finished Aug 16 06:04:53 PM PDT 24
Peak memory 215640 kb
Host smart-941778b5-3d53-4df3-a236-d094ccbf4546
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464629970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.3464629970
+enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.1828648029
Short name T841
Test name
Test status
Simulation time 520510828 ps
CPU time 1.6 seconds
Started Aug 16 06:04:49 PM PDT 24
Finished Aug 16 06:04:51 PM PDT 24
Peak memory 216088 kb
Host smart-70081294-9086-4113-bbf1-d7132c378a06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828648029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr
_outstanding.1828648029 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.1868752589
Short name T87
Test name
Test status
Simulation time 702822840 ps
CPU time 2.41 seconds
Started Aug 16 06:04:51 PM PDT 24
Finished Aug 16 06:04:54 PM PDT 24
Peak memory 218224 kb
Host smart-fe569138-21f6-44b9-a217-a585e0058d19
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868752589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac
_shadow_reg_errors_with_csr_rw.1868752589 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_errors.4032954987
Short name T725
Test name
Test status
Simulation time 73033581 ps
CPU time 2.51 seconds
Started Aug 16 06:04:49 PM PDT 24
Finished Aug 16 06:04:52 PM PDT 24
Peak memory 216152 kb
Host smart-eb82f364-e0f0-4f77-b87c-3fb7008ffd88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032954987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.4032954987 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.104424777
Short name T190
Test name
Test status
Simulation time 208495829 ps
CPU time 4.1 seconds
Started Aug 16 06:04:49 PM PDT 24
Finished Aug 16 06:04:53 PM PDT 24
Peak memory 216124 kb
Host smart-c92ff023-7bc0-4f7d-8f97-d8020b64978e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104424777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.104424
777 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.kmac_intr_test.2163509210
Short name T723
Test name
Test status
Simulation time 26013847 ps
CPU time 0.76 seconds
Started Aug 16 06:05:32 PM PDT 24
Finished Aug 16 06:05:33 PM PDT 24
Peak memory 215772 kb
Host smart-aca787a1-b1d3-4227-b803-c8e78cd6e057
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163509210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.2163509210 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.kmac_intr_test.3204728768
Short name T167
Test name
Test status
Simulation time 21294234 ps
CPU time 0.82 seconds
Started Aug 16 06:05:34 PM PDT 24
Finished Aug 16 06:05:35 PM PDT 24
Peak memory 215788 kb
Host smart-309c1dd9-ab38-4b75-9f13-9d44ce45bb92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204728768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.3204728768 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.kmac_intr_test.1154517275
Short name T861
Test name
Test status
Simulation time 37872416 ps
CPU time 0.77 seconds
Started Aug 16 06:05:38 PM PDT 24
Finished Aug 16 06:05:39 PM PDT 24
Peak memory 215740 kb
Host smart-0f158b4c-4318-47d3-8006-a94c7f1e6ab4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154517275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.1154517275 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.kmac_intr_test.4210474802
Short name T761
Test name
Test status
Simulation time 11572517 ps
CPU time 0.8 seconds
Started Aug 16 06:05:40 PM PDT 24
Finished Aug 16 06:05:41 PM PDT 24
Peak memory 215760 kb
Host smart-d957a3d4-ce33-4a6e-ac1c-b0334515d60f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210474802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.4210474802 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.kmac_intr_test.4011130221
Short name T808
Test name
Test status
Simulation time 24608698 ps
CPU time 0.82 seconds
Started Aug 16 06:05:39 PM PDT 24
Finished Aug 16 06:05:40 PM PDT 24
Peak memory 215804 kb
Host smart-2952f2e4-7bc6-4081-bb86-f9033761e578
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011130221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.4011130221 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.kmac_intr_test.3393955228
Short name T859
Test name
Test status
Simulation time 191058684 ps
CPU time 0.74 seconds
Started Aug 16 06:05:40 PM PDT 24
Finished Aug 16 06:05:41 PM PDT 24
Peak memory 215756 kb
Host smart-85353159-1cfa-41b2-a12b-b4f50714742f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393955228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.3393955228 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.kmac_intr_test.977081938
Short name T166
Test name
Test status
Simulation time 24561118 ps
CPU time 0.83 seconds
Started Aug 16 06:05:43 PM PDT 24
Finished Aug 16 06:05:44 PM PDT 24
Peak memory 215732 kb
Host smart-cd045d7b-adc2-4119-8728-de41e40709d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977081938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.977081938 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/47.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.kmac_intr_test.2238853566
Short name T833
Test name
Test status
Simulation time 42088026 ps
CPU time 0.79 seconds
Started Aug 16 06:05:44 PM PDT 24
Finished Aug 16 06:05:45 PM PDT 24
Peak memory 215836 kb
Host smart-6182b323-1ab8-4fe2-a02f-33b6d7074062
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238853566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.2238853566 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.kmac_intr_test.3045300246
Short name T771
Test name
Test status
Simulation time 28083928 ps
CPU time 0.8 seconds
Started Aug 16 06:05:43 PM PDT 24
Finished Aug 16 06:05:44 PM PDT 24
Peak memory 215716 kb
Host smart-7deedac7-b100-448c-b3a8-247bb0a44205
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045300246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.3045300246 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.3743209111
Short name T750
Test name
Test status
Simulation time 24198419 ps
CPU time 1.45 seconds
Started Aug 16 06:04:59 PM PDT 24
Finished Aug 16 06:05:01 PM PDT 24
Peak memory 217140 kb
Host smart-9eda9397-20c7-4031-822a-08a4c4960fd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743209111 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.3743209111 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_rw.2901766830
Short name T720
Test name
Test status
Simulation time 51464861 ps
CPU time 1.15 seconds
Started Aug 16 06:04:59 PM PDT 24
Finished Aug 16 06:05:00 PM PDT 24
Peak memory 216080 kb
Host smart-53d95609-3280-4bfe-acac-dd73d28ccfed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901766830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.2901766830 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_intr_test.1783292609
Short name T863
Test name
Test status
Simulation time 45006105 ps
CPU time 0.8 seconds
Started Aug 16 06:04:58 PM PDT 24
Finished Aug 16 06:04:59 PM PDT 24
Peak memory 215728 kb
Host smart-d05ad96c-3c6e-481d-95e5-21d32f12a424
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783292609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.1783292609 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.3143833271
Short name T714
Test name
Test status
Simulation time 95481029 ps
CPU time 2.78 seconds
Started Aug 16 06:05:01 PM PDT 24
Finished Aug 16 06:05:04 PM PDT 24
Peak memory 216108 kb
Host smart-ae838a2f-9172-4984-8322-6fd809880299
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143833271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr
_outstanding.3143833271 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.2863155224
Short name T836
Test name
Test status
Simulation time 95996397 ps
CPU time 1.09 seconds
Started Aug 16 06:04:49 PM PDT 24
Finished Aug 16 06:04:51 PM PDT 24
Peak memory 216404 kb
Host smart-2c4dba18-8d39-455a-b28b-c4cc66db0ec8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863155224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_
errors.2863155224 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_errors.1729872911
Short name T850
Test name
Test status
Simulation time 318228072 ps
CPU time 2.33 seconds
Started Aug 16 06:04:51 PM PDT 24
Finished Aug 16 06:04:54 PM PDT 24
Peak memory 216208 kb
Host smart-f899f7d3-ef28-4c65-acec-68e07b36b39f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729872911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.1729872911 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.3385630548
Short name T811
Test name
Test status
Simulation time 567680819 ps
CPU time 3.16 seconds
Started Aug 16 06:04:57 PM PDT 24
Finished Aug 16 06:05:01 PM PDT 24
Peak memory 216148 kb
Host smart-a157a5ad-700a-44e5-b803-78d07165a443
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385630548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.33856
30548 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2453520754
Short name T801
Test name
Test status
Simulation time 25416697 ps
CPU time 1.88 seconds
Started Aug 16 06:05:01 PM PDT 24
Finished Aug 16 06:05:03 PM PDT 24
Peak memory 217096 kb
Host smart-1a6eccef-9025-4d38-b343-46c3ad888382
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453520754 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.2453520754 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_rw.1169908139
Short name T746
Test name
Test status
Simulation time 32232239 ps
CPU time 0.95 seconds
Started Aug 16 06:05:00 PM PDT 24
Finished Aug 16 06:05:01 PM PDT 24
Peak memory 215876 kb
Host smart-8d8eb7c4-b84b-47f3-854a-a9c3e6c86d7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169908139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.1169908139 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_intr_test.1361912670
Short name T865
Test name
Test status
Simulation time 15705567 ps
CPU time 0.85 seconds
Started Aug 16 06:05:01 PM PDT 24
Finished Aug 16 06:05:02 PM PDT 24
Peak memory 215864 kb
Host smart-c540856e-5f84-4adc-b72e-1fa29793f8f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361912670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.1361912670 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.2810607626
Short name T157
Test name
Test status
Simulation time 191111223 ps
CPU time 2.54 seconds
Started Aug 16 06:04:57 PM PDT 24
Finished Aug 16 06:05:00 PM PDT 24
Peak memory 216068 kb
Host smart-112d1f67-fde6-45c1-8120-0e180aa0b56e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810607626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr
_outstanding.2810607626 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.141731135
Short name T773
Test name
Test status
Simulation time 92332026 ps
CPU time 1.38 seconds
Started Aug 16 06:05:01 PM PDT 24
Finished Aug 16 06:05:02 PM PDT 24
Peak memory 216364 kb
Host smart-109f5e94-59c5-4751-a25f-686f3322024c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141731135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_e
rrors.141731135 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.2669804323
Short name T832
Test name
Test status
Simulation time 1403183914 ps
CPU time 3.18 seconds
Started Aug 16 06:04:59 PM PDT 24
Finished Aug 16 06:05:02 PM PDT 24
Peak memory 218968 kb
Host smart-75986409-7683-4f7c-b502-3bfd05eebc51
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669804323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac
_shadow_reg_errors_with_csr_rw.2669804323 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_errors.1545703603
Short name T791
Test name
Test status
Simulation time 216310306 ps
CPU time 3.02 seconds
Started Aug 16 06:04:58 PM PDT 24
Finished Aug 16 06:05:01 PM PDT 24
Peak memory 216220 kb
Host smart-d8db018d-d367-42d5-b444-379ea5606e7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545703603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.1545703603 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.1396927844
Short name T118
Test name
Test status
Simulation time 238845524 ps
CPU time 2.77 seconds
Started Aug 16 06:04:58 PM PDT 24
Finished Aug 16 06:05:01 PM PDT 24
Peak memory 216076 kb
Host smart-89acbe13-e10b-4db6-81ee-093a0e42cc76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396927844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.13969
27844 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.461124499
Short name T126
Test name
Test status
Simulation time 165200189 ps
CPU time 1.66 seconds
Started Aug 16 06:05:03 PM PDT 24
Finished Aug 16 06:05:04 PM PDT 24
Peak memory 219176 kb
Host smart-547505fb-756d-4a5f-9a50-9d2954ddbe47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461124499 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.461124499 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_rw.1180921846
Short name T813
Test name
Test status
Simulation time 61993678 ps
CPU time 0.94 seconds
Started Aug 16 06:05:03 PM PDT 24
Finished Aug 16 06:05:04 PM PDT 24
Peak memory 215684 kb
Host smart-51931d93-1124-4c35-84e7-e052141eb765
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180921846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.1180921846 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_intr_test.2483295514
Short name T744
Test name
Test status
Simulation time 52576196 ps
CPU time 0.78 seconds
Started Aug 16 06:04:57 PM PDT 24
Finished Aug 16 06:04:58 PM PDT 24
Peak memory 215860 kb
Host smart-b2401d42-9e14-4031-876c-cce486fa9b68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483295514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.2483295514 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.2452998229
Short name T763
Test name
Test status
Simulation time 226717651 ps
CPU time 1.42 seconds
Started Aug 16 06:05:00 PM PDT 24
Finished Aug 16 06:05:01 PM PDT 24
Peak memory 216084 kb
Host smart-749ec5aa-866f-4164-bc50-ff80c8793d84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452998229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr
_outstanding.2452998229 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.1915207955
Short name T86
Test name
Test status
Simulation time 102397706 ps
CPU time 1.18 seconds
Started Aug 16 06:05:00 PM PDT 24
Finished Aug 16 06:05:01 PM PDT 24
Peak memory 216492 kb
Host smart-25c77d32-4bb2-49ab-adc0-b60a55ba27fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915207955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_
errors.1915207955 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.1004590090
Short name T854
Test name
Test status
Simulation time 65060449 ps
CPU time 1.97 seconds
Started Aug 16 06:04:59 PM PDT 24
Finished Aug 16 06:05:01 PM PDT 24
Peak memory 216392 kb
Host smart-e710b726-2dea-45a5-91e8-fb820ec00e8f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004590090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac
_shadow_reg_errors_with_csr_rw.1004590090 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_errors.3370184393
Short name T864
Test name
Test status
Simulation time 142486327 ps
CPU time 2.42 seconds
Started Aug 16 06:04:59 PM PDT 24
Finished Aug 16 06:05:02 PM PDT 24
Peak memory 216136 kb
Host smart-07b280e9-233f-4ace-ae9b-1fca9f72234a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370184393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.3370184393 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.1306072596
Short name T177
Test name
Test status
Simulation time 733500838 ps
CPU time 5.1 seconds
Started Aug 16 06:05:00 PM PDT 24
Finished Aug 16 06:05:06 PM PDT 24
Peak memory 216064 kb
Host smart-c40c08d2-349e-4a47-8bea-9d3e4b8a0e9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306072596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.13060
72596 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2072888463
Short name T806
Test name
Test status
Simulation time 133450518 ps
CPU time 2.34 seconds
Started Aug 16 06:05:06 PM PDT 24
Finished Aug 16 06:05:08 PM PDT 24
Peak memory 221672 kb
Host smart-2c49908f-afb6-4070-8925-fa381d81d59e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072888463 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.2072888463 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_rw.4055666482
Short name T719
Test name
Test status
Simulation time 52935005 ps
CPU time 1.14 seconds
Started Aug 16 06:05:10 PM PDT 24
Finished Aug 16 06:05:11 PM PDT 24
Peak memory 216092 kb
Host smart-bfc390b5-177d-47ad-b08e-bb0a22f0fc83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055666482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.4055666482 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_intr_test.1228884798
Short name T731
Test name
Test status
Simulation time 42579760 ps
CPU time 0.85 seconds
Started Aug 16 06:05:10 PM PDT 24
Finished Aug 16 06:05:11 PM PDT 24
Peak memory 215704 kb
Host smart-4856b719-b7bf-45c9-8752-cce44723b047
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228884798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.1228884798 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.76799398
Short name T734
Test name
Test status
Simulation time 40648282 ps
CPU time 2.05 seconds
Started Aug 16 06:05:11 PM PDT 24
Finished Aug 16 06:05:13 PM PDT 24
Peak memory 216016 kb
Host smart-b6773055-2547-40d3-be30-c0ef681433af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76799398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_o
utstanding.76799398 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.2724393423
Short name T728
Test name
Test status
Simulation time 29977133 ps
CPU time 1.28 seconds
Started Aug 16 06:05:01 PM PDT 24
Finished Aug 16 06:05:03 PM PDT 24
Peak memory 216308 kb
Host smart-2206ef78-082b-4a7d-9d07-533c18f045b2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724393423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_
errors.2724393423 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.3709908665
Short name T738
Test name
Test status
Simulation time 123960009 ps
CPU time 1.74 seconds
Started Aug 16 06:05:00 PM PDT 24
Finished Aug 16 06:05:01 PM PDT 24
Peak memory 218348 kb
Host smart-e832c726-926d-457b-ae90-3eced3d85661
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709908665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac
_shadow_reg_errors_with_csr_rw.3709908665 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_errors.3831049086
Short name T780
Test name
Test status
Simulation time 1785644771 ps
CPU time 3.32 seconds
Started Aug 16 06:04:58 PM PDT 24
Finished Aug 16 06:05:01 PM PDT 24
Peak memory 216124 kb
Host smart-63234805-ab77-4236-a02d-f2713340c3e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831049086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.3831049086 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.3514968147
Short name T117
Test name
Test status
Simulation time 256716162 ps
CPU time 2.58 seconds
Started Aug 16 06:05:13 PM PDT 24
Finished Aug 16 06:05:16 PM PDT 24
Peak memory 216036 kb
Host smart-640ae82f-825d-4d71-bc2f-c56da5c0aeda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514968147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.35149
68147 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.1097617225
Short name T814
Test name
Test status
Simulation time 81327804 ps
CPU time 1.56 seconds
Started Aug 16 06:05:06 PM PDT 24
Finished Aug 16 06:05:08 PM PDT 24
Peak memory 217940 kb
Host smart-ba671851-3eeb-489e-a84e-11adc7f9f8ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097617225 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.1097617225 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_rw.672471855
Short name T743
Test name
Test status
Simulation time 80461949 ps
CPU time 1.16 seconds
Started Aug 16 06:05:07 PM PDT 24
Finished Aug 16 06:05:09 PM PDT 24
Peak memory 216228 kb
Host smart-ad756070-de4c-4c2f-a877-f623f1e44839
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672471855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.672471855 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/9.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_intr_test.293706026
Short name T775
Test name
Test status
Simulation time 15535821 ps
CPU time 0.82 seconds
Started Aug 16 06:05:12 PM PDT 24
Finished Aug 16 06:05:13 PM PDT 24
Peak memory 215640 kb
Host smart-f4d952de-c5ec-437c-98ba-eb59ad5cc09d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293706026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.293706026 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/9.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.1928891766
Short name T777
Test name
Test status
Simulation time 272352564 ps
CPU time 1.99 seconds
Started Aug 16 06:05:07 PM PDT 24
Finished Aug 16 06:05:09 PM PDT 24
Peak memory 216100 kb
Host smart-c94cde76-f090-41f3-b54d-14893a1173c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928891766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr
_outstanding.1928891766 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.3068156339
Short name T789
Test name
Test status
Simulation time 188357870 ps
CPU time 1.3 seconds
Started Aug 16 06:05:09 PM PDT 24
Finished Aug 16 06:05:11 PM PDT 24
Peak memory 216568 kb
Host smart-1b69321e-a0f2-4714-8a9a-fc638d947636
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068156339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_
errors.3068156339 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.1149014048
Short name T793
Test name
Test status
Simulation time 117584929 ps
CPU time 2.56 seconds
Started Aug 16 06:05:08 PM PDT 24
Finished Aug 16 06:05:11 PM PDT 24
Peak memory 219628 kb
Host smart-b1227f54-1065-415a-a485-deda34ea6bd7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149014048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac
_shadow_reg_errors_with_csr_rw.1149014048 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_errors.3181508792
Short name T790
Test name
Test status
Simulation time 121879801 ps
CPU time 1.98 seconds
Started Aug 16 06:05:07 PM PDT 24
Finished Aug 16 06:05:09 PM PDT 24
Peak memory 216180 kb
Host smart-a8a47da6-2734-40b4-b936-f74e9cbcf326
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181508792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.3181508792 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.3278924987
Short name T182
Test name
Test status
Simulation time 102283384 ps
CPU time 2.64 seconds
Started Aug 16 06:05:11 PM PDT 24
Finished Aug 16 06:05:14 PM PDT 24
Peak memory 216160 kb
Host smart-8b733656-d4e1-40aa-b4ea-d716174aeccb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278924987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.32789
24987 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.kmac_alert_test.121495093
Short name T132
Test name
Test status
Simulation time 20734574 ps
CPU time 0.83 seconds
Started Aug 16 06:05:46 PM PDT 24
Finished Aug 16 06:05:47 PM PDT 24
Peak memory 218248 kb
Host smart-d241c6a5-c6f0-4d75-8e89-5a51e94bb6a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121495093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.121495093 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/0.kmac_alert_test/latest

Test location /workspace/coverage/default/0.kmac_app.3461006874
Short name T642
Test name
Test status
Simulation time 24503196194 ps
CPU time 332.87 seconds
Started Aug 16 06:05:42 PM PDT 24
Finished Aug 16 06:11:15 PM PDT 24
Peak memory 317660 kb
Host smart-9d9e1e00-5c03-4254-9df7-863e9020ad66
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461006874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.3461006874 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/0.kmac_app/latest

Test location /workspace/coverage/default/0.kmac_app_with_partial_data.50262037
Short name T449
Test name
Test status
Simulation time 9361451400 ps
CPU time 212.44 seconds
Started Aug 16 06:05:40 PM PDT 24
Finished Aug 16 06:09:12 PM PDT 24
Peak memory 349688 kb
Host smart-5b80a077-6103-4bb7-9f32-5983e0ca2ed9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50262037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partia
l_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_parti
al_data.50262037 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/0.kmac_burst_write.1317555366
Short name T475
Test name
Test status
Simulation time 1677146032 ps
CPU time 44.56 seconds
Started Aug 16 06:05:43 PM PDT 24
Finished Aug 16 06:06:28 PM PDT 24
Peak memory 226184 kb
Host smart-112c0846-b4ef-45ec-b74a-95b813b94bca
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317555366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.1317555366
+enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_burst_write/latest

Test location /workspace/coverage/default/0.kmac_edn_timeout_error.727416566
Short name T336
Test name
Test status
Simulation time 3418704595 ps
CPU time 47.43 seconds
Started Aug 16 06:05:45 PM PDT 24
Finished Aug 16 06:06:32 PM PDT 24
Peak memory 227988 kb
Host smart-4edf4861-d4e9-46da-9017-2f913fdc4f48
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=727416566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.727416566 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_refresh.2706609942
Short name T624
Test name
Test status
Simulation time 18974174414 ps
CPU time 44.44 seconds
Started Aug 16 06:05:41 PM PDT 24
Finished Aug 16 06:06:26 PM PDT 24
Peak memory 245100 kb
Host smart-d97de4ab-11d7-4f7a-afdf-a6f2a50af1c3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706609942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.27
06609942 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/0.kmac_key_error.345092421
Short name T341
Test name
Test status
Simulation time 1691573292 ps
CPU time 7.82 seconds
Started Aug 16 06:05:42 PM PDT 24
Finished Aug 16 06:05:50 PM PDT 24
Peak memory 226480 kb
Host smart-ec2432ec-910a-4821-b1de-8f3a78eb9c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345092421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.345092421 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_key_error/latest

Test location /workspace/coverage/default/0.kmac_long_msg_and_output.3992439601
Short name T62
Test name
Test status
Simulation time 90707146164 ps
CPU time 2989.42 seconds
Started Aug 16 06:05:40 PM PDT 24
Finished Aug 16 06:55:30 PM PDT 24
Peak memory 1550540 kb
Host smart-0baac1fd-640b-458a-8a1a-221e696965a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992439601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an
d_output.3992439601 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/0.kmac_mubi.4085093290
Short name T555
Test name
Test status
Simulation time 51344362646 ps
CPU time 421.83 seconds
Started Aug 16 06:05:43 PM PDT 24
Finished Aug 16 06:12:46 PM PDT 24
Peak memory 517260 kb
Host smart-8d38e57f-fb21-4ded-9685-1bf6f86cca76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085093290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.4085093290 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mubi/latest

Test location /workspace/coverage/default/0.kmac_sec_cm.1949849878
Short name T34
Test name
Test status
Simulation time 4781295422 ps
CPU time 83.66 seconds
Started Aug 16 06:05:41 PM PDT 24
Finished Aug 16 06:07:04 PM PDT 24
Peak memory 273540 kb
Host smart-fe4292eb-dd42-4773-a5e9-e09c1f056776
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949849878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.1949849878 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/0.kmac_sec_cm/latest

Test location /workspace/coverage/default/0.kmac_sideload.1149411656
Short name T425
Test name
Test status
Simulation time 17489660140 ps
CPU time 579.09 seconds
Started Aug 16 06:05:43 PM PDT 24
Finished Aug 16 06:15:22 PM PDT 24
Peak memory 620864 kb
Host smart-3e453c91-bc8b-4467-96e8-a11520cf0482
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149411656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.1149411656 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_sideload/latest

Test location /workspace/coverage/default/0.kmac_smoke.3231327360
Short name T631
Test name
Test status
Simulation time 123817512 ps
CPU time 4.46 seconds
Started Aug 16 06:05:42 PM PDT 24
Finished Aug 16 06:05:46 PM PDT 24
Peak memory 223276 kb
Host smart-7f0752aa-4924-40f2-b4e7-7864099856ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231327360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.3231327360 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_smoke/latest

Test location /workspace/coverage/default/0.kmac_stress_all.4267122306
Short name T476
Test name
Test status
Simulation time 693716605311 ps
CPU time 2435.36 seconds
Started Aug 16 06:05:43 PM PDT 24
Finished Aug 16 06:46:19 PM PDT 24
Peak memory 1598536 kb
Host smart-d5d4b9f8-d0a5-491a-bd44-28d20571bd01
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4267122306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.4267122306 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all/latest

Test location /workspace/coverage/default/0.kmac_stress_all_with_rand_reset.1951393713
Short name T65
Test name
Test status
Simulation time 9747249747 ps
CPU time 64.95 seconds
Started Aug 16 06:05:46 PM PDT 24
Finished Aug 16 06:06:51 PM PDT 24
Peak memory 243324 kb
Host smart-0ebcc66a-b229-49a1-8741-da5eb11006c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1951393713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all_with_rand_reset.1951393713 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac.2786384004
Short name T697
Test name
Test status
Simulation time 82582351 ps
CPU time 3.35 seconds
Started Aug 16 06:05:40 PM PDT 24
Finished Aug 16 06:05:43 PM PDT 24
Peak memory 219664 kb
Host smart-f662e3e8-e869-4aef-8379-96c534874836
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786384004 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.kmac_test_vectors_kmac.2786384004 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac_xof.1941751267
Short name T211
Test name
Test status
Simulation time 201703919 ps
CPU time 3.11 seconds
Started Aug 16 06:05:43 PM PDT 24
Finished Aug 16 06:05:46 PM PDT 24
Peak memory 219704 kb
Host smart-7fa7c330-fdf1-49d8-8b1b-d45220f7f31c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941751267 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.kmac_test_vectors_kmac_xof.1941751267 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_224.3084486587
Short name T438
Test name
Test status
Simulation time 1278559030 ps
CPU time 40.79 seconds
Started Aug 16 06:05:41 PM PDT 24
Finished Aug 16 06:06:22 PM PDT 24
Peak memory 225716 kb
Host smart-2fa0471d-d98b-4036-9013-d875c45fafb8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3084486587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.3084486587 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_256.115669151
Short name T197
Test name
Test status
Simulation time 6787156976 ps
CPU time 42.05 seconds
Started Aug 16 06:05:41 PM PDT 24
Finished Aug 16 06:06:23 PM PDT 24
Peak memory 225320 kb
Host smart-2549e2e5-d713-4ae7-9b1d-505a93081053
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=115669151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.115669151 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_384.3500889799
Short name T264
Test name
Test status
Simulation time 109931010583 ps
CPU time 1590.7 seconds
Started Aug 16 06:05:42 PM PDT 24
Finished Aug 16 06:32:13 PM PDT 24
Peak memory 905376 kb
Host smart-80e260b2-9635-41c6-b100-2db8b7a3c123
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3500889799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.3500889799 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_512.1732105727
Short name T431
Test name
Test status
Simulation time 1296616012 ps
CPU time 19.46 seconds
Started Aug 16 06:05:43 PM PDT 24
Finished Aug 16 06:06:03 PM PDT 24
Peak memory 223640 kb
Host smart-da80bbaf-8318-4ed3-8d01-77dca495580a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1732105727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.1732105727 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_128.2808912925
Short name T674
Test name
Test status
Simulation time 98615885009 ps
CPU time 3603.51 seconds
Started Aug 16 06:05:43 PM PDT 24
Finished Aug 16 07:05:48 PM PDT 24
Peak memory 3705880 kb
Host smart-8f5125fc-b229-4b07-ad46-ad3c53c78acb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2808912925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.2808912925 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_256.3226316298
Short name T458
Test name
Test status
Simulation time 12626438510 ps
CPU time 130.31 seconds
Started Aug 16 06:05:42 PM PDT 24
Finished Aug 16 06:07:52 PM PDT 24
Peak memory 258700 kb
Host smart-582b2405-38c0-421d-baac-d69146580e17
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3226316298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.3226316298 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/1.kmac_app.1475188439
Short name T659
Test name
Test status
Simulation time 18841909308 ps
CPU time 424.78 seconds
Started Aug 16 06:05:53 PM PDT 24
Finished Aug 16 06:12:58 PM PDT 24
Peak memory 508348 kb
Host smart-1b1a3fc9-c16d-494b-af22-5e2089e056f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475188439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.1475188439 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/1.kmac_app/latest

Test location /workspace/coverage/default/1.kmac_app_with_partial_data.2961317388
Short name T296
Test name
Test status
Simulation time 33206356 ps
CPU time 1.1 seconds
Started Aug 16 06:05:51 PM PDT 24
Finished Aug 16 06:05:53 PM PDT 24
Peak memory 225644 kb
Host smart-605d43e9-49fc-4cf5-8a87-f117bbac4333
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961317388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_par
tial_data.2961317388 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/1.kmac_burst_write.3563382735
Short name T368
Test name
Test status
Simulation time 74230803430 ps
CPU time 1158.89 seconds
Started Aug 16 06:05:54 PM PDT 24
Finished Aug 16 06:25:13 PM PDT 24
Peak memory 243152 kb
Host smart-661fc843-6efb-4360-a143-d354cc496615
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563382735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.3563382735
+enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_burst_write/latest

Test location /workspace/coverage/default/1.kmac_edn_timeout_error.2222403322
Short name T662
Test name
Test status
Simulation time 525956385 ps
CPU time 9.22 seconds
Started Aug 16 06:05:51 PM PDT 24
Finished Aug 16 06:06:00 PM PDT 24
Peak memory 236904 kb
Host smart-ab1a2b46-0da2-4329-b946-2b62835fa5cd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2222403322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.2222403322 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_mode_error.1917063669
Short name T429
Test name
Test status
Simulation time 44434856 ps
CPU time 1.2 seconds
Started Aug 16 06:05:50 PM PDT 24
Finished Aug 16 06:05:51 PM PDT 24
Peak memory 218360 kb
Host smart-8390c764-4366-4c11-bf76-0e75bdb101f5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1917063669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.1917063669 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_ready_error.594172811
Short name T566
Test name
Test status
Simulation time 19980551162 ps
CPU time 56.75 seconds
Started Aug 16 06:05:51 PM PDT 24
Finished Aug 16 06:06:48 PM PDT 24
Peak memory 226804 kb
Host smart-812b67b1-e312-45ae-8c23-733a7eaa10b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594172811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.594172811 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_refresh.1340382110
Short name T251
Test name
Test status
Simulation time 5459067309 ps
CPU time 51.67 seconds
Started Aug 16 06:05:47 PM PDT 24
Finished Aug 16 06:06:39 PM PDT 24
Peak memory 259676 kb
Host smart-e88108e2-4f32-431d-953d-456b20bdf839
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340382110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.13
40382110 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/1.kmac_error.2580214722
Short name T210
Test name
Test status
Simulation time 2314304396 ps
CPU time 31.6 seconds
Started Aug 16 06:05:48 PM PDT 24
Finished Aug 16 06:06:20 PM PDT 24
Peak memory 254012 kb
Host smart-825fa937-05f2-45cd-be91-2a405cd26c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580214722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.2580214722 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_error/latest

Test location /workspace/coverage/default/1.kmac_lc_escalation.3523596422
Short name T552
Test name
Test status
Simulation time 122328697 ps
CPU time 1.39 seconds
Started Aug 16 06:05:52 PM PDT 24
Finished Aug 16 06:05:53 PM PDT 24
Peak memory 226600 kb
Host smart-543599c9-75dd-4ce1-a78b-f1f44324de53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523596422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.3523596422 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/1.kmac_lc_escalation/latest

Test location /workspace/coverage/default/1.kmac_sec_cm.3707512546
Short name T105
Test name
Test status
Simulation time 11754015003 ps
CPU time 85.78 seconds
Started Aug 16 06:05:52 PM PDT 24
Finished Aug 16 06:07:18 PM PDT 24
Peak memory 265768 kb
Host smart-f22dd88e-dbe0-4b06-beab-9ad575b221c4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707512546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.3707512546 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/1.kmac_sec_cm/latest

Test location /workspace/coverage/default/1.kmac_sideload.2425267213
Short name T405
Test name
Test status
Simulation time 5108962311 ps
CPU time 349.21 seconds
Started Aug 16 06:05:48 PM PDT 24
Finished Aug 16 06:11:37 PM PDT 24
Peak memory 343236 kb
Host smart-8827745a-8c9b-4a53-941a-ca3f295985de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425267213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.2425267213 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_sideload/latest

Test location /workspace/coverage/default/1.kmac_smoke.3219939456
Short name T204
Test name
Test status
Simulation time 3465666094 ps
CPU time 12.88 seconds
Started Aug 16 06:05:46 PM PDT 24
Finished Aug 16 06:05:59 PM PDT 24
Peak memory 222780 kb
Host smart-f8f12396-c6a6-4288-83f3-b93176a4ece5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219939456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.3219939456 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_smoke/latest

Test location /workspace/coverage/default/1.kmac_stress_all.1145982216
Short name T505
Test name
Test status
Simulation time 14065130271 ps
CPU time 606.45 seconds
Started Aug 16 06:05:53 PM PDT 24
Finished Aug 16 06:15:59 PM PDT 24
Peak memory 330860 kb
Host smart-760b8a7d-ecd4-4a90-80f7-b208532c051a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1145982216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.1145982216 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all/latest

Test location /workspace/coverage/default/1.kmac_stress_all_with_rand_reset.3931842742
Short name T66
Test name
Test status
Simulation time 2793681705 ps
CPU time 56.22 seconds
Started Aug 16 06:05:54 PM PDT 24
Finished Aug 16 06:06:50 PM PDT 24
Peak memory 258824 kb
Host smart-4f694862-b973-4759-a735-a8d5ac57bfcc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3931842742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all_with_rand_reset.3931842742 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac.2681143400
Short name T661
Test name
Test status
Simulation time 313943178 ps
CPU time 2.73 seconds
Started Aug 16 06:05:50 PM PDT 24
Finished Aug 16 06:05:53 PM PDT 24
Peak memory 219572 kb
Host smart-eb94dbe7-34bd-470b-bba8-c6bd1f28fc03
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681143400 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.kmac_test_vectors_kmac.2681143400 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac_xof.2602056656
Short name T337
Test name
Test status
Simulation time 46739338 ps
CPU time 2.83 seconds
Started Aug 16 06:05:53 PM PDT 24
Finished Aug 16 06:05:56 PM PDT 24
Peak memory 219580 kb
Host smart-6abdaf43-845e-417b-9cd2-d469d913458e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602056656 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.kmac_test_vectors_kmac_xof.2602056656 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_224.624808427
Short name T329
Test name
Test status
Simulation time 2609227665 ps
CPU time 47.35 seconds
Started Aug 16 06:05:50 PM PDT 24
Finished Aug 16 06:06:37 PM PDT 24
Peak memory 253392 kb
Host smart-e3c8ff86-5d4f-41ff-8d08-48db9cd52c52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=624808427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.624808427 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_256.1405870883
Short name T584
Test name
Test status
Simulation time 11188982909 ps
CPU time 45.84 seconds
Started Aug 16 06:05:55 PM PDT 24
Finished Aug 16 06:06:41 PM PDT 24
Peak memory 248408 kb
Host smart-0c15462d-d71b-42e5-95c5-59e7b9454f85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1405870883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.1405870883 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_384.750200597
Short name T516
Test name
Test status
Simulation time 44683882126 ps
CPU time 1995.14 seconds
Started Aug 16 06:05:51 PM PDT 24
Finished Aug 16 06:39:07 PM PDT 24
Peak memory 2344464 kb
Host smart-393540b9-0f5d-4a1f-8f0a-258ed0da6c73
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=750200597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.750200597 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_512.3736676631
Short name T498
Test name
Test status
Simulation time 63127480228 ps
CPU time 1725.5 seconds
Started Aug 16 06:05:51 PM PDT 24
Finished Aug 16 06:34:37 PM PDT 24
Peak memory 1721280 kb
Host smart-43543988-61f9-47a8-9800-3cb93b776c56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3736676631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.3736676631 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_128.1701897495
Short name T37
Test name
Test status
Simulation time 503904337272 ps
CPU time 3868.43 seconds
Started Aug 16 06:05:52 PM PDT 24
Finished Aug 16 07:10:21 PM PDT 24
Peak memory 3582428 kb
Host smart-3bbad631-5ad2-47ea-bbb9-57e7e4975afe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1701897495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.1701897495 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_256.1929761337
Short name T239
Test name
Test status
Simulation time 46081254684 ps
CPU time 438.37 seconds
Started Aug 16 06:05:54 PM PDT 24
Finished Aug 16 06:13:12 PM PDT 24
Peak memory 360548 kb
Host smart-0f3f2942-6241-4e74-8ddf-d78c48f9429e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1929761337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.1929761337 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/10.kmac_alert_test.2461211634
Short name T609
Test name
Test status
Simulation time 36492034 ps
CPU time 0.89 seconds
Started Aug 16 06:06:43 PM PDT 24
Finished Aug 16 06:06:43 PM PDT 24
Peak memory 218272 kb
Host smart-dedb8f1e-bcee-4ae9-9095-14db05c83ab4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461211634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.2461211634 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_alert_test/latest

Test location /workspace/coverage/default/10.kmac_burst_write.3927340636
Short name T134
Test name
Test status
Simulation time 20226322188 ps
CPU time 823.66 seconds
Started Aug 16 06:06:44 PM PDT 24
Finished Aug 16 06:20:28 PM PDT 24
Peak memory 252012 kb
Host smart-ff68d9b5-0a88-44ff-862b-5ac18a3c7f83
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927340636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.392734063
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_burst_write/latest

Test location /workspace/coverage/default/10.kmac_edn_timeout_error.516541499
Short name T443
Test name
Test status
Simulation time 25425381 ps
CPU time 1.17 seconds
Started Aug 16 06:06:43 PM PDT 24
Finished Aug 16 06:06:44 PM PDT 24
Peak memory 218348 kb
Host smart-dc90cfc6-5408-4a9d-a87a-b2f5b7d0f4c5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=516541499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.516541499 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_mode_error.183093669
Short name T268
Test name
Test status
Simulation time 115487234 ps
CPU time 1.12 seconds
Started Aug 16 06:06:44 PM PDT 24
Finished Aug 16 06:06:46 PM PDT 24
Peak memory 218376 kb
Host smart-7333dfd8-02e8-4529-935a-13e0609e5ff5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=183093669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.183093669 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_refresh.1404997802
Short name T415
Test name
Test status
Simulation time 27260037494 ps
CPU time 156.32 seconds
Started Aug 16 06:06:44 PM PDT 24
Finished Aug 16 06:09:20 PM PDT 24
Peak memory 333072 kb
Host smart-0e3601a3-ab8a-46a0-b971-a0cad3afd0e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404997802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.1
404997802 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/10.kmac_error.72889106
Short name T163
Test name
Test status
Simulation time 8840951778 ps
CPU time 405.7 seconds
Started Aug 16 06:06:43 PM PDT 24
Finished Aug 16 06:13:29 PM PDT 24
Peak memory 351800 kb
Host smart-65d30aea-8877-44b3-9300-2c91bd5a7b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72889106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.72889106 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_error/latest

Test location /workspace/coverage/default/10.kmac_key_error.4124354658
Short name T321
Test name
Test status
Simulation time 1057298119 ps
CPU time 7.96 seconds
Started Aug 16 06:06:43 PM PDT 24
Finished Aug 16 06:06:51 PM PDT 24
Peak memory 226588 kb
Host smart-5fd3b04f-fd90-4b42-a131-f5bec6cf5351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124354658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.4124354658 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_key_error/latest

Test location /workspace/coverage/default/10.kmac_lc_escalation.2118115169
Short name T389
Test name
Test status
Simulation time 34792777 ps
CPU time 1.23 seconds
Started Aug 16 06:06:45 PM PDT 24
Finished Aug 16 06:06:47 PM PDT 24
Peak memory 226476 kb
Host smart-3aa493e4-70fb-44cf-b88e-7098c950f93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118115169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.2118115169 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/10.kmac_lc_escalation/latest

Test location /workspace/coverage/default/10.kmac_long_msg_and_output.1878901512
Short name T398
Test name
Test status
Simulation time 106075361214 ps
CPU time 848.86 seconds
Started Aug 16 06:06:46 PM PDT 24
Finished Aug 16 06:20:55 PM PDT 24
Peak memory 1187608 kb
Host smart-b3d0676b-6f65-49e7-b783-90397b5bef14
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878901512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_a
nd_output.1878901512 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/10.kmac_sideload.2908952796
Short name T303
Test name
Test status
Simulation time 7673044803 ps
CPU time 169.51 seconds
Started Aug 16 06:06:43 PM PDT 24
Finished Aug 16 06:09:32 PM PDT 24
Peak memory 364088 kb
Host smart-72d7ddab-2be9-4b8d-a15f-b6b10665dbd9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908952796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.2908952796 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_sideload/latest

Test location /workspace/coverage/default/10.kmac_smoke.1259054892
Short name T681
Test name
Test status
Simulation time 13241600972 ps
CPU time 71.74 seconds
Started Aug 16 06:06:46 PM PDT 24
Finished Aug 16 06:07:57 PM PDT 24
Peak memory 227152 kb
Host smart-eaeea13e-291c-4d42-99a9-9eaac7c5e546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259054892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.1259054892 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_smoke/latest

Test location /workspace/coverage/default/10.kmac_stress_all.1398665198
Short name T688
Test name
Test status
Simulation time 32174149723 ps
CPU time 1653.17 seconds
Started Aug 16 06:06:42 PM PDT 24
Finished Aug 16 06:34:16 PM PDT 24
Peak memory 683144 kb
Host smart-8ef15a67-0c38-4bfc-ad00-1f964838f5cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1398665198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.1398665198 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_stress_all/latest

Test location /workspace/coverage/default/11.kmac_alert_test.1821333505
Short name T503
Test name
Test status
Simulation time 77004000 ps
CPU time 0.85 seconds
Started Aug 16 06:06:51 PM PDT 24
Finished Aug 16 06:06:51 PM PDT 24
Peak memory 218276 kb
Host smart-7bcc6f5e-f4e6-4018-b55e-5668f2bd9177
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821333505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.1821333505 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_alert_test/latest

Test location /workspace/coverage/default/11.kmac_app.2025983359
Short name T446
Test name
Test status
Simulation time 76915899112 ps
CPU time 392.1 seconds
Started Aug 16 06:06:50 PM PDT 24
Finished Aug 16 06:13:22 PM PDT 24
Peak memory 464208 kb
Host smart-02f29168-bc14-446f-acf6-70e9f4500199
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025983359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.2025983359 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/11.kmac_app/latest

Test location /workspace/coverage/default/11.kmac_burst_write.2782685565
Short name T445
Test name
Test status
Simulation time 1242920102 ps
CPU time 119.91 seconds
Started Aug 16 06:06:55 PM PDT 24
Finished Aug 16 06:08:55 PM PDT 24
Peak memory 234756 kb
Host smart-726ba083-6c6d-4f1b-ae3e-d65e0ec28fde
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782685565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.278268556
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_burst_write/latest

Test location /workspace/coverage/default/11.kmac_edn_timeout_error.2073308966
Short name T467
Test name
Test status
Simulation time 1630866962 ps
CPU time 40.14 seconds
Started Aug 16 06:06:52 PM PDT 24
Finished Aug 16 06:07:32 PM PDT 24
Peak memory 227160 kb
Host smart-891ff551-30b7-40f6-af4e-d294bab176e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2073308966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.2073308966 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_mode_error.2765978930
Short name T78
Test name
Test status
Simulation time 73472640 ps
CPU time 1.15 seconds
Started Aug 16 06:06:53 PM PDT 24
Finished Aug 16 06:06:54 PM PDT 24
Peak memory 222292 kb
Host smart-f5a7cfd1-fec0-44a0-8341-946fb7c3bbe8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2765978930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.2765978930 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_refresh.224687959
Short name T646
Test name
Test status
Simulation time 6613829538 ps
CPU time 169.6 seconds
Started Aug 16 06:06:52 PM PDT 24
Finished Aug 16 06:09:42 PM PDT 24
Peak memory 273336 kb
Host smart-b92551e6-21aa-40e1-9a54-5f47b120ea84
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224687959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.22
4687959 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/11.kmac_error.3080171680
Short name T703
Test name
Test status
Simulation time 5499318845 ps
CPU time 501.9 seconds
Started Aug 16 06:06:50 PM PDT 24
Finished Aug 16 06:15:12 PM PDT 24
Peak memory 387816 kb
Host smart-605edc3b-35ea-4767-b815-498c494dacb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080171680 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.3080171680 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_error/latest

Test location /workspace/coverage/default/11.kmac_key_error.1049336585
Short name T602
Test name
Test status
Simulation time 1753345307 ps
CPU time 11.94 seconds
Started Aug 16 06:06:52 PM PDT 24
Finished Aug 16 06:07:04 PM PDT 24
Peak memory 226536 kb
Host smart-9f24520e-637d-48f0-8859-6602f0d4d96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049336585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.1049336585 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_key_error/latest

Test location /workspace/coverage/default/11.kmac_lc_escalation.3276114075
Short name T30
Test name
Test status
Simulation time 33903380 ps
CPU time 1.43 seconds
Started Aug 16 06:06:53 PM PDT 24
Finished Aug 16 06:06:55 PM PDT 24
Peak memory 226520 kb
Host smart-2ae14123-c442-43b9-9018-af3fedf53dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276114075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.3276114075 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/11.kmac_lc_escalation/latest

Test location /workspace/coverage/default/11.kmac_long_msg_and_output.141805698
Short name T520
Test name
Test status
Simulation time 28534513882 ps
CPU time 4335.05 seconds
Started Aug 16 06:06:42 PM PDT 24
Finished Aug 16 07:18:58 PM PDT 24
Peak memory 1911272 kb
Host smart-f146a953-be19-49c4-9a53-de3ce16bf35e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141805698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_an
d_output.141805698 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/11.kmac_sideload.2631915375
Short name T235
Test name
Test status
Simulation time 4830380628 ps
CPU time 96.12 seconds
Started Aug 16 06:06:52 PM PDT 24
Finished Aug 16 06:08:28 PM PDT 24
Peak memory 253804 kb
Host smart-38c85b38-ff3d-4b31-92ed-0619c3c7c134
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631915375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.2631915375 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_sideload/latest

Test location /workspace/coverage/default/11.kmac_smoke.920598477
Short name T297
Test name
Test status
Simulation time 1995905159 ps
CPU time 18.89 seconds
Started Aug 16 06:06:43 PM PDT 24
Finished Aug 16 06:07:02 PM PDT 24
Peak memory 226572 kb
Host smart-d2b17fd2-75c6-405d-b2e3-e1b4e90ebed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920598477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.920598477 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_smoke/latest

Test location /workspace/coverage/default/11.kmac_stress_all.1951303527
Short name T55
Test name
Test status
Simulation time 741708529 ps
CPU time 21.46 seconds
Started Aug 16 06:06:55 PM PDT 24
Finished Aug 16 06:07:16 PM PDT 24
Peak memory 243372 kb
Host smart-378ceb04-cfe7-455e-b392-015363187bf9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1951303527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.1951303527 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_stress_all/latest

Test location /workspace/coverage/default/12.kmac_alert_test.753852927
Short name T534
Test name
Test status
Simulation time 35380999 ps
CPU time 0.81 seconds
Started Aug 16 06:07:06 PM PDT 24
Finished Aug 16 06:07:07 PM PDT 24
Peak memory 218248 kb
Host smart-a817c5b7-89ee-41a6-956f-93d5b6e03e64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753852927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.753852927 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/12.kmac_alert_test/latest

Test location /workspace/coverage/default/12.kmac_app.3329087993
Short name T457
Test name
Test status
Simulation time 48894770307 ps
CPU time 308.96 seconds
Started Aug 16 06:06:53 PM PDT 24
Finished Aug 16 06:12:02 PM PDT 24
Peak memory 445184 kb
Host smart-3c654ddd-df9b-47f1-b94b-0b3e01fac6c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329087993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.3329087993 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/12.kmac_app/latest

Test location /workspace/coverage/default/12.kmac_burst_write.2776836033
Short name T483
Test name
Test status
Simulation time 6465459597 ps
CPU time 699.82 seconds
Started Aug 16 06:06:52 PM PDT 24
Finished Aug 16 06:18:32 PM PDT 24
Peak memory 243164 kb
Host smart-dd2ab864-049a-44cf-bd6b-4ee93ba677c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776836033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.277683603
3 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_burst_write/latest

Test location /workspace/coverage/default/12.kmac_edn_timeout_error.660001705
Short name T217
Test name
Test status
Simulation time 1081792174 ps
CPU time 19.93 seconds
Started Aug 16 06:06:51 PM PDT 24
Finished Aug 16 06:07:11 PM PDT 24
Peak memory 231272 kb
Host smart-41e7bf3f-f73d-4fba-ae38-3a7e907be6ab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=660001705 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.660001705 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_mode_error.2988833896
Short name T287
Test name
Test status
Simulation time 25641425 ps
CPU time 1.11 seconds
Started Aug 16 06:07:12 PM PDT 24
Finished Aug 16 06:07:13 PM PDT 24
Peak memory 218300 kb
Host smart-fbd7e88b-248a-4bb5-b70f-98c60a622681
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2988833896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.2988833896 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_refresh.2269182718
Short name T269
Test name
Test status
Simulation time 8225742876 ps
CPU time 119.65 seconds
Started Aug 16 06:06:51 PM PDT 24
Finished Aug 16 06:08:50 PM PDT 24
Peak memory 263612 kb
Host smart-78f1ea5b-6bde-4d56-b327-d5cb210488bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269182718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.2
269182718 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/12.kmac_error.3027166935
Short name T595
Test name
Test status
Simulation time 5059896693 ps
CPU time 445.03 seconds
Started Aug 16 06:06:51 PM PDT 24
Finished Aug 16 06:14:16 PM PDT 24
Peak memory 381032 kb
Host smart-b46ec5af-102c-432d-ba42-7bfc860791c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027166935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.3027166935 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_error/latest

Test location /workspace/coverage/default/12.kmac_key_error.2945798990
Short name T506
Test name
Test status
Simulation time 982413840 ps
CPU time 8.3 seconds
Started Aug 16 06:06:53 PM PDT 24
Finished Aug 16 06:07:01 PM PDT 24
Peak memory 226564 kb
Host smart-9b4eadea-b697-4d32-8228-56836afd0464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945798990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.2945798990 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_key_error/latest

Test location /workspace/coverage/default/12.kmac_long_msg_and_output.533559216
Short name T194
Test name
Test status
Simulation time 61992298808 ps
CPU time 3603.29 seconds
Started Aug 16 06:06:53 PM PDT 24
Finished Aug 16 07:06:57 PM PDT 24
Peak memory 2996120 kb
Host smart-8b0191cc-2a54-4982-a1eb-b61fcc45c717
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533559216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_an
d_output.533559216 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/12.kmac_sideload.807509067
Short name T310
Test name
Test status
Simulation time 15650756362 ps
CPU time 341.35 seconds
Started Aug 16 06:06:58 PM PDT 24
Finished Aug 16 06:12:39 PM PDT 24
Peak memory 335148 kb
Host smart-42c9999a-b982-41dc-8faa-3e36a887d3b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807509067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.807509067 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_sideload/latest

Test location /workspace/coverage/default/12.kmac_smoke.2341868102
Short name T546
Test name
Test status
Simulation time 12861815790 ps
CPU time 68.17 seconds
Started Aug 16 06:06:49 PM PDT 24
Finished Aug 16 06:07:58 PM PDT 24
Peak memory 227392 kb
Host smart-a52ab830-ab06-455c-b58a-92fdbf593871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341868102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.2341868102 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_smoke/latest

Test location /workspace/coverage/default/12.kmac_stress_all.3592433680
Short name T406
Test name
Test status
Simulation time 21877209063 ps
CPU time 1939.72 seconds
Started Aug 16 06:07:00 PM PDT 24
Finished Aug 16 06:39:20 PM PDT 24
Peak memory 553652 kb
Host smart-f3cef686-fc21-45d8-aee9-63c48b354269
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3592433680 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.3592433680 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_stress_all/latest

Test location /workspace/coverage/default/13.kmac_alert_test.3240690410
Short name T355
Test name
Test status
Simulation time 24013733 ps
CPU time 0.78 seconds
Started Aug 16 06:07:02 PM PDT 24
Finished Aug 16 06:07:03 PM PDT 24
Peak memory 218244 kb
Host smart-d1a5a92a-14ef-4888-bc91-e81af275dda0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240690410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.3240690410 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_alert_test/latest

Test location /workspace/coverage/default/13.kmac_burst_write.2529810430
Short name T537
Test name
Test status
Simulation time 5000237504 ps
CPU time 277.11 seconds
Started Aug 16 06:06:59 PM PDT 24
Finished Aug 16 06:11:36 PM PDT 24
Peak memory 234948 kb
Host smart-f1f8602f-8701-49df-9c68-2070c5c1b453
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529810430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.252981043
0 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_burst_write/latest

Test location /workspace/coverage/default/13.kmac_edn_timeout_error.4102008369
Short name T403
Test name
Test status
Simulation time 1461813472 ps
CPU time 38.25 seconds
Started Aug 16 06:07:03 PM PDT 24
Finished Aug 16 06:07:41 PM PDT 24
Peak memory 234492 kb
Host smart-99a4d4e0-4c1a-44c5-ac2b-a542a73ef0ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4102008369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.4102008369 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_mode_error.1122953253
Short name T591
Test name
Test status
Simulation time 671974341 ps
CPU time 1.51 seconds
Started Aug 16 06:07:01 PM PDT 24
Finished Aug 16 06:07:03 PM PDT 24
Peak memory 222280 kb
Host smart-4d7cd714-313b-4530-96ee-f7f82f5704a5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1122953253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.1122953253 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_refresh.1638510508
Short name T265
Test name
Test status
Simulation time 27352895724 ps
CPU time 140.67 seconds
Started Aug 16 06:07:00 PM PDT 24
Finished Aug 16 06:09:21 PM PDT 24
Peak memory 319804 kb
Host smart-be0c6caf-952a-4335-afc2-1fe34793fe0d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638510508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.1
638510508 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/13.kmac_error.2072056162
Short name T370
Test name
Test status
Simulation time 24378531024 ps
CPU time 391.8 seconds
Started Aug 16 06:07:10 PM PDT 24
Finished Aug 16 06:13:42 PM PDT 24
Peak memory 502200 kb
Host smart-7e199fcd-d856-441a-b68d-10f0cade5275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072056162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.2072056162 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_error/latest

Test location /workspace/coverage/default/13.kmac_key_error.3783756954
Short name T447
Test name
Test status
Simulation time 541263313 ps
CPU time 4.76 seconds
Started Aug 16 06:07:03 PM PDT 24
Finished Aug 16 06:07:08 PM PDT 24
Peak memory 226592 kb
Host smart-62192db3-4e65-4bdd-ae00-8c7da569b325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783756954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.3783756954 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_key_error/latest

Test location /workspace/coverage/default/13.kmac_long_msg_and_output.988986539
Short name T582
Test name
Test status
Simulation time 40587526010 ps
CPU time 2738.18 seconds
Started Aug 16 06:07:00 PM PDT 24
Finished Aug 16 06:52:39 PM PDT 24
Peak memory 1351012 kb
Host smart-5881e83a-ccf9-4606-bf48-af3fcc565680
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988986539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_an
d_output.988986539 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/13.kmac_sideload.3356759023
Short name T698
Test name
Test status
Simulation time 98854532641 ps
CPU time 645.52 seconds
Started Aug 16 06:07:10 PM PDT 24
Finished Aug 16 06:17:56 PM PDT 24
Peak memory 682036 kb
Host smart-2634bcf5-ba25-4195-bff8-650d5a4699fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356759023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.3356759023 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_sideload/latest

Test location /workspace/coverage/default/13.kmac_smoke.851707849
Short name T559
Test name
Test status
Simulation time 454809598 ps
CPU time 4.14 seconds
Started Aug 16 06:07:12 PM PDT 24
Finished Aug 16 06:07:16 PM PDT 24
Peak memory 226648 kb
Host smart-77cb1e34-1ac8-451b-8af2-0ff20d738844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851707849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.851707849 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_smoke/latest

Test location /workspace/coverage/default/13.kmac_stress_all.1644511590
Short name T59
Test name
Test status
Simulation time 1559810711098 ps
CPU time 3928.63 seconds
Started Aug 16 06:07:00 PM PDT 24
Finished Aug 16 07:12:30 PM PDT 24
Peak memory 2255184 kb
Host smart-3d91ed56-71e6-448f-8d95-92a3b1b5a07e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1644511590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.1644511590 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all/latest

Test location /workspace/coverage/default/14.kmac_alert_test.2766354801
Short name T419
Test name
Test status
Simulation time 13799501 ps
CPU time 0.84 seconds
Started Aug 16 06:07:09 PM PDT 24
Finished Aug 16 06:07:10 PM PDT 24
Peak memory 218240 kb
Host smart-c7cf7c54-42fb-4fdf-b499-f19aa5082501
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766354801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.2766354801 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_alert_test/latest

Test location /workspace/coverage/default/14.kmac_app.950417941
Short name T658
Test name
Test status
Simulation time 9076916898 ps
CPU time 135.18 seconds
Started Aug 16 06:07:09 PM PDT 24
Finished Aug 16 06:09:25 PM PDT 24
Peak memory 305544 kb
Host smart-0366262c-12c4-4b72-8fd0-4bff946bf245
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950417941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.950417941 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/14.kmac_app/latest

Test location /workspace/coverage/default/14.kmac_burst_write.4046964913
Short name T364
Test name
Test status
Simulation time 43286695619 ps
CPU time 576.42 seconds
Started Aug 16 06:07:06 PM PDT 24
Finished Aug 16 06:16:42 PM PDT 24
Peak memory 244572 kb
Host smart-941c257a-62be-49f1-96f3-61a43bb1f19f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046964913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.404696491
3 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_burst_write/latest

Test location /workspace/coverage/default/14.kmac_edn_timeout_error.700583021
Short name T76
Test name
Test status
Simulation time 16767842 ps
CPU time 0.95 seconds
Started Aug 16 06:07:09 PM PDT 24
Finished Aug 16 06:07:10 PM PDT 24
Peak memory 218168 kb
Host smart-9a7d851e-089f-4712-8dc8-d9e28d5139fb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=700583021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.700583021 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_mode_error.3927112815
Short name T580
Test name
Test status
Simulation time 86225530 ps
CPU time 0.94 seconds
Started Aug 16 06:07:29 PM PDT 24
Finished Aug 16 06:07:30 PM PDT 24
Peak memory 220592 kb
Host smart-5ca220eb-7c9d-4db7-beee-f3b8bae58807
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3927112815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.3927112815 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_refresh.3209976875
Short name T213
Test name
Test status
Simulation time 11292163084 ps
CPU time 53.2 seconds
Started Aug 16 06:06:59 PM PDT 24
Finished Aug 16 06:07:52 PM PDT 24
Peak memory 254388 kb
Host smart-0f6a72eb-9171-45c6-a4ec-1283c1583787
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209976875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.3
209976875 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/14.kmac_error.98647976
Short name T472
Test name
Test status
Simulation time 39964168415 ps
CPU time 360.41 seconds
Started Aug 16 06:07:18 PM PDT 24
Finished Aug 16 06:13:19 PM PDT 24
Peak memory 521132 kb
Host smart-c36d0093-d7fe-4a64-aefe-4f6ea5764979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98647976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.98647976 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_error/latest

Test location /workspace/coverage/default/14.kmac_key_error.1655350978
Short name T600
Test name
Test status
Simulation time 6677572410 ps
CPU time 12.62 seconds
Started Aug 16 06:07:11 PM PDT 24
Finished Aug 16 06:07:23 PM PDT 24
Peak memory 226644 kb
Host smart-336ce4d9-d0fe-4d8d-87ac-4db7e877f736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655350978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.1655350978 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_key_error/latest

Test location /workspace/coverage/default/14.kmac_lc_escalation.2054914630
Short name T188
Test name
Test status
Simulation time 58139167 ps
CPU time 1.24 seconds
Started Aug 16 06:07:28 PM PDT 24
Finished Aug 16 06:07:29 PM PDT 24
Peak memory 226616 kb
Host smart-5a28594e-6dc1-4840-90ff-f3e2da57ddb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054914630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.2054914630 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/14.kmac_lc_escalation/latest

Test location /workspace/coverage/default/14.kmac_long_msg_and_output.4254917432
Short name T206
Test name
Test status
Simulation time 15209421665 ps
CPU time 1861.79 seconds
Started Aug 16 06:07:10 PM PDT 24
Finished Aug 16 06:38:13 PM PDT 24
Peak memory 1096228 kb
Host smart-5b74b3e0-7dd3-4919-a399-a8e069f897e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254917432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_a
nd_output.4254917432 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/14.kmac_sideload.1221575905
Short name T527
Test name
Test status
Simulation time 14979425539 ps
CPU time 584.55 seconds
Started Aug 16 06:07:11 PM PDT 24
Finished Aug 16 06:16:56 PM PDT 24
Peak memory 614008 kb
Host smart-a56d834b-30b4-4864-8c3d-d3fe5ed495b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221575905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.1221575905 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_sideload/latest

Test location /workspace/coverage/default/14.kmac_smoke.278400643
Short name T304
Test name
Test status
Simulation time 2038714610 ps
CPU time 43.36 seconds
Started Aug 16 06:07:11 PM PDT 24
Finished Aug 16 06:07:55 PM PDT 24
Peak memory 222608 kb
Host smart-4fc2b846-0a18-49a6-be76-b739d5ce9780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278400643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.278400643 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_smoke/latest

Test location /workspace/coverage/default/14.kmac_stress_all.1755885835
Short name T558
Test name
Test status
Simulation time 14432942454 ps
CPU time 1340.92 seconds
Started Aug 16 06:07:08 PM PDT 24
Finished Aug 16 06:29:30 PM PDT 24
Peak memory 629340 kb
Host smart-5ded5511-97d9-4e76-a253-0fcac052e4d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1755885835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.1755885835 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all/latest

Test location /workspace/coverage/default/15.kmac_alert_test.3994646450
Short name T250
Test name
Test status
Simulation time 47701887 ps
CPU time 0.83 seconds
Started Aug 16 06:07:25 PM PDT 24
Finished Aug 16 06:07:26 PM PDT 24
Peak memory 218308 kb
Host smart-f8aa6827-b9f3-43f2-8c80-7f16ab95da07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994646450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.3994646450 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_alert_test/latest

Test location /workspace/coverage/default/15.kmac_entropy_mode_error.104067775
Short name T418
Test name
Test status
Simulation time 61678270 ps
CPU time 1.11 seconds
Started Aug 16 06:07:18 PM PDT 24
Finished Aug 16 06:07:20 PM PDT 24
Peak memory 222100 kb
Host smart-59f17bb9-a3c4-43d0-acda-e5466dc68e0a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=104067775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.104067775 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_refresh.2586045826
Short name T639
Test name
Test status
Simulation time 15448163774 ps
CPU time 177.79 seconds
Started Aug 16 06:07:26 PM PDT 24
Finished Aug 16 06:10:24 PM PDT 24
Peak memory 353540 kb
Host smart-98b9818d-111e-4802-a841-14573134cbc1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586045826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.2
586045826 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/15.kmac_error.2233666364
Short name T380
Test name
Test status
Simulation time 4737222659 ps
CPU time 185.93 seconds
Started Aug 16 06:07:08 PM PDT 24
Finished Aug 16 06:10:14 PM PDT 24
Peak memory 292244 kb
Host smart-d64f3e7d-bc65-46bc-839b-e70ee1389a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233666364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.2233666364 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_error/latest

Test location /workspace/coverage/default/15.kmac_key_error.3604658384
Short name T474
Test name
Test status
Simulation time 1909113246 ps
CPU time 12.69 seconds
Started Aug 16 06:07:19 PM PDT 24
Finished Aug 16 06:07:32 PM PDT 24
Peak memory 226596 kb
Host smart-dd8e29bc-1e54-4efe-b6c6-9206b8ca97f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604658384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.3604658384 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_key_error/latest

Test location /workspace/coverage/default/15.kmac_lc_escalation.1857812757
Short name T28
Test name
Test status
Simulation time 71896701 ps
CPU time 1.56 seconds
Started Aug 16 06:07:33 PM PDT 24
Finished Aug 16 06:07:35 PM PDT 24
Peak memory 226664 kb
Host smart-fe27b61e-31fb-45ee-936a-a5f983010d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857812757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.1857812757 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/15.kmac_lc_escalation/latest

Test location /workspace/coverage/default/15.kmac_sideload.1050771257
Short name T440
Test name
Test status
Simulation time 3042497079 ps
CPU time 67.7 seconds
Started Aug 16 06:07:19 PM PDT 24
Finished Aug 16 06:08:27 PM PDT 24
Peak memory 283792 kb
Host smart-2eb62b99-f8b6-48be-be4b-439e490c1e3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050771257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.1050771257 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_sideload/latest

Test location /workspace/coverage/default/15.kmac_smoke.1587365028
Short name T420
Test name
Test status
Simulation time 3206846503 ps
CPU time 26.73 seconds
Started Aug 16 06:07:10 PM PDT 24
Finished Aug 16 06:07:37 PM PDT 24
Peak memory 226680 kb
Host smart-6f57ba65-5ff2-4692-bc5b-a9aeefac5b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587365028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.1587365028 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_smoke/latest

Test location /workspace/coverage/default/15.kmac_stress_all.3649973240
Short name T290
Test name
Test status
Simulation time 110158248848 ps
CPU time 1232.34 seconds
Started Aug 16 06:07:34 PM PDT 24
Finished Aug 16 06:28:06 PM PDT 24
Peak memory 837524 kb
Host smart-a69fb5c5-e620-49d3-be0a-9f122aff9817
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3649973240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.3649973240 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_stress_all/latest

Test location /workspace/coverage/default/16.kmac_alert_test.2278436065
Short name T691
Test name
Test status
Simulation time 137710408 ps
CPU time 0.91 seconds
Started Aug 16 06:07:21 PM PDT 24
Finished Aug 16 06:07:22 PM PDT 24
Peak memory 218232 kb
Host smart-23060754-eadc-452f-ae6f-f861cbf515cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278436065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.2278436065 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_alert_test/latest

Test location /workspace/coverage/default/16.kmac_app.3349702619
Short name T663
Test name
Test status
Simulation time 9318626984 ps
CPU time 318.04 seconds
Started Aug 16 06:07:18 PM PDT 24
Finished Aug 16 06:12:36 PM PDT 24
Peak memory 455908 kb
Host smart-0beb1b29-2222-4dae-8dcf-eda4b630016b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349702619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.3349702619 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/16.kmac_app/latest

Test location /workspace/coverage/default/16.kmac_burst_write.2295750432
Short name T421
Test name
Test status
Simulation time 40976214960 ps
CPU time 1178.34 seconds
Started Aug 16 06:07:36 PM PDT 24
Finished Aug 16 06:27:14 PM PDT 24
Peak memory 244244 kb
Host smart-aca72b81-238b-42d4-bce3-a5451268dee7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295750432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.229575043
2 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_burst_write/latest

Test location /workspace/coverage/default/16.kmac_edn_timeout_error.3813658990
Short name T255
Test name
Test status
Simulation time 638004130 ps
CPU time 4.02 seconds
Started Aug 16 06:07:18 PM PDT 24
Finished Aug 16 06:07:22 PM PDT 24
Peak memory 218444 kb
Host smart-6819a9dd-e8de-4704-acf0-9ba33bcd041e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3813658990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.3813658990 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_mode_error.3215982733
Short name T71
Test name
Test status
Simulation time 31869417 ps
CPU time 0.83 seconds
Started Aug 16 06:07:18 PM PDT 24
Finished Aug 16 06:07:19 PM PDT 24
Peak memory 218192 kb
Host smart-bc3986d8-b5e5-4dbe-9b8a-6145cad0f115
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3215982733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.3215982733 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_refresh.1587544805
Short name T701
Test name
Test status
Simulation time 10250502659 ps
CPU time 152.2 seconds
Started Aug 16 06:07:17 PM PDT 24
Finished Aug 16 06:09:49 PM PDT 24
Peak memory 329860 kb
Host smart-b18dec1d-8b6c-4d6a-bd4d-328e34868ad3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587544805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.1
587544805 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/16.kmac_error.432654297
Short name T175
Test name
Test status
Simulation time 17020121143 ps
CPU time 517.61 seconds
Started Aug 16 06:07:19 PM PDT 24
Finished Aug 16 06:15:57 PM PDT 24
Peak memory 610052 kb
Host smart-f3520f8b-fb79-418a-9431-36e523b3cad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432654297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.432654297 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_error/latest

Test location /workspace/coverage/default/16.kmac_key_error.2873403978
Short name T577
Test name
Test status
Simulation time 171977236 ps
CPU time 2.42 seconds
Started Aug 16 06:07:17 PM PDT 24
Finished Aug 16 06:07:20 PM PDT 24
Peak memory 226564 kb
Host smart-fd3b13af-3c9e-4a9f-804e-c5537651ae76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873403978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.2873403978 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_key_error/latest

Test location /workspace/coverage/default/16.kmac_lc_escalation.3625351457
Short name T615
Test name
Test status
Simulation time 105147456 ps
CPU time 1.79 seconds
Started Aug 16 06:07:24 PM PDT 24
Finished Aug 16 06:07:26 PM PDT 24
Peak memory 226632 kb
Host smart-079740de-ea92-43ac-8e59-47bf0d64137a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625351457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.3625351457 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/16.kmac_lc_escalation/latest

Test location /workspace/coverage/default/16.kmac_long_msg_and_output.1343336826
Short name T135
Test name
Test status
Simulation time 32646789129 ps
CPU time 208.67 seconds
Started Aug 16 06:07:17 PM PDT 24
Finished Aug 16 06:10:46 PM PDT 24
Peak memory 457272 kb
Host smart-30e556dd-0343-48f3-bb4b-9be9c19dcbc5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343336826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_a
nd_output.1343336826 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/16.kmac_sideload.2474547955
Short name T320
Test name
Test status
Simulation time 12188309997 ps
CPU time 238.49 seconds
Started Aug 16 06:07:34 PM PDT 24
Finished Aug 16 06:11:32 PM PDT 24
Peak memory 317104 kb
Host smart-dc933bce-9f62-447b-a6b7-6663da1d4adf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474547955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.2474547955 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_sideload/latest

Test location /workspace/coverage/default/16.kmac_smoke.2656106510
Short name T375
Test name
Test status
Simulation time 1361216121 ps
CPU time 7.87 seconds
Started Aug 16 06:07:18 PM PDT 24
Finished Aug 16 06:07:26 PM PDT 24
Peak memory 226776 kb
Host smart-4d690416-90f1-4f3a-888a-568e85bbd0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656106510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.2656106510 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_smoke/latest

Test location /workspace/coverage/default/16.kmac_stress_all.1879875448
Short name T473
Test name
Test status
Simulation time 22413198611 ps
CPU time 627.67 seconds
Started Aug 16 06:07:17 PM PDT 24
Finished Aug 16 06:17:45 PM PDT 24
Peak memory 406500 kb
Host smart-ce04ccc2-0d45-44c2-94b3-d8c762ac7620
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1879875448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.1879875448 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_stress_all/latest

Test location /workspace/coverage/default/17.kmac_alert_test.3251243751
Short name T315
Test name
Test status
Simulation time 36363920 ps
CPU time 0.89 seconds
Started Aug 16 06:07:36 PM PDT 24
Finished Aug 16 06:07:37 PM PDT 24
Peak memory 218196 kb
Host smart-434cc622-3350-49c4-97a7-7d9726e570cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251243751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.3251243751 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_alert_test/latest

Test location /workspace/coverage/default/17.kmac_app.1250661531
Short name T280
Test name
Test status
Simulation time 3284153705 ps
CPU time 8.67 seconds
Started Aug 16 06:07:30 PM PDT 24
Finished Aug 16 06:07:39 PM PDT 24
Peak memory 234908 kb
Host smart-bf9ac499-3609-4804-8911-1c3146bbe1c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250661531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.1250661531 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/17.kmac_app/latest

Test location /workspace/coverage/default/17.kmac_burst_write.3125707757
Short name T80
Test name
Test status
Simulation time 76326191544 ps
CPU time 1037.67 seconds
Started Aug 16 06:07:34 PM PDT 24
Finished Aug 16 06:24:52 PM PDT 24
Peak memory 255128 kb
Host smart-cc3c63fd-c4e1-46a1-a91c-67f4aa468dff
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125707757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.312570775
7 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_burst_write/latest

Test location /workspace/coverage/default/17.kmac_edn_timeout_error.2581507300
Short name T246
Test name
Test status
Simulation time 5827501749 ps
CPU time 24.8 seconds
Started Aug 16 06:07:29 PM PDT 24
Finished Aug 16 06:07:54 PM PDT 24
Peak memory 240336 kb
Host smart-73764fc5-3699-48be-8470-5cb105c23ed9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2581507300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.2581507300 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_mode_error.1077785389
Short name T79
Test name
Test status
Simulation time 50566906 ps
CPU time 1.34 seconds
Started Aug 16 06:07:31 PM PDT 24
Finished Aug 16 06:07:33 PM PDT 24
Peak memory 222048 kb
Host smart-46f93171-dc63-4230-9443-b68c20c6e4b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1077785389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.1077785389 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_refresh.2249539913
Short name T349
Test name
Test status
Simulation time 7522044651 ps
CPU time 70.92 seconds
Started Aug 16 06:07:33 PM PDT 24
Finished Aug 16 06:08:44 PM PDT 24
Peak memory 272936 kb
Host smart-0205b877-1fd9-4e17-a742-4ed1eaa6c44c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249539913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.2
249539913 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/17.kmac_error.1024531900
Short name T422
Test name
Test status
Simulation time 17603893577 ps
CPU time 147.04 seconds
Started Aug 16 06:07:31 PM PDT 24
Finished Aug 16 06:09:59 PM PDT 24
Peak memory 330264 kb
Host smart-0743189d-e6df-4bac-910c-56ce51093547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024531900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.1024531900 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_error/latest

Test location /workspace/coverage/default/17.kmac_key_error.1645909436
Short name T266
Test name
Test status
Simulation time 4589841624 ps
CPU time 9.97 seconds
Started Aug 16 06:07:30 PM PDT 24
Finished Aug 16 06:07:40 PM PDT 24
Peak memory 226680 kb
Host smart-9b3d6b4e-811c-4e8e-89c3-e9115e487a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645909436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.1645909436 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_key_error/latest

Test location /workspace/coverage/default/17.kmac_lc_escalation.2918707976
Short name T460
Test name
Test status
Simulation time 52632803 ps
CPU time 1.43 seconds
Started Aug 16 06:07:32 PM PDT 24
Finished Aug 16 06:07:33 PM PDT 24
Peak memory 226588 kb
Host smart-1118d2d1-1a76-45d0-a1ac-4011676f1182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918707976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.2918707976 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/17.kmac_lc_escalation/latest

Test location /workspace/coverage/default/17.kmac_sideload.207540371
Short name T671
Test name
Test status
Simulation time 8692722188 ps
CPU time 191.25 seconds
Started Aug 16 06:07:32 PM PDT 24
Finished Aug 16 06:10:44 PM PDT 24
Peak memory 286992 kb
Host smart-bacd64d7-47d8-4884-98f1-c33642969772
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207540371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.207540371 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_sideload/latest

Test location /workspace/coverage/default/17.kmac_smoke.1732412232
Short name T202
Test name
Test status
Simulation time 16028419956 ps
CPU time 79.05 seconds
Started Aug 16 06:07:25 PM PDT 24
Finished Aug 16 06:08:44 PM PDT 24
Peak memory 229784 kb
Host smart-e30846d7-77f3-4b04-870d-24ecf57c8a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732412232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.1732412232 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_smoke/latest

Test location /workspace/coverage/default/18.kmac_alert_test.3721281443
Short name T666
Test name
Test status
Simulation time 14543068 ps
CPU time 0.81 seconds
Started Aug 16 06:07:31 PM PDT 24
Finished Aug 16 06:07:32 PM PDT 24
Peak memory 218244 kb
Host smart-119ceefd-4da6-4054-b20b-7d588dd669e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721281443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.3721281443 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_alert_test/latest

Test location /workspace/coverage/default/18.kmac_app.2101354682
Short name T114
Test name
Test status
Simulation time 4982681558 ps
CPU time 81.26 seconds
Started Aug 16 06:07:33 PM PDT 24
Finished Aug 16 06:08:54 PM PDT 24
Peak memory 253044 kb
Host smart-7e1000c5-d24e-4f88-bede-ff4b5b14d7b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101354682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.2101354682 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/18.kmac_app/latest

Test location /workspace/coverage/default/18.kmac_burst_write.2035203886
Short name T130
Test name
Test status
Simulation time 1782002718 ps
CPU time 111.97 seconds
Started Aug 16 06:07:30 PM PDT 24
Finished Aug 16 06:09:23 PM PDT 24
Peak memory 240788 kb
Host smart-d2ba3fc5-6623-4e61-93dd-22283b3016c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035203886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.203520388
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_burst_write/latest

Test location /workspace/coverage/default/18.kmac_edn_timeout_error.1593424543
Short name T3
Test name
Test status
Simulation time 4018311398 ps
CPU time 43.35 seconds
Started Aug 16 06:07:30 PM PDT 24
Finished Aug 16 06:08:14 PM PDT 24
Peak memory 236488 kb
Host smart-04a701a0-1768-4335-88d0-1930b940edc5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1593424543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.1593424543 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_mode_error.1666302374
Short name T678
Test name
Test status
Simulation time 41584072 ps
CPU time 1.21 seconds
Started Aug 16 06:07:39 PM PDT 24
Finished Aug 16 06:07:40 PM PDT 24
Peak memory 221816 kb
Host smart-89c63a3d-f016-486d-ae1d-32ef0e235860
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1666302374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.1666302374 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_refresh.3287147355
Short name T412
Test name
Test status
Simulation time 34904550110 ps
CPU time 229.41 seconds
Started Aug 16 06:07:27 PM PDT 24
Finished Aug 16 06:11:16 PM PDT 24
Peak memory 381340 kb
Host smart-acf1e41c-a0c4-45ad-b2f3-a81decf1a5d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287147355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.3
287147355 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/18.kmac_error.1040789125
Short name T279
Test name
Test status
Simulation time 4901562547 ps
CPU time 141.21 seconds
Started Aug 16 06:07:29 PM PDT 24
Finished Aug 16 06:09:50 PM PDT 24
Peak memory 333836 kb
Host smart-30aeb9ad-f355-4a5f-a751-9e87fa13ec88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040789125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.1040789125 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_error/latest

Test location /workspace/coverage/default/18.kmac_key_error.3308125306
Short name T100
Test name
Test status
Simulation time 5458178732 ps
CPU time 10.29 seconds
Started Aug 16 06:07:33 PM PDT 24
Finished Aug 16 06:07:44 PM PDT 24
Peak memory 226756 kb
Host smart-80e11605-7b36-4a3f-baf2-d90a774cb5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308125306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.3308125306 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_key_error/latest

Test location /workspace/coverage/default/18.kmac_lc_escalation.4209796355
Short name T262
Test name
Test status
Simulation time 73050519 ps
CPU time 1.35 seconds
Started Aug 16 06:07:30 PM PDT 24
Finished Aug 16 06:07:32 PM PDT 24
Peak memory 226652 kb
Host smart-5ed52fca-dd5e-4e66-a026-62b9bc222edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209796355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.4209796355 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/18.kmac_lc_escalation/latest

Test location /workspace/coverage/default/18.kmac_long_msg_and_output.1511452207
Short name T205
Test name
Test status
Simulation time 61191564539 ps
CPU time 3203.17 seconds
Started Aug 16 06:07:37 PM PDT 24
Finished Aug 16 07:01:00 PM PDT 24
Peak memory 2973984 kb
Host smart-2fb76d5f-36b0-4d88-a1ad-68643e4b9120
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511452207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_a
nd_output.1511452207 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/18.kmac_sideload.294059076
Short name T385
Test name
Test status
Simulation time 12031349093 ps
CPU time 440.7 seconds
Started Aug 16 06:07:29 PM PDT 24
Finished Aug 16 06:14:50 PM PDT 24
Peak memory 529184 kb
Host smart-35e2f97e-8241-4df9-ae9f-d49936cc90af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294059076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.294059076 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_sideload/latest

Test location /workspace/coverage/default/18.kmac_smoke.338158107
Short name T308
Test name
Test status
Simulation time 933922444 ps
CPU time 21.16 seconds
Started Aug 16 06:07:31 PM PDT 24
Finished Aug 16 06:07:52 PM PDT 24
Peak memory 226692 kb
Host smart-09f9d447-20c9-4818-a429-69c32dd6c648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338158107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.338158107 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_smoke/latest

Test location /workspace/coverage/default/18.kmac_stress_all.3322055406
Short name T147
Test name
Test status
Simulation time 79990930538 ps
CPU time 887.98 seconds
Started Aug 16 06:07:34 PM PDT 24
Finished Aug 16 06:22:22 PM PDT 24
Peak memory 821220 kb
Host smart-5c2c8c9e-2199-4e03-8018-658f7854aed5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3322055406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.3322055406 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_stress_all/latest

Test location /workspace/coverage/default/19.kmac_alert_test.1951695603
Short name T226
Test name
Test status
Simulation time 11761920 ps
CPU time 0.77 seconds
Started Aug 16 06:07:38 PM PDT 24
Finished Aug 16 06:07:39 PM PDT 24
Peak memory 218392 kb
Host smart-a609224b-6cda-449d-be98-ff877d225856
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951695603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.1951695603 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_alert_test/latest

Test location /workspace/coverage/default/19.kmac_app.4153352542
Short name T198
Test name
Test status
Simulation time 8403663328 ps
CPU time 110.28 seconds
Started Aug 16 06:07:38 PM PDT 24
Finished Aug 16 06:09:28 PM PDT 24
Peak memory 258116 kb
Host smart-fd9df17a-4f69-43b6-bfb6-9f5218725794
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153352542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.4153352542 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/19.kmac_app/latest

Test location /workspace/coverage/default/19.kmac_burst_write.3441511702
Short name T549
Test name
Test status
Simulation time 9955646087 ps
CPU time 126.23 seconds
Started Aug 16 06:07:40 PM PDT 24
Finished Aug 16 06:09:46 PM PDT 24
Peak memory 239012 kb
Host smart-e88daebe-f239-4636-a3a2-182bdf3e00fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441511702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.344151170
2 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_burst_write/latest

Test location /workspace/coverage/default/19.kmac_edn_timeout_error.2437120513
Short name T434
Test name
Test status
Simulation time 149378367 ps
CPU time 0.93 seconds
Started Aug 16 06:07:37 PM PDT 24
Finished Aug 16 06:07:38 PM PDT 24
Peak memory 218164 kb
Host smart-201bc756-271c-47da-884c-dad0ea5f0e4c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2437120513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.2437120513 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_mode_error.4008212767
Short name T72
Test name
Test status
Simulation time 234189842 ps
CPU time 1.17 seconds
Started Aug 16 06:07:38 PM PDT 24
Finished Aug 16 06:07:40 PM PDT 24
Peak memory 221996 kb
Host smart-c60f53df-8146-418b-84ca-c0fa15cdaaba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4008212767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.4008212767 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_refresh.3468511217
Short name T579
Test name
Test status
Simulation time 43848012244 ps
CPU time 302.05 seconds
Started Aug 16 06:07:36 PM PDT 24
Finished Aug 16 06:12:38 PM PDT 24
Peak memory 418652 kb
Host smart-5f91b34b-d5e3-4e9d-9320-0ba2ddae8152
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468511217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.3
468511217 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/19.kmac_error.1711236513
Short name T64
Test name
Test status
Simulation time 1132069616 ps
CPU time 38.03 seconds
Started Aug 16 06:07:38 PM PDT 24
Finished Aug 16 06:08:16 PM PDT 24
Peak memory 270644 kb
Host smart-be1a260d-92f9-46a4-b2e7-3c42d3e35d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711236513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.1711236513 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_error/latest

Test location /workspace/coverage/default/19.kmac_key_error.3375791187
Short name T633
Test name
Test status
Simulation time 921483484 ps
CPU time 7.3 seconds
Started Aug 16 06:07:41 PM PDT 24
Finished Aug 16 06:07:49 PM PDT 24
Peak memory 226708 kb
Host smart-2e09a2fa-8750-4205-b707-8fc577f0a099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375791187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.3375791187 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_key_error/latest

Test location /workspace/coverage/default/19.kmac_lc_escalation.1955645216
Short name T455
Test name
Test status
Simulation time 87166696 ps
CPU time 1.52 seconds
Started Aug 16 06:07:40 PM PDT 24
Finished Aug 16 06:07:42 PM PDT 24
Peak memory 226592 kb
Host smart-81570846-2eda-4744-b7b1-233cec326531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955645216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.1955645216 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/19.kmac_lc_escalation/latest

Test location /workspace/coverage/default/19.kmac_long_msg_and_output.129424019
Short name T689
Test name
Test status
Simulation time 25941438987 ps
CPU time 358.49 seconds
Started Aug 16 06:07:35 PM PDT 24
Finished Aug 16 06:13:34 PM PDT 24
Peak memory 426848 kb
Host smart-4cefaeed-860e-4a40-9900-259bfd7f3ba3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129424019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_an
d_output.129424019 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/19.kmac_sideload.3687524400
Short name T463
Test name
Test status
Simulation time 12832060959 ps
CPU time 289.69 seconds
Started Aug 16 06:07:40 PM PDT 24
Finished Aug 16 06:12:30 PM PDT 24
Peak memory 496744 kb
Host smart-c5c18940-eca9-4cd1-9d3b-52b1bfb550c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687524400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.3687524400 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_sideload/latest

Test location /workspace/coverage/default/19.kmac_smoke.3533545814
Short name T414
Test name
Test status
Simulation time 9611354747 ps
CPU time 105.56 seconds
Started Aug 16 06:07:39 PM PDT 24
Finished Aug 16 06:09:25 PM PDT 24
Peak memory 231260 kb
Host smart-8e3f6e8c-88ee-4962-90e1-7932b37e03a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533545814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.3533545814 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_smoke/latest

Test location /workspace/coverage/default/19.kmac_stress_all.1335737731
Short name T57
Test name
Test status
Simulation time 126001526100 ps
CPU time 924.98 seconds
Started Aug 16 06:07:39 PM PDT 24
Finished Aug 16 06:23:04 PM PDT 24
Peak memory 455244 kb
Host smart-9ee636c1-de56-433b-ba99-1e01fc8ea1c6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1335737731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.1335737731 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all/latest

Test location /workspace/coverage/default/2.kmac_alert_test.4052150015
Short name T426
Test name
Test status
Simulation time 21824462 ps
CPU time 0.87 seconds
Started Aug 16 06:05:59 PM PDT 24
Finished Aug 16 06:06:01 PM PDT 24
Peak memory 218288 kb
Host smart-9b63a33c-3b84-4dc5-a0db-82b12d4689a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052150015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.4052150015 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_alert_test/latest

Test location /workspace/coverage/default/2.kmac_app.3461838624
Short name T41
Test name
Test status
Simulation time 4330345748 ps
CPU time 47.77 seconds
Started Aug 16 06:06:00 PM PDT 24
Finished Aug 16 06:06:48 PM PDT 24
Peak memory 238488 kb
Host smart-276387fc-b650-4de6-8385-1052d30f1fb3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461838624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.3461838624 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/2.kmac_app/latest

Test location /workspace/coverage/default/2.kmac_app_with_partial_data.2929601399
Short name T586
Test name
Test status
Simulation time 1948339180 ps
CPU time 118.63 seconds
Started Aug 16 06:05:59 PM PDT 24
Finished Aug 16 06:07:58 PM PDT 24
Peak memory 263640 kb
Host smart-f4d565f9-9e08-41ab-abb0-dc539e19d4ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929601399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_par
tial_data.2929601399 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/2.kmac_burst_write.3553068822
Short name T144
Test name
Test status
Simulation time 133532823188 ps
CPU time 1500.09 seconds
Started Aug 16 06:05:48 PM PDT 24
Finished Aug 16 06:30:49 PM PDT 24
Peak memory 263284 kb
Host smart-3989c08e-f47a-44bc-8b31-ec5ee23254a4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553068822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.3553068822
+enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_burst_write/latest

Test location /workspace/coverage/default/2.kmac_edn_timeout_error.1729587206
Short name T565
Test name
Test status
Simulation time 17745142 ps
CPU time 0.92 seconds
Started Aug 16 06:06:01 PM PDT 24
Finished Aug 16 06:06:02 PM PDT 24
Peak memory 218128 kb
Host smart-fa7497b5-90bf-48cf-9fc8-a0727dacfec7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1729587206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.1729587206 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_mode_error.552288511
Short name T574
Test name
Test status
Simulation time 17441873 ps
CPU time 0.84 seconds
Started Aug 16 06:05:57 PM PDT 24
Finished Aug 16 06:05:58 PM PDT 24
Peak memory 220276 kb
Host smart-0beaf70f-f419-437e-a0d2-c6eca996f3b8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=552288511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.552288511 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_ready_error.605395292
Short name T10
Test name
Test status
Simulation time 341543493 ps
CPU time 2.19 seconds
Started Aug 16 06:05:58 PM PDT 24
Finished Aug 16 06:06:00 PM PDT 24
Peak memory 223192 kb
Host smart-fb187acb-62b7-464e-aa45-1bc24f6f6f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605395292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.605395292 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_refresh.3880909703
Short name T193
Test name
Test status
Simulation time 120179414948 ps
CPU time 272.78 seconds
Started Aug 16 06:06:04 PM PDT 24
Finished Aug 16 06:10:37 PM PDT 24
Peak memory 310208 kb
Host smart-4e4b9e81-343d-4873-bfaa-a2358cfa58ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880909703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.38
80909703 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/2.kmac_error.3220640862
Short name T338
Test name
Test status
Simulation time 3988471623 ps
CPU time 349 seconds
Started Aug 16 06:05:57 PM PDT 24
Finished Aug 16 06:11:46 PM PDT 24
Peak memory 357512 kb
Host smart-6f5978d8-d5c6-45c1-bfb7-442365516c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220640862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.3220640862 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_error/latest

Test location /workspace/coverage/default/2.kmac_key_error.2201192007
Short name T247
Test name
Test status
Simulation time 3675402694 ps
CPU time 12.76 seconds
Started Aug 16 06:06:00 PM PDT 24
Finished Aug 16 06:06:13 PM PDT 24
Peak memory 226656 kb
Host smart-f4751a0f-11af-4302-9446-53e896bab5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201192007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.2201192007 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_key_error/latest

Test location /workspace/coverage/default/2.kmac_mubi.505103149
Short name T58
Test name
Test status
Simulation time 2376669366 ps
CPU time 67.14 seconds
Started Aug 16 06:06:02 PM PDT 24
Finished Aug 16 06:07:09 PM PDT 24
Peak memory 245540 kb
Host smart-67aeabe9-c419-46ff-a1ab-e72167cf30c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505103149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.505103149 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mubi/latest

Test location /workspace/coverage/default/2.kmac_sec_cm.1962983941
Short name T33
Test name
Test status
Simulation time 49339902665 ps
CPU time 77 seconds
Started Aug 16 06:06:00 PM PDT 24
Finished Aug 16 06:07:17 PM PDT 24
Peak memory 273244 kb
Host smart-f07b5e98-ea0a-43da-885f-758958b1ff15
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962983941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.1962983941 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/2.kmac_sec_cm/latest

Test location /workspace/coverage/default/2.kmac_sideload.729307353
Short name T482
Test name
Test status
Simulation time 27533826098 ps
CPU time 209.44 seconds
Started Aug 16 06:05:49 PM PDT 24
Finished Aug 16 06:09:19 PM PDT 24
Peak memory 362028 kb
Host smart-a6a24a05-cb12-46ba-98c7-d85bfd2e9daa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729307353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.729307353 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_sideload/latest

Test location /workspace/coverage/default/2.kmac_smoke.2175173545
Short name T459
Test name
Test status
Simulation time 23389313422 ps
CPU time 78.3 seconds
Started Aug 16 06:05:48 PM PDT 24
Finished Aug 16 06:07:07 PM PDT 24
Peak memory 227832 kb
Host smart-32a3379d-8a3c-4eb5-a290-9293fe47d597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175173545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.2175173545 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_smoke/latest

Test location /workspace/coverage/default/2.kmac_stress_all.4057801790
Short name T679
Test name
Test status
Simulation time 83334944642 ps
CPU time 589.09 seconds
Started Aug 16 06:06:01 PM PDT 24
Finished Aug 16 06:15:51 PM PDT 24
Peak memory 412032 kb
Host smart-37b55304-10fb-48ef-8c9c-ebc9f3d79014
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4057801790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.4057801790 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac.3299294963
Short name T617
Test name
Test status
Simulation time 110678910 ps
CPU time 2.87 seconds
Started Aug 16 06:05:53 PM PDT 24
Finished Aug 16 06:05:56 PM PDT 24
Peak memory 219532 kb
Host smart-e3778750-3461-4952-b99c-dedef05f1f47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299294963 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.kmac_test_vectors_kmac.3299294963 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac_xof.1104655660
Short name T670
Test name
Test status
Simulation time 66197938 ps
CPU time 2.46 seconds
Started Aug 16 06:05:55 PM PDT 24
Finished Aug 16 06:05:58 PM PDT 24
Peak memory 218520 kb
Host smart-8968b335-e4b4-41a0-86f1-b22fb60695f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104655660 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.kmac_test_vectors_kmac_xof.1104655660 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_224.789692235
Short name T593
Test name
Test status
Simulation time 81959847533 ps
CPU time 3544.76 seconds
Started Aug 16 06:05:52 PM PDT 24
Finished Aug 16 07:04:57 PM PDT 24
Peak memory 3105444 kb
Host smart-a2ba4f3c-46c6-4fce-9098-711c206e098c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=789692235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.789692235 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_256.324226210
Short name T276
Test name
Test status
Simulation time 634959074935 ps
CPU time 3661.33 seconds
Started Aug 16 06:05:50 PM PDT 24
Finished Aug 16 07:06:52 PM PDT 24
Peak memory 3048300 kb
Host smart-976fc313-1b01-4c98-a3b5-2a1777761978
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=324226210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.324226210 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_384.3913604725
Short name T433
Test name
Test status
Simulation time 861313655 ps
CPU time 24.47 seconds
Started Aug 16 06:05:52 PM PDT 24
Finished Aug 16 06:06:17 PM PDT 24
Peak memory 220216 kb
Host smart-ef7d2310-68bb-45d9-b0b1-694c2db62a4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3913604725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.3913604725 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_512.1196920029
Short name T223
Test name
Test status
Simulation time 41506147199 ps
CPU time 1284.55 seconds
Started Aug 16 06:05:51 PM PDT 24
Finished Aug 16 06:27:15 PM PDT 24
Peak memory 712428 kb
Host smart-53c96f43-449b-4770-ae8f-0b4537839aef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1196920029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.1196920029 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_128.3709725532
Short name T632
Test name
Test status
Simulation time 95648007456 ps
CPU time 2650.79 seconds
Started Aug 16 06:05:51 PM PDT 24
Finished Aug 16 06:50:03 PM PDT 24
Peak memory 1351528 kb
Host smart-b76fc4bd-1996-4e2a-a84f-04c9007c00e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3709725532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.3709725532 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/20.kmac_alert_test.1691921629
Short name T325
Test name
Test status
Simulation time 152912908 ps
CPU time 0.81 seconds
Started Aug 16 06:07:43 PM PDT 24
Finished Aug 16 06:07:44 PM PDT 24
Peak memory 218268 kb
Host smart-a16fdc62-8607-4b27-a282-21a697e7e0bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691921629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.1691921629 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_alert_test/latest

Test location /workspace/coverage/default/20.kmac_app.3114665375
Short name T496
Test name
Test status
Simulation time 13957674137 ps
CPU time 127.73 seconds
Started Aug 16 06:07:38 PM PDT 24
Finished Aug 16 06:09:45 PM PDT 24
Peak memory 303040 kb
Host smart-2536a104-0f00-47ae-a68f-414947a1cd67
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114665375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.3114665375 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/20.kmac_app/latest

Test location /workspace/coverage/default/20.kmac_burst_write.2197077538
Short name T553
Test name
Test status
Simulation time 9715913228 ps
CPU time 413.25 seconds
Started Aug 16 06:07:39 PM PDT 24
Finished Aug 16 06:14:33 PM PDT 24
Peak memory 240688 kb
Host smart-be81bc37-c8c4-4e2a-8df6-df89228a56a2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197077538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.219707753
8 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_burst_write/latest

Test location /workspace/coverage/default/20.kmac_entropy_refresh.4009117259
Short name T432
Test name
Test status
Simulation time 8005042429 ps
CPU time 205.66 seconds
Started Aug 16 06:07:37 PM PDT 24
Finished Aug 16 06:11:03 PM PDT 24
Peak memory 378444 kb
Host smart-6c856eb2-1481-47cd-99c4-8a7dd1edefc4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009117259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.4
009117259 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/20.kmac_error.1704674591
Short name T545
Test name
Test status
Simulation time 16715968506 ps
CPU time 230.32 seconds
Started Aug 16 06:07:40 PM PDT 24
Finished Aug 16 06:11:31 PM PDT 24
Peak memory 431828 kb
Host smart-3ac3f3f6-8632-42ab-9983-4a84b45f837b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704674591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.1704674591 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_error/latest

Test location /workspace/coverage/default/20.kmac_key_error.840597716
Short name T281
Test name
Test status
Simulation time 2084907264 ps
CPU time 6.06 seconds
Started Aug 16 06:07:38 PM PDT 24
Finished Aug 16 06:07:44 PM PDT 24
Peak memory 226480 kb
Host smart-afde4c13-9e1f-4147-bc19-8e1c9231e462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840597716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.840597716 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_key_error/latest

Test location /workspace/coverage/default/20.kmac_lc_escalation.3580307004
Short name T529
Test name
Test status
Simulation time 65924368 ps
CPU time 1.44 seconds
Started Aug 16 06:07:36 PM PDT 24
Finished Aug 16 06:07:38 PM PDT 24
Peak memory 226572 kb
Host smart-83cde88e-d5bd-4fa0-bfaf-81829afe1bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580307004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.3580307004 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/20.kmac_lc_escalation/latest

Test location /workspace/coverage/default/20.kmac_long_msg_and_output.3549692812
Short name T316
Test name
Test status
Simulation time 27297620916 ps
CPU time 3360.01 seconds
Started Aug 16 06:07:40 PM PDT 24
Finished Aug 16 07:03:41 PM PDT 24
Peak memory 1690448 kb
Host smart-5e915fbf-e350-46b9-adb1-4bfa885aee46
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549692812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_a
nd_output.3549692812 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/20.kmac_sideload.3366453656
Short name T359
Test name
Test status
Simulation time 17524996614 ps
CPU time 128.63 seconds
Started Aug 16 06:07:40 PM PDT 24
Finished Aug 16 06:09:49 PM PDT 24
Peak memory 273080 kb
Host smart-c5fe57a8-ffa0-4e46-bfa2-3adf942f2a2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366453656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.3366453656 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_sideload/latest

Test location /workspace/coverage/default/20.kmac_smoke.3038592730
Short name T413
Test name
Test status
Simulation time 541636913 ps
CPU time 20.38 seconds
Started Aug 16 06:07:39 PM PDT 24
Finished Aug 16 06:07:59 PM PDT 24
Peak memory 226720 kb
Host smart-f13b1992-5360-4a6b-b076-cd9450d77683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038592730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.3038592730 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_smoke/latest

Test location /workspace/coverage/default/20.kmac_stress_all.3295802644
Short name T448
Test name
Test status
Simulation time 15428271735 ps
CPU time 1207.21 seconds
Started Aug 16 06:07:40 PM PDT 24
Finished Aug 16 06:27:47 PM PDT 24
Peak memory 653492 kb
Host smart-457d392d-1b74-4fa0-9ae6-88a82890b055
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3295802644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.3295802644 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_stress_all/latest

Test location /workspace/coverage/default/21.kmac_alert_test.1430915929
Short name T240
Test name
Test status
Simulation time 15937412 ps
CPU time 0.77 seconds
Started Aug 16 06:07:57 PM PDT 24
Finished Aug 16 06:07:57 PM PDT 24
Peak memory 218136 kb
Host smart-0b6b3203-b8e9-4ab8-b5c0-7589fc195b71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430915929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.1430915929 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_alert_test/latest

Test location /workspace/coverage/default/21.kmac_app.1353390473
Short name T643
Test name
Test status
Simulation time 11996886554 ps
CPU time 157.49 seconds
Started Aug 16 06:07:45 PM PDT 24
Finished Aug 16 06:10:23 PM PDT 24
Peak memory 272036 kb
Host smart-95d68c22-5142-4412-b74e-89b7604a3275
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353390473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.1353390473 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/21.kmac_app/latest

Test location /workspace/coverage/default/21.kmac_burst_write.14599110
Short name T313
Test name
Test status
Simulation time 48156059096 ps
CPU time 1184.44 seconds
Started Aug 16 06:07:49 PM PDT 24
Finished Aug 16 06:27:33 PM PDT 24
Peak memory 244800 kb
Host smart-ddd523f8-1cd7-4e54-9f6d-3510597b6016
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14599110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.14599110 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_burst_write/latest

Test location /workspace/coverage/default/21.kmac_error.371896450
Short name T311
Test name
Test status
Simulation time 65401320985 ps
CPU time 537.32 seconds
Started Aug 16 06:07:49 PM PDT 24
Finished Aug 16 06:16:46 PM PDT 24
Peak memory 583892 kb
Host smart-7b4556a4-b189-497e-8038-6c831efc9c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371896450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.371896450 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_error/latest

Test location /workspace/coverage/default/21.kmac_key_error.2810665413
Short name T660
Test name
Test status
Simulation time 1573437066 ps
CPU time 10.96 seconds
Started Aug 16 06:07:49 PM PDT 24
Finished Aug 16 06:08:00 PM PDT 24
Peak memory 226432 kb
Host smart-d7f4e27e-1d8d-440f-8e01-ae7bbfbe6122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810665413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.2810665413 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_key_error/latest

Test location /workspace/coverage/default/21.kmac_lc_escalation.3867032864
Short name T47
Test name
Test status
Simulation time 38965142 ps
CPU time 1.64 seconds
Started Aug 16 06:07:45 PM PDT 24
Finished Aug 16 06:07:47 PM PDT 24
Peak memory 226576 kb
Host smart-d7b64613-7335-454b-ba5b-ccc56493e4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867032864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.3867032864 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/21.kmac_lc_escalation/latest

Test location /workspace/coverage/default/21.kmac_long_msg_and_output.2115073633
Short name T572
Test name
Test status
Simulation time 11303580097 ps
CPU time 333.16 seconds
Started Aug 16 06:07:47 PM PDT 24
Finished Aug 16 06:13:21 PM PDT 24
Peak memory 384524 kb
Host smart-802e1c5b-57cc-4169-b0c5-a7af32e0762b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115073633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_a
nd_output.2115073633 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/21.kmac_sideload.3425723869
Short name T231
Test name
Test status
Simulation time 213948797 ps
CPU time 5.48 seconds
Started Aug 16 06:07:50 PM PDT 24
Finished Aug 16 06:07:56 PM PDT 24
Peak memory 242364 kb
Host smart-9befc683-425d-419b-ba1d-28dde15a4fb2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425723869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.3425723869 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_sideload/latest

Test location /workspace/coverage/default/21.kmac_smoke.2748032089
Short name T224
Test name
Test status
Simulation time 250430250 ps
CPU time 10.94 seconds
Started Aug 16 06:07:47 PM PDT 24
Finished Aug 16 06:07:58 PM PDT 24
Peak memory 226672 kb
Host smart-a2e524ea-ac48-47db-b077-6b96ee0b28b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748032089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.2748032089 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_smoke/latest

Test location /workspace/coverage/default/21.kmac_stress_all.3464460666
Short name T77
Test name
Test status
Simulation time 27324599905 ps
CPU time 452.08 seconds
Started Aug 16 06:07:48 PM PDT 24
Finished Aug 16 06:15:20 PM PDT 24
Peak memory 340860 kb
Host smart-030408bb-1dd5-42e9-833e-c60aa8060a35
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3464460666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.3464460666 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_stress_all/latest

Test location /workspace/coverage/default/22.kmac_alert_test.651520166
Short name T317
Test name
Test status
Simulation time 21763704 ps
CPU time 0.84 seconds
Started Aug 16 06:07:57 PM PDT 24
Finished Aug 16 06:07:57 PM PDT 24
Peak memory 218184 kb
Host smart-41dd4869-154c-48c2-913d-9690c9f9ea95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651520166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.651520166 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/22.kmac_alert_test/latest

Test location /workspace/coverage/default/22.kmac_app.1896859499
Short name T328
Test name
Test status
Simulation time 55035771585 ps
CPU time 371.71 seconds
Started Aug 16 06:07:54 PM PDT 24
Finished Aug 16 06:14:06 PM PDT 24
Peak memory 474548 kb
Host smart-2b0be4b3-2f68-41c8-9a57-7a16495262c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896859499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.1896859499 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/22.kmac_app/latest

Test location /workspace/coverage/default/22.kmac_burst_write.857283817
Short name T526
Test name
Test status
Simulation time 52114070686 ps
CPU time 1223.18 seconds
Started Aug 16 06:07:55 PM PDT 24
Finished Aug 16 06:28:19 PM PDT 24
Peak memory 259564 kb
Host smart-15960be6-c8bb-4178-a8fb-a46f5c4c3e86
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857283817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.857283817
+enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_burst_write/latest

Test location /workspace/coverage/default/22.kmac_entropy_refresh.1511586228
Short name T400
Test name
Test status
Simulation time 2322009017 ps
CPU time 208.88 seconds
Started Aug 16 06:07:53 PM PDT 24
Finished Aug 16 06:11:22 PM PDT 24
Peak memory 293836 kb
Host smart-401ae3f4-38b9-457d-a4b0-d8cee77d9fa2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511586228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.1
511586228 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/22.kmac_error.4280851770
Short name T629
Test name
Test status
Simulation time 24348144989 ps
CPU time 498.63 seconds
Started Aug 16 06:07:55 PM PDT 24
Finished Aug 16 06:16:14 PM PDT 24
Peak memory 398440 kb
Host smart-e3398d6c-164f-4314-b5c4-4539476bebce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280851770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.4280851770 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_error/latest

Test location /workspace/coverage/default/22.kmac_key_error.3567890319
Short name T680
Test name
Test status
Simulation time 6014861659 ps
CPU time 11.38 seconds
Started Aug 16 06:07:56 PM PDT 24
Finished Aug 16 06:08:07 PM PDT 24
Peak memory 226672 kb
Host smart-21d0d4a2-edc2-469b-92e2-ff845125d90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567890319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.3567890319 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_key_error/latest

Test location /workspace/coverage/default/22.kmac_lc_escalation.3601145407
Short name T306
Test name
Test status
Simulation time 38275434 ps
CPU time 1.37 seconds
Started Aug 16 06:07:56 PM PDT 24
Finished Aug 16 06:07:58 PM PDT 24
Peak memory 226668 kb
Host smart-925aff40-8ab5-409c-96cf-cf302145050a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601145407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.3601145407 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/22.kmac_lc_escalation/latest

Test location /workspace/coverage/default/22.kmac_long_msg_and_output.3519686888
Short name T583
Test name
Test status
Simulation time 7052105436 ps
CPU time 266.83 seconds
Started Aug 16 06:07:57 PM PDT 24
Finished Aug 16 06:12:24 PM PDT 24
Peak memory 542312 kb
Host smart-2e79e35d-75cc-4648-9e49-fe2ce7b4671a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519686888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_a
nd_output.3519686888 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/22.kmac_sideload.2599213636
Short name T507
Test name
Test status
Simulation time 20271252876 ps
CPU time 344.18 seconds
Started Aug 16 06:07:56 PM PDT 24
Finished Aug 16 06:13:41 PM PDT 24
Peak memory 338640 kb
Host smart-f3d5608d-8797-488b-806d-8911582d5288
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599213636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.2599213636 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_sideload/latest

Test location /workspace/coverage/default/22.kmac_smoke.462235728
Short name T112
Test name
Test status
Simulation time 1229890789 ps
CPU time 6.92 seconds
Started Aug 16 06:08:00 PM PDT 24
Finished Aug 16 06:08:07 PM PDT 24
Peak memory 222888 kb
Host smart-bde8a8f1-901b-414b-bd86-b18e1421a7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462235728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.462235728 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_smoke/latest

Test location /workspace/coverage/default/22.kmac_stress_all.214119399
Short name T263
Test name
Test status
Simulation time 5978296773 ps
CPU time 53.75 seconds
Started Aug 16 06:07:59 PM PDT 24
Finished Aug 16 06:08:53 PM PDT 24
Peak memory 239136 kb
Host smart-5ccb4d4e-d555-4e5a-b8b7-ee4221137853
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=214119399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.214119399 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_stress_all/latest

Test location /workspace/coverage/default/23.kmac_alert_test.4206635004
Short name T298
Test name
Test status
Simulation time 102990730 ps
CPU time 0.91 seconds
Started Aug 16 06:08:06 PM PDT 24
Finished Aug 16 06:08:07 PM PDT 24
Peak memory 218248 kb
Host smart-e9f620aa-3a84-477e-b298-9b85db790371
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206635004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.4206635004 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_alert_test/latest

Test location /workspace/coverage/default/23.kmac_app.278613919
Short name T200
Test name
Test status
Simulation time 30618898299 ps
CPU time 402.24 seconds
Started Aug 16 06:07:54 PM PDT 24
Finished Aug 16 06:14:36 PM PDT 24
Peak memory 503828 kb
Host smart-4cb0b4c3-8289-4a8d-a5de-87e2521d3b34
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278613919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.278613919 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/23.kmac_app/latest

Test location /workspace/coverage/default/23.kmac_burst_write.1964372039
Short name T339
Test name
Test status
Simulation time 2385208420 ps
CPU time 131.15 seconds
Started Aug 16 06:07:58 PM PDT 24
Finished Aug 16 06:10:10 PM PDT 24
Peak memory 235896 kb
Host smart-46cff296-a243-4ce1-bbe9-db22febbd854
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964372039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.196437203
9 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_burst_write/latest

Test location /workspace/coverage/default/23.kmac_entropy_refresh.487819993
Short name T705
Test name
Test status
Simulation time 32874317228 ps
CPU time 246.44 seconds
Started Aug 16 06:08:00 PM PDT 24
Finished Aug 16 06:12:06 PM PDT 24
Peak memory 385200 kb
Host smart-12261bdd-1e99-48fb-b421-7bd544ea6de0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487819993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.48
7819993 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/23.kmac_error.3647497053
Short name T333
Test name
Test status
Simulation time 3434349262 ps
CPU time 279.62 seconds
Started Aug 16 06:07:55 PM PDT 24
Finished Aug 16 06:12:35 PM PDT 24
Peak memory 334060 kb
Host smart-be27d92c-6d78-4d89-afb2-82bfa519ebbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647497053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.3647497053 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_error/latest

Test location /workspace/coverage/default/23.kmac_key_error.651269257
Short name T672
Test name
Test status
Simulation time 3319940132 ps
CPU time 8.93 seconds
Started Aug 16 06:08:10 PM PDT 24
Finished Aug 16 06:08:20 PM PDT 24
Peak memory 226708 kb
Host smart-50cba8b3-511a-402a-9bd7-475f82937cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651269257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.651269257 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_key_error/latest

Test location /workspace/coverage/default/23.kmac_lc_escalation.550923343
Short name T50
Test name
Test status
Simulation time 694111359 ps
CPU time 1.75 seconds
Started Aug 16 06:08:05 PM PDT 24
Finished Aug 16 06:08:07 PM PDT 24
Peak memory 226676 kb
Host smart-7daf6a2c-db55-43ef-aff8-7bd00f574d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550923343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.550923343 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/23.kmac_lc_escalation/latest

Test location /workspace/coverage/default/23.kmac_long_msg_and_output.3444069541
Short name T203
Test name
Test status
Simulation time 148434304104 ps
CPU time 3377.5 seconds
Started Aug 16 06:07:56 PM PDT 24
Finished Aug 16 07:04:14 PM PDT 24
Peak memory 2934024 kb
Host smart-66f34796-1caa-415c-b27c-f40184846624
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444069541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_a
nd_output.3444069541 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/23.kmac_sideload.2385334015
Short name T495
Test name
Test status
Simulation time 7434881694 ps
CPU time 259.69 seconds
Started Aug 16 06:07:54 PM PDT 24
Finished Aug 16 06:12:14 PM PDT 24
Peak memory 429364 kb
Host smart-1a63a766-a577-4ed7-a5fc-fea77fe601fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385334015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.2385334015 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_sideload/latest

Test location /workspace/coverage/default/23.kmac_smoke.1077505929
Short name T603
Test name
Test status
Simulation time 1076009782 ps
CPU time 7.26 seconds
Started Aug 16 06:07:55 PM PDT 24
Finished Aug 16 06:08:02 PM PDT 24
Peak memory 226684 kb
Host smart-6391ace9-a303-4b6a-ae89-56a54a5266a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077505929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.1077505929 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_smoke/latest

Test location /workspace/coverage/default/23.kmac_stress_all.1371937840
Short name T647
Test name
Test status
Simulation time 116316684819 ps
CPU time 1022.19 seconds
Started Aug 16 06:08:07 PM PDT 24
Finished Aug 16 06:25:09 PM PDT 24
Peak memory 928696 kb
Host smart-46e9a647-d60c-49e7-9fef-051be18b0215
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1371937840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.1371937840 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all/latest

Test location /workspace/coverage/default/24.kmac_alert_test.2465172064
Short name T367
Test name
Test status
Simulation time 40683113 ps
CPU time 0.86 seconds
Started Aug 16 06:08:09 PM PDT 24
Finished Aug 16 06:08:10 PM PDT 24
Peak memory 218196 kb
Host smart-19ba158a-2d87-4f31-9b77-f46319defdac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465172064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.2465172064 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_alert_test/latest

Test location /workspace/coverage/default/24.kmac_app.594608643
Short name T377
Test name
Test status
Simulation time 8626788827 ps
CPU time 140.58 seconds
Started Aug 16 06:08:04 PM PDT 24
Finished Aug 16 06:10:25 PM PDT 24
Peak memory 321212 kb
Host smart-ef8b3c4e-912e-400a-9bd6-712006334cca
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594608643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.594608643 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/24.kmac_app/latest

Test location /workspace/coverage/default/24.kmac_burst_write.2798392374
Short name T686
Test name
Test status
Simulation time 22018065182 ps
CPU time 1079.08 seconds
Started Aug 16 06:08:06 PM PDT 24
Finished Aug 16 06:26:05 PM PDT 24
Peak memory 257184 kb
Host smart-0e8ce505-c15f-4005-80cc-7310aa1908dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798392374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.279839237
4 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_burst_write/latest

Test location /workspace/coverage/default/24.kmac_entropy_refresh.1080394970
Short name T442
Test name
Test status
Simulation time 6645080242 ps
CPU time 290.98 seconds
Started Aug 16 06:08:05 PM PDT 24
Finished Aug 16 06:12:56 PM PDT 24
Peak memory 316916 kb
Host smart-07773250-07bf-44eb-9df4-c77d89652194
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080394970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.1
080394970 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/24.kmac_error.2365784717
Short name T627
Test name
Test status
Simulation time 18317856465 ps
CPU time 410.04 seconds
Started Aug 16 06:08:06 PM PDT 24
Finished Aug 16 06:14:56 PM PDT 24
Peak memory 547852 kb
Host smart-754cccf4-1877-4574-a0e7-0038d84bc17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365784717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.2365784717 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_error/latest

Test location /workspace/coverage/default/24.kmac_key_error.1366252701
Short name T497
Test name
Test status
Simulation time 1228354117 ps
CPU time 9.32 seconds
Started Aug 16 06:08:10 PM PDT 24
Finished Aug 16 06:08:19 PM PDT 24
Peak memory 226604 kb
Host smart-fcd3ff36-b174-4721-947e-9df8b3a65024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366252701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.1366252701 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_key_error/latest

Test location /workspace/coverage/default/24.kmac_lc_escalation.2053707301
Short name T616
Test name
Test status
Simulation time 3541210205 ps
CPU time 27.51 seconds
Started Aug 16 06:08:10 PM PDT 24
Finished Aug 16 06:08:38 PM PDT 24
Peak memory 253432 kb
Host smart-50ffd6ef-2bbf-4ecc-9834-baba9903564d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053707301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.2053707301 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/24.kmac_lc_escalation/latest

Test location /workspace/coverage/default/24.kmac_long_msg_and_output.4289747313
Short name T143
Test name
Test status
Simulation time 50494053287 ps
CPU time 2181.67 seconds
Started Aug 16 06:08:06 PM PDT 24
Finished Aug 16 06:44:28 PM PDT 24
Peak memory 2106024 kb
Host smart-2c74f406-163c-4ec4-9330-afab62f519ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289747313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_a
nd_output.4289747313 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/24.kmac_sideload.417611
Short name T517
Test name
Test status
Simulation time 5854067447 ps
CPU time 210.54 seconds
Started Aug 16 06:08:08 PM PDT 24
Finished Aug 16 06:11:38 PM PDT 24
Peak memory 376344 kb
Host smart-e25ed9b9-1f9e-4ab1-a8d7-bea237e55f5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417611 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.417611 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/24.kmac_sideload/latest

Test location /workspace/coverage/default/24.kmac_smoke.2899133039
Short name T581
Test name
Test status
Simulation time 2640903313 ps
CPU time 74.92 seconds
Started Aug 16 06:08:05 PM PDT 24
Finished Aug 16 06:09:20 PM PDT 24
Peak memory 222872 kb
Host smart-5138f76f-c4a8-4dad-932a-f571aa3a22eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899133039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.2899133039 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_smoke/latest

Test location /workspace/coverage/default/24.kmac_stress_all.1613213727
Short name T323
Test name
Test status
Simulation time 8703960443 ps
CPU time 591.79 seconds
Started Aug 16 06:08:08 PM PDT 24
Finished Aug 16 06:18:00 PM PDT 24
Peak memory 312312 kb
Host smart-61a98a9c-22d7-45c7-bdac-756de240a069
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1613213727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.1613213727 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_stress_all/latest

Test location /workspace/coverage/default/25.kmac_alert_test.3271332411
Short name T462
Test name
Test status
Simulation time 44096591 ps
CPU time 0.85 seconds
Started Aug 16 06:08:17 PM PDT 24
Finished Aug 16 06:08:18 PM PDT 24
Peak memory 218264 kb
Host smart-63626b89-03de-4172-bb50-c516d0071339
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271332411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.3271332411 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_alert_test/latest

Test location /workspace/coverage/default/25.kmac_app.2788317517
Short name T353
Test name
Test status
Simulation time 36468513733 ps
CPU time 251.06 seconds
Started Aug 16 06:08:05 PM PDT 24
Finished Aug 16 06:12:16 PM PDT 24
Peak memory 418872 kb
Host smart-79680bd2-8e81-45f2-9401-3b21c8313b30
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788317517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.2788317517 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/25.kmac_app/latest

Test location /workspace/coverage/default/25.kmac_burst_write.3100795989
Short name T83
Test name
Test status
Simulation time 18397216696 ps
CPU time 559.05 seconds
Started Aug 16 06:08:07 PM PDT 24
Finished Aug 16 06:17:27 PM PDT 24
Peak memory 240348 kb
Host smart-c181489f-d992-44aa-9727-36918990a1e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100795989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.310079598
9 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_burst_write/latest

Test location /workspace/coverage/default/25.kmac_entropy_refresh.2431956793
Short name T300
Test name
Test status
Simulation time 21890321659 ps
CPU time 343.94 seconds
Started Aug 16 06:08:05 PM PDT 24
Finished Aug 16 06:13:49 PM PDT 24
Peak memory 318860 kb
Host smart-54c07c67-6a0c-4572-a6bc-de1c95114dc1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431956793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.2
431956793 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/25.kmac_error.3482266817
Short name T162
Test name
Test status
Simulation time 67702850324 ps
CPU time 234.92 seconds
Started Aug 16 06:08:05 PM PDT 24
Finished Aug 16 06:12:01 PM PDT 24
Peak memory 423212 kb
Host smart-00f8b231-9e44-4644-97f7-fb15cebaacc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482266817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.3482266817 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_error/latest

Test location /workspace/coverage/default/25.kmac_key_error.2186672531
Short name T374
Test name
Test status
Simulation time 786435012 ps
CPU time 3.71 seconds
Started Aug 16 06:08:05 PM PDT 24
Finished Aug 16 06:08:09 PM PDT 24
Peak memory 226424 kb
Host smart-246b8041-7395-4c14-aa14-286a56c1087a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186672531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.2186672531 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_key_error/latest

Test location /workspace/coverage/default/25.kmac_long_msg_and_output.2551844112
Short name T621
Test name
Test status
Simulation time 78340905103 ps
CPU time 2530.66 seconds
Started Aug 16 06:08:08 PM PDT 24
Finished Aug 16 06:50:19 PM PDT 24
Peak memory 1247612 kb
Host smart-1e35f49d-7d07-408d-b4f7-ed450d95bee9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551844112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_a
nd_output.2551844112 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/25.kmac_sideload.398588950
Short name T259
Test name
Test status
Simulation time 37204625737 ps
CPU time 546.74 seconds
Started Aug 16 06:08:05 PM PDT 24
Finished Aug 16 06:17:11 PM PDT 24
Peak memory 399860 kb
Host smart-12fa81db-7627-459e-8552-b14509ad19fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398588950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.398588950 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_sideload/latest

Test location /workspace/coverage/default/25.kmac_smoke.634214097
Short name T302
Test name
Test status
Simulation time 1661646821 ps
CPU time 16.79 seconds
Started Aug 16 06:08:07 PM PDT 24
Finished Aug 16 06:08:24 PM PDT 24
Peak memory 226716 kb
Host smart-04272658-fae6-44a8-b690-a45a1e90e2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634214097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.634214097 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_smoke/latest

Test location /workspace/coverage/default/25.kmac_stress_all.3863676532
Short name T700
Test name
Test status
Simulation time 17377798129 ps
CPU time 1159.86 seconds
Started Aug 16 06:08:17 PM PDT 24
Finished Aug 16 06:27:38 PM PDT 24
Peak memory 518492 kb
Host smart-820d6e5d-3cd3-4c7b-b823-1931524dd076
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3863676532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.3863676532 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_stress_all/latest

Test location /workspace/coverage/default/26.kmac_alert_test.3438244330
Short name T242
Test name
Test status
Simulation time 50741360 ps
CPU time 0.85 seconds
Started Aug 16 06:08:15 PM PDT 24
Finished Aug 16 06:08:16 PM PDT 24
Peak memory 218276 kb
Host smart-0487b924-7d16-4a69-aee2-4cb4ce9cdf0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438244330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.3438244330 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_alert_test/latest

Test location /workspace/coverage/default/26.kmac_app.1765398452
Short name T619
Test name
Test status
Simulation time 9836099681 ps
CPU time 311.23 seconds
Started Aug 16 06:08:15 PM PDT 24
Finished Aug 16 06:13:26 PM PDT 24
Peak memory 440380 kb
Host smart-27cbee94-8ef0-4fb5-b5a6-17a6f0ad9f1a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765398452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.1765398452 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/26.kmac_app/latest

Test location /workspace/coverage/default/26.kmac_burst_write.3797885842
Short name T149
Test name
Test status
Simulation time 9726867382 ps
CPU time 523.11 seconds
Started Aug 16 06:08:15 PM PDT 24
Finished Aug 16 06:16:58 PM PDT 24
Peak memory 243380 kb
Host smart-529c69f5-4f16-4197-95ed-0e5dfefb4806
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797885842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.379788584
2 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_burst_write/latest

Test location /workspace/coverage/default/26.kmac_entropy_refresh.57485338
Short name T75
Test name
Test status
Simulation time 6264370622 ps
CPU time 41.12 seconds
Started Aug 16 06:08:15 PM PDT 24
Finished Aug 16 06:08:56 PM PDT 24
Peak memory 233312 kb
Host smart-0957b88b-f6ad-466d-be4b-b8b4f0f8004c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57485338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.574
85338 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/26.kmac_error.3209590820
Short name T454
Test name
Test status
Simulation time 15513027996 ps
CPU time 582.69 seconds
Started Aug 16 06:08:20 PM PDT 24
Finished Aug 16 06:18:03 PM PDT 24
Peak memory 636136 kb
Host smart-bacd7a9b-7da4-4d0e-80dc-7e2709f300e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209590820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.3209590820 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_error/latest

Test location /workspace/coverage/default/26.kmac_key_error.2000496939
Short name T101
Test name
Test status
Simulation time 2671505386 ps
CPU time 10.26 seconds
Started Aug 16 06:08:16 PM PDT 24
Finished Aug 16 06:08:26 PM PDT 24
Peak memory 226492 kb
Host smart-47071a70-685e-4be4-8fe8-09af7d561a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000496939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.2000496939 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_key_error/latest

Test location /workspace/coverage/default/26.kmac_lc_escalation.1906090308
Short name T46
Test name
Test status
Simulation time 61156406 ps
CPU time 1.4 seconds
Started Aug 16 06:08:12 PM PDT 24
Finished Aug 16 06:08:13 PM PDT 24
Peak memory 226724 kb
Host smart-96b8905f-cc71-44e8-86e4-08593d262803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906090308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.1906090308 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/26.kmac_lc_escalation/latest

Test location /workspace/coverage/default/26.kmac_long_msg_and_output.3640603266
Short name T233
Test name
Test status
Simulation time 11965316997 ps
CPU time 357.65 seconds
Started Aug 16 06:08:12 PM PDT 24
Finished Aug 16 06:14:10 PM PDT 24
Peak memory 673844 kb
Host smart-f8e74180-9b7e-4cd2-8679-f3a7b58ed6d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640603266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_a
nd_output.3640603266 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/26.kmac_sideload.372455807
Short name T479
Test name
Test status
Simulation time 17207021364 ps
CPU time 466.52 seconds
Started Aug 16 06:08:14 PM PDT 24
Finished Aug 16 06:16:00 PM PDT 24
Peak memory 576360 kb
Host smart-8c6efa53-6d4b-4a26-86ef-a41ff0689a86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372455807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.372455807 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_sideload/latest

Test location /workspace/coverage/default/26.kmac_smoke.1510061796
Short name T435
Test name
Test status
Simulation time 1413169852 ps
CPU time 3.64 seconds
Started Aug 16 06:08:19 PM PDT 24
Finished Aug 16 06:08:23 PM PDT 24
Peak memory 226580 kb
Host smart-553f3429-843c-40da-bd21-d8d73642dfdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510061796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.1510061796 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_smoke/latest

Test location /workspace/coverage/default/26.kmac_stress_all.1538499245
Short name T16
Test name
Test status
Simulation time 13299175346 ps
CPU time 409.14 seconds
Started Aug 16 06:08:20 PM PDT 24
Finished Aug 16 06:15:09 PM PDT 24
Peak memory 347832 kb
Host smart-57949673-834e-45aa-b783-a605b89b238b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1538499245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.1538499245 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all/latest

Test location /workspace/coverage/default/27.kmac_alert_test.2254219318
Short name T350
Test name
Test status
Simulation time 15692211 ps
CPU time 0.83 seconds
Started Aug 16 06:08:14 PM PDT 24
Finished Aug 16 06:08:15 PM PDT 24
Peak memory 218240 kb
Host smart-c5c37f02-909f-4eb6-87b7-5c49b3318ede
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254219318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.2254219318 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_alert_test/latest

Test location /workspace/coverage/default/27.kmac_app.2853473395
Short name T673
Test name
Test status
Simulation time 5700607688 ps
CPU time 279.37 seconds
Started Aug 16 06:08:12 PM PDT 24
Finished Aug 16 06:12:52 PM PDT 24
Peak memory 311560 kb
Host smart-463a8799-6bdf-4555-b3f4-e5df8be3b3cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853473395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.2853473395 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/27.kmac_app/latest

Test location /workspace/coverage/default/27.kmac_burst_write.1066444298
Short name T606
Test name
Test status
Simulation time 59783367815 ps
CPU time 1455.33 seconds
Started Aug 16 06:08:20 PM PDT 24
Finished Aug 16 06:32:35 PM PDT 24
Peak memory 264152 kb
Host smart-9b70361e-000a-4d16-8583-1af3aafd8c95
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066444298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.106644429
8 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_burst_write/latest

Test location /workspace/coverage/default/27.kmac_entropy_refresh.2023593768
Short name T557
Test name
Test status
Simulation time 910962594 ps
CPU time 5.93 seconds
Started Aug 16 06:08:15 PM PDT 24
Finished Aug 16 06:08:21 PM PDT 24
Peak memory 225904 kb
Host smart-992e2ecb-e491-40ae-bac2-28b4b711ca25
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023593768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.2
023593768 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/27.kmac_error.3767423403
Short name T644
Test name
Test status
Simulation time 4987688973 ps
CPU time 138.13 seconds
Started Aug 16 06:08:15 PM PDT 24
Finished Aug 16 06:10:33 PM PDT 24
Peak memory 336860 kb
Host smart-e7ed960d-beb9-44e1-9e53-a60bf13d99f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767423403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.3767423403 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_error/latest

Test location /workspace/coverage/default/27.kmac_key_error.1792643121
Short name T244
Test name
Test status
Simulation time 2426950001 ps
CPU time 9.96 seconds
Started Aug 16 06:08:16 PM PDT 24
Finished Aug 16 06:08:26 PM PDT 24
Peak memory 226616 kb
Host smart-540ea04f-4e0c-4d15-907f-9f672c6c14a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792643121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.1792643121 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_key_error/latest

Test location /workspace/coverage/default/27.kmac_lc_escalation.1480954570
Short name T324
Test name
Test status
Simulation time 47654776 ps
CPU time 1.41 seconds
Started Aug 16 06:08:14 PM PDT 24
Finished Aug 16 06:08:16 PM PDT 24
Peak memory 226628 kb
Host smart-9e48fa77-dfe9-4e29-9549-46bfe7d606ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480954570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.1480954570 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/27.kmac_lc_escalation/latest

Test location /workspace/coverage/default/27.kmac_long_msg_and_output.3485183568
Short name T104
Test name
Test status
Simulation time 13074351683 ps
CPU time 1539.43 seconds
Started Aug 16 06:08:16 PM PDT 24
Finished Aug 16 06:33:56 PM PDT 24
Peak memory 957632 kb
Host smart-92005625-d1dc-4db5-9781-3a43e260ba94
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485183568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_a
nd_output.3485183568 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/27.kmac_sideload.1212355905
Short name T109
Test name
Test status
Simulation time 3002032983 ps
CPU time 133.75 seconds
Started Aug 16 06:08:17 PM PDT 24
Finished Aug 16 06:10:31 PM PDT 24
Peak memory 274520 kb
Host smart-4dcd67e4-1bb0-4eba-934c-4ce31c51417d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212355905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.1212355905 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_sideload/latest

Test location /workspace/coverage/default/27.kmac_smoke.3257433089
Short name T207
Test name
Test status
Simulation time 496378897 ps
CPU time 6.29 seconds
Started Aug 16 06:08:13 PM PDT 24
Finished Aug 16 06:08:19 PM PDT 24
Peak memory 226668 kb
Host smart-5ceb7e08-a766-40b1-9c32-20468987c293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257433089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.3257433089 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_smoke/latest

Test location /workspace/coverage/default/27.kmac_stress_all.4107406220
Short name T657
Test name
Test status
Simulation time 8272927661 ps
CPU time 620.49 seconds
Started Aug 16 06:08:19 PM PDT 24
Finished Aug 16 06:18:40 PM PDT 24
Peak memory 312804 kb
Host smart-8f246c56-d947-44af-bd7e-e508b7cad597
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4107406220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.4107406220 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_stress_all/latest

Test location /workspace/coverage/default/28.kmac_alert_test.368798488
Short name T464
Test name
Test status
Simulation time 246038395 ps
CPU time 0.89 seconds
Started Aug 16 06:08:28 PM PDT 24
Finished Aug 16 06:08:29 PM PDT 24
Peak memory 218168 kb
Host smart-573d75c4-dfa5-4e00-965d-2cf5e57461f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368798488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.368798488 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/28.kmac_alert_test/latest

Test location /workspace/coverage/default/28.kmac_app.3750821105
Short name T318
Test name
Test status
Simulation time 2599366146 ps
CPU time 70.98 seconds
Started Aug 16 06:08:16 PM PDT 24
Finished Aug 16 06:09:27 PM PDT 24
Peak memory 269720 kb
Host smart-ee675373-ee10-4a03-9c3b-78106eb2d36b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750821105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.3750821105 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/28.kmac_app/latest

Test location /workspace/coverage/default/28.kmac_burst_write.1550801316
Short name T539
Test name
Test status
Simulation time 26052033364 ps
CPU time 721.1 seconds
Started Aug 16 06:08:14 PM PDT 24
Finished Aug 16 06:20:15 PM PDT 24
Peak memory 245004 kb
Host smart-94cd959e-4002-4285-90f3-6f4fa98ec06a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550801316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.155080131
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_burst_write/latest

Test location /workspace/coverage/default/28.kmac_entropy_refresh.1739442968
Short name T391
Test name
Test status
Simulation time 48663343648 ps
CPU time 330.58 seconds
Started Aug 16 06:08:17 PM PDT 24
Finished Aug 16 06:13:48 PM PDT 24
Peak memory 452008 kb
Host smart-9088f8f5-e44a-4937-9a5a-4c18e0530246
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739442968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.1
739442968 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/28.kmac_error.91328557
Short name T25
Test name
Test status
Simulation time 17844919119 ps
CPU time 157.98 seconds
Started Aug 16 06:08:12 PM PDT 24
Finished Aug 16 06:10:50 PM PDT 24
Peak memory 341320 kb
Host smart-8788209e-5259-4767-9307-af8e68f9e6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91328557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.91328557 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_error/latest

Test location /workspace/coverage/default/28.kmac_key_error.2999656352
Short name T531
Test name
Test status
Simulation time 5236155655 ps
CPU time 9.75 seconds
Started Aug 16 06:08:23 PM PDT 24
Finished Aug 16 06:08:32 PM PDT 24
Peak memory 226600 kb
Host smart-e7702082-df7c-42c7-97e4-45a046f16a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999656352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.2999656352 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_key_error/latest

Test location /workspace/coverage/default/28.kmac_lc_escalation.626141210
Short name T53
Test name
Test status
Simulation time 1539224381 ps
CPU time 20.22 seconds
Started Aug 16 06:08:20 PM PDT 24
Finished Aug 16 06:08:40 PM PDT 24
Peak memory 243308 kb
Host smart-352c7d3f-e316-4780-9b6e-aa92c9537faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626141210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.626141210 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/28.kmac_lc_escalation/latest

Test location /workspace/coverage/default/28.kmac_long_msg_and_output.3829575163
Short name T254
Test name
Test status
Simulation time 59503823586 ps
CPU time 1849.39 seconds
Started Aug 16 06:08:19 PM PDT 24
Finished Aug 16 06:39:09 PM PDT 24
Peak memory 1069740 kb
Host smart-e9e6b578-2489-4bf3-8781-d299bafde861
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829575163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_a
nd_output.3829575163 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/28.kmac_sideload.925171850
Short name T683
Test name
Test status
Simulation time 214139317 ps
CPU time 5.91 seconds
Started Aug 16 06:08:15 PM PDT 24
Finished Aug 16 06:08:21 PM PDT 24
Peak memory 234816 kb
Host smart-c62b5897-5663-490a-8383-5fc39da7e8ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925171850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.925171850 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_sideload/latest

Test location /workspace/coverage/default/28.kmac_smoke.1200776591
Short name T39
Test name
Test status
Simulation time 5008919001 ps
CPU time 34.08 seconds
Started Aug 16 06:08:16 PM PDT 24
Finished Aug 16 06:08:50 PM PDT 24
Peak memory 226880 kb
Host smart-c9794f8b-360b-4732-af91-8e68cc43f362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200776591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.1200776591 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_smoke/latest

Test location /workspace/coverage/default/28.kmac_stress_all.1416651850
Short name T610
Test name
Test status
Simulation time 40425738279 ps
CPU time 1227.38 seconds
Started Aug 16 06:08:22 PM PDT 24
Finished Aug 16 06:28:50 PM PDT 24
Peak memory 895476 kb
Host smart-19458e86-6602-494f-9205-4d4991f051ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1416651850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.1416651850 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_stress_all/latest

Test location /workspace/coverage/default/29.kmac_alert_test.3794118562
Short name T288
Test name
Test status
Simulation time 12944670 ps
CPU time 0.86 seconds
Started Aug 16 06:08:33 PM PDT 24
Finished Aug 16 06:08:34 PM PDT 24
Peak memory 218228 kb
Host smart-cd53f772-b9c9-45f5-b7b2-2d78b248b2c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794118562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.3794118562 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_alert_test/latest

Test location /workspace/coverage/default/29.kmac_app.1169618665
Short name T196
Test name
Test status
Simulation time 3508021878 ps
CPU time 121.42 seconds
Started Aug 16 06:08:28 PM PDT 24
Finished Aug 16 06:10:30 PM PDT 24
Peak memory 305484 kb
Host smart-54356355-23ab-40a0-b2e2-739c236220db
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169618665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.1169618665 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/29.kmac_app/latest

Test location /workspace/coverage/default/29.kmac_burst_write.273585324
Short name T452
Test name
Test status
Simulation time 102833558732 ps
CPU time 1161.38 seconds
Started Aug 16 06:08:27 PM PDT 24
Finished Aug 16 06:27:48 PM PDT 24
Peak memory 255932 kb
Host smart-5484af07-df2a-4454-b68b-0e968a65311b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273585324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.273585324
+enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_burst_write/latest

Test location /workspace/coverage/default/29.kmac_entropy_refresh.3608062625
Short name T172
Test name
Test status
Simulation time 27563128532 ps
CPU time 265.67 seconds
Started Aug 16 06:08:24 PM PDT 24
Finished Aug 16 06:12:49 PM PDT 24
Peak memory 296276 kb
Host smart-b67fef31-e2c6-47fc-92b0-f2af3da40ca8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608062625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.3
608062625 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/29.kmac_error.3871873864
Short name T669
Test name
Test status
Simulation time 10248237706 ps
CPU time 346 seconds
Started Aug 16 06:08:24 PM PDT 24
Finished Aug 16 06:14:10 PM PDT 24
Peak memory 500272 kb
Host smart-39cf081b-85dd-4d92-a8e5-34463da38ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871873864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.3871873864 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_error/latest

Test location /workspace/coverage/default/29.kmac_key_error.767825299
Short name T536
Test name
Test status
Simulation time 1906099757 ps
CPU time 9.32 seconds
Started Aug 16 06:08:21 PM PDT 24
Finished Aug 16 06:08:31 PM PDT 24
Peak memory 226520 kb
Host smart-5ee1974e-3f1e-44e2-9cbc-2b6aec2e4241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767825299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.767825299 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_key_error/latest

Test location /workspace/coverage/default/29.kmac_lc_escalation.2637912876
Short name T35
Test name
Test status
Simulation time 26518606 ps
CPU time 1.41 seconds
Started Aug 16 06:08:33 PM PDT 24
Finished Aug 16 06:08:34 PM PDT 24
Peak memory 226508 kb
Host smart-60282e2f-cc02-4b9c-be97-5f8de0af7e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637912876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.2637912876 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/29.kmac_lc_escalation/latest

Test location /workspace/coverage/default/29.kmac_long_msg_and_output.2770946428
Short name T330
Test name
Test status
Simulation time 348444879733 ps
CPU time 5179.21 seconds
Started Aug 16 06:08:28 PM PDT 24
Finished Aug 16 07:34:48 PM PDT 24
Peak memory 3635704 kb
Host smart-e332c047-dec5-437b-943b-fa7737c4d2ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770946428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a
nd_output.2770946428 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/29.kmac_sideload.4179265491
Short name T585
Test name
Test status
Simulation time 3117873045 ps
CPU time 225.44 seconds
Started Aug 16 06:08:23 PM PDT 24
Finished Aug 16 06:12:09 PM PDT 24
Peak memory 308596 kb
Host smart-8583e069-7762-4ef0-a4e4-04868ad619bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179265491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.4179265491 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_sideload/latest

Test location /workspace/coverage/default/29.kmac_smoke.400720697
Short name T651
Test name
Test status
Simulation time 979311776 ps
CPU time 19.77 seconds
Started Aug 16 06:08:25 PM PDT 24
Finished Aug 16 06:08:45 PM PDT 24
Peak memory 226624 kb
Host smart-e8078d1d-60eb-4faf-b5c0-3e95bea92b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400720697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.400720697 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_smoke/latest

Test location /workspace/coverage/default/29.kmac_stress_all.3909471157
Short name T390
Test name
Test status
Simulation time 59198595124 ps
CPU time 360.75 seconds
Started Aug 16 06:08:32 PM PDT 24
Finished Aug 16 06:14:33 PM PDT 24
Peak memory 353912 kb
Host smart-e5c48176-ffe9-4f11-8942-c0fb09b9ed96
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3909471157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.3909471157 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_stress_all/latest

Test location /workspace/coverage/default/3.kmac_alert_test.4294787829
Short name T271
Test name
Test status
Simulation time 18875923 ps
CPU time 0.92 seconds
Started Aug 16 06:06:11 PM PDT 24
Finished Aug 16 06:06:12 PM PDT 24
Peak memory 218172 kb
Host smart-f9d34ab9-db72-4eb5-bf4a-7212ec58b504
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294787829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.4294787829 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_alert_test/latest

Test location /workspace/coverage/default/3.kmac_app.2650144256
Short name T622
Test name
Test status
Simulation time 6789370064 ps
CPU time 85.39 seconds
Started Aug 16 06:06:00 PM PDT 24
Finished Aug 16 06:07:25 PM PDT 24
Peak memory 249760 kb
Host smart-bf4cdcd5-e46e-440a-bf5e-aa093a2a1ced
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650144256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.2650144256 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/3.kmac_app/latest

Test location /workspace/coverage/default/3.kmac_app_with_partial_data.484904365
Short name T620
Test name
Test status
Simulation time 62491675970 ps
CPU time 328.2 seconds
Started Aug 16 06:06:03 PM PDT 24
Finished Aug 16 06:11:32 PM PDT 24
Peak memory 323096 kb
Host smart-5b90a75f-a680-423a-a7d4-cd83a3025979
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484904365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_parti
al_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_part
ial_data.484904365 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/3.kmac_burst_write.4165667604
Short name T319
Test name
Test status
Simulation time 74510932942 ps
CPU time 452.65 seconds
Started Aug 16 06:06:04 PM PDT 24
Finished Aug 16 06:13:37 PM PDT 24
Peak memory 243204 kb
Host smart-e7829605-6536-47e6-b247-39f050d18ff2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165667604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.4165667604
+enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_burst_write/latest

Test location /workspace/coverage/default/3.kmac_edn_timeout_error.880695709
Short name T340
Test name
Test status
Simulation time 2096626033 ps
CPU time 33.32 seconds
Started Aug 16 06:06:10 PM PDT 24
Finished Aug 16 06:06:44 PM PDT 24
Peak memory 235064 kb
Host smart-566cfd74-04a0-45a2-886b-07f037e1f6a3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=880695709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.880695709 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_mode_error.3484897950
Short name T399
Test name
Test status
Simulation time 34917878 ps
CPU time 1.13 seconds
Started Aug 16 06:06:10 PM PDT 24
Finished Aug 16 06:06:11 PM PDT 24
Peak memory 218220 kb
Host smart-43f118c1-94b1-4d1e-977e-9fc5de449602
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3484897950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.3484897950 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_ready_error.1187341365
Short name T9
Test name
Test status
Simulation time 10610792967 ps
CPU time 32.31 seconds
Started Aug 16 06:06:07 PM PDT 24
Finished Aug 16 06:06:40 PM PDT 24
Peak memory 226948 kb
Host smart-4678db2f-e075-4d12-828a-4e2d6ee95ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187341365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.1187341365 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_refresh.3771381961
Short name T480
Test name
Test status
Simulation time 7658238881 ps
CPU time 326.21 seconds
Started Aug 16 06:05:57 PM PDT 24
Finished Aug 16 06:11:23 PM PDT 24
Peak memory 323984 kb
Host smart-c755ada8-66ee-4f58-a8e9-b86b08f1e4c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771381961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.37
71381961 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/3.kmac_error.532985290
Short name T27
Test name
Test status
Simulation time 10356126656 ps
CPU time 192.32 seconds
Started Aug 16 06:05:59 PM PDT 24
Finished Aug 16 06:09:12 PM PDT 24
Peak memory 360480 kb
Host smart-5e1cde13-5d69-41da-9ab1-e97043e45383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532985290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.532985290 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_error/latest

Test location /workspace/coverage/default/3.kmac_key_error.1681299911
Short name T576
Test name
Test status
Simulation time 1232216871 ps
CPU time 2.86 seconds
Started Aug 16 06:06:05 PM PDT 24
Finished Aug 16 06:06:08 PM PDT 24
Peak memory 226372 kb
Host smart-31d236b9-9c1d-4de6-b254-3f86be278e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681299911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.1681299911 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_key_error/latest

Test location /workspace/coverage/default/3.kmac_lc_escalation.2473277585
Short name T594
Test name
Test status
Simulation time 53620474 ps
CPU time 1.49 seconds
Started Aug 16 06:06:08 PM PDT 24
Finished Aug 16 06:06:09 PM PDT 24
Peak memory 226556 kb
Host smart-622173b1-2747-4787-965b-61f4d8979e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473277585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.2473277585 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/3.kmac_lc_escalation/latest

Test location /workspace/coverage/default/3.kmac_mubi.2909049260
Short name T614
Test name
Test status
Simulation time 12922010966 ps
CPU time 169.42 seconds
Started Aug 16 06:05:58 PM PDT 24
Finished Aug 16 06:08:48 PM PDT 24
Peak memory 343576 kb
Host smart-ede1dc16-3a5b-4570-8ab7-9733ef8a774a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909049260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.2909049260 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mubi/latest

Test location /workspace/coverage/default/3.kmac_sideload.3104164315
Short name T401
Test name
Test status
Simulation time 21915793027 ps
CPU time 498.69 seconds
Started Aug 16 06:06:03 PM PDT 24
Finished Aug 16 06:14:22 PM PDT 24
Peak memory 382840 kb
Host smart-18e8ac8d-0474-4387-a596-04a63b01f231
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104164315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.3104164315 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_sideload/latest

Test location /workspace/coverage/default/3.kmac_smoke.2823014325
Short name T550
Test name
Test status
Simulation time 7144730428 ps
CPU time 74.49 seconds
Started Aug 16 06:05:58 PM PDT 24
Finished Aug 16 06:07:13 PM PDT 24
Peak memory 226764 kb
Host smart-225e12b4-b1f1-463b-aac8-3e1527695641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823014325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.2823014325 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_smoke/latest

Test location /workspace/coverage/default/3.kmac_stress_all.975011267
Short name T441
Test name
Test status
Simulation time 30411026055 ps
CPU time 1273.26 seconds
Started Aug 16 06:06:09 PM PDT 24
Finished Aug 16 06:27:22 PM PDT 24
Peak memory 1077720 kb
Host smart-9ce4471c-ba52-4caf-918f-c4b4abeb576b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=975011267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.975011267 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac.1373620731
Short name T409
Test name
Test status
Simulation time 188512896 ps
CPU time 3.29 seconds
Started Aug 16 06:05:59 PM PDT 24
Finished Aug 16 06:06:03 PM PDT 24
Peak memory 219612 kb
Host smart-edb13c96-7b32-41b8-9e0a-0dad5d46ffe8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373620731 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.kmac_test_vectors_kmac.1373620731 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac_xof.4141883131
Short name T376
Test name
Test status
Simulation time 91219129 ps
CPU time 2.68 seconds
Started Aug 16 06:06:00 PM PDT 24
Finished Aug 16 06:06:03 PM PDT 24
Peak memory 219600 kb
Host smart-34baee6f-02e8-431b-a019-60d34af2b821
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141883131 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.kmac_test_vectors_kmac_xof.4141883131 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_224.472828580
Short name T540
Test name
Test status
Simulation time 96695589685 ps
CPU time 3706.31 seconds
Started Aug 16 06:06:05 PM PDT 24
Finished Aug 16 07:07:51 PM PDT 24
Peak memory 3170820 kb
Host smart-03079b67-aa15-46d7-8598-9130cf727437
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=472828580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.472828580 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_256.153353857
Short name T356
Test name
Test status
Simulation time 10546306010 ps
CPU time 38.86 seconds
Started Aug 16 06:05:59 PM PDT 24
Finished Aug 16 06:06:38 PM PDT 24
Peak memory 224836 kb
Host smart-a03e285a-fa83-4b46-b2f3-34ca35bb3317
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=153353857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.153353857 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_384.3293157783
Short name T371
Test name
Test status
Simulation time 6631772439 ps
CPU time 30.81 seconds
Started Aug 16 06:06:05 PM PDT 24
Finished Aug 16 06:06:36 PM PDT 24
Peak memory 235120 kb
Host smart-1b1ef41d-ad7a-4af6-a14d-38b085fc4a07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3293157783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.3293157783 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_512.2567043957
Short name T519
Test name
Test status
Simulation time 190589389476 ps
CPU time 1312.91 seconds
Started Aug 16 06:05:59 PM PDT 24
Finished Aug 16 06:27:53 PM PDT 24
Peak memory 704092 kb
Host smart-a75b255f-a3b1-4af4-9346-31c8a7fade01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2567043957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.2567043957 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_128.96027232
Short name T238
Test name
Test status
Simulation time 250156048363 ps
CPU time 355.51 seconds
Started Aug 16 06:05:58 PM PDT 24
Finished Aug 16 06:11:54 PM PDT 24
Peak memory 276124 kb
Host smart-792f3da5-4a83-48c7-9e48-fa432c336053
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=96027232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.96027232 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_256.2157979080
Short name T195
Test name
Test status
Simulation time 65949291572 ps
CPU time 1938.33 seconds
Started Aug 16 06:06:05 PM PDT 24
Finished Aug 16 06:38:24 PM PDT 24
Peak memory 1087880 kb
Host smart-f7a2a3e3-4747-4839-ad38-c5a0064c71c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2157979080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.2157979080 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/30.kmac_alert_test.20716091
Short name T225
Test name
Test status
Simulation time 25809679 ps
CPU time 0.84 seconds
Started Aug 16 06:08:34 PM PDT 24
Finished Aug 16 06:08:35 PM PDT 24
Peak memory 218180 kb
Host smart-8536529a-7895-4398-a20e-db3aa8d20726
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20716091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.20716091 +enable_mas
king=1 +sw_key_masked=0
Directory /workspace/30.kmac_alert_test/latest

Test location /workspace/coverage/default/30.kmac_app.169474603
Short name T386
Test name
Test status
Simulation time 306745371 ps
CPU time 1.9 seconds
Started Aug 16 06:08:29 PM PDT 24
Finished Aug 16 06:08:31 PM PDT 24
Peak memory 226448 kb
Host smart-3fa8d010-8aba-4594-91bc-b3f6a0ece1ce
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169474603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.169474603 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/30.kmac_app/latest

Test location /workspace/coverage/default/30.kmac_burst_write.74848214
Short name T488
Test name
Test status
Simulation time 8541137188 ps
CPU time 915.03 seconds
Started Aug 16 06:08:30 PM PDT 24
Finished Aug 16 06:23:45 PM PDT 24
Peak memory 243188 kb
Host smart-c4e2215b-3c77-4c83-99cb-96800ee3b3cf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74848214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.74848214 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_burst_write/latest

Test location /workspace/coverage/default/30.kmac_entropy_refresh.3228290553
Short name T274
Test name
Test status
Simulation time 8610263422 ps
CPU time 173.43 seconds
Started Aug 16 06:08:34 PM PDT 24
Finished Aug 16 06:11:28 PM PDT 24
Peak memory 354340 kb
Host smart-72dbd33e-d279-436b-9565-2f619d51b4bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228290553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.3
228290553 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/30.kmac_error.1834146062
Short name T548
Test name
Test status
Simulation time 13442064236 ps
CPU time 232.34 seconds
Started Aug 16 06:08:30 PM PDT 24
Finished Aug 16 06:12:23 PM PDT 24
Peak memory 400416 kb
Host smart-5a2ad420-0276-4762-a2a0-e5a0242350fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834146062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.1834146062 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_error/latest

Test location /workspace/coverage/default/30.kmac_key_error.140680512
Short name T102
Test name
Test status
Simulation time 726085796 ps
CPU time 3.35 seconds
Started Aug 16 06:08:31 PM PDT 24
Finished Aug 16 06:08:34 PM PDT 24
Peak memory 226580 kb
Host smart-7b570722-62eb-4b5b-8408-e7867111f2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140680512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.140680512 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_key_error/latest

Test location /workspace/coverage/default/30.kmac_lc_escalation.2296343242
Short name T645
Test name
Test status
Simulation time 56740821 ps
CPU time 1.51 seconds
Started Aug 16 06:08:29 PM PDT 24
Finished Aug 16 06:08:31 PM PDT 24
Peak memory 226560 kb
Host smart-ead0a1fb-248b-4a5c-9f8c-36b30a179fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296343242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.2296343242 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/30.kmac_lc_escalation/latest

Test location /workspace/coverage/default/30.kmac_long_msg_and_output.689341466
Short name T613
Test name
Test status
Simulation time 39074092447 ps
CPU time 406.48 seconds
Started Aug 16 06:08:32 PM PDT 24
Finished Aug 16 06:15:19 PM PDT 24
Peak memory 426392 kb
Host smart-928c67a2-cba0-4ab3-974c-f1c88e1b29f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689341466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_an
d_output.689341466 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/30.kmac_sideload.3183438705
Short name T578
Test name
Test status
Simulation time 9680290752 ps
CPU time 96.2 seconds
Started Aug 16 06:08:32 PM PDT 24
Finished Aug 16 06:10:09 PM PDT 24
Peak memory 257552 kb
Host smart-47c7b97b-d4e8-4610-b0b0-a75b4fa03075
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183438705 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.3183438705 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_sideload/latest

Test location /workspace/coverage/default/30.kmac_smoke.3253944842
Short name T493
Test name
Test status
Simulation time 1657105154 ps
CPU time 56.37 seconds
Started Aug 16 06:08:32 PM PDT 24
Finished Aug 16 06:09:28 PM PDT 24
Peak memory 226644 kb
Host smart-427b0ecf-6994-4e75-8200-d8e5265ac3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253944842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.3253944842 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_smoke/latest

Test location /workspace/coverage/default/30.kmac_stress_all.63722356
Short name T468
Test name
Test status
Simulation time 90961601917 ps
CPU time 246.82 seconds
Started Aug 16 06:08:34 PM PDT 24
Finished Aug 16 06:12:41 PM PDT 24
Peak memory 407760 kb
Host smart-d21f5d3d-5dfe-4f31-af66-77998e71f473
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=63722356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.63722356 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all/latest

Test location /workspace/coverage/default/31.kmac_alert_test.2435137329
Short name T470
Test name
Test status
Simulation time 46243628 ps
CPU time 0.88 seconds
Started Aug 16 06:08:41 PM PDT 24
Finished Aug 16 06:08:43 PM PDT 24
Peak memory 218280 kb
Host smart-591c4064-d7e4-4098-9cc5-098b4e93fa48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435137329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.2435137329 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_alert_test/latest

Test location /workspace/coverage/default/31.kmac_app.289763371
Short name T96
Test name
Test status
Simulation time 14452799279 ps
CPU time 279.44 seconds
Started Aug 16 06:08:38 PM PDT 24
Finished Aug 16 06:13:18 PM PDT 24
Peak memory 307244 kb
Host smart-cd18614a-f7ec-4160-8e58-9b7de900aa36
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289763371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.289763371 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/31.kmac_app/latest

Test location /workspace/coverage/default/31.kmac_burst_write.834441232
Short name T515
Test name
Test status
Simulation time 123955630600 ps
CPU time 1560.42 seconds
Started Aug 16 06:08:41 PM PDT 24
Finished Aug 16 06:34:42 PM PDT 24
Peak memory 264416 kb
Host smart-fd2596b9-3944-4889-97e5-56e16c4cc8b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834441232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.834441232
+enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_burst_write/latest

Test location /workspace/coverage/default/31.kmac_entropy_refresh.614837503
Short name T42
Test name
Test status
Simulation time 19628624777 ps
CPU time 411.92 seconds
Started Aug 16 06:08:42 PM PDT 24
Finished Aug 16 06:15:34 PM PDT 24
Peak memory 507492 kb
Host smart-ac783cf9-4073-4e2a-bbbd-246eada97fe5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614837503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.61
4837503 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/31.kmac_error.3774141221
Short name T305
Test name
Test status
Simulation time 30020340987 ps
CPU time 403.78 seconds
Started Aug 16 06:08:39 PM PDT 24
Finished Aug 16 06:15:23 PM PDT 24
Peak memory 526408 kb
Host smart-080b1bb0-f69e-400c-a18c-c857b0ae7524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774141221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.3774141221 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_error/latest

Test location /workspace/coverage/default/31.kmac_key_error.62905174
Short name T687
Test name
Test status
Simulation time 13262729677 ps
CPU time 11.64 seconds
Started Aug 16 06:08:41 PM PDT 24
Finished Aug 16 06:08:52 PM PDT 24
Peak memory 226632 kb
Host smart-d90c77e9-badb-423a-9fd9-61b4cf60cafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62905174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.62905174 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_key_error/latest

Test location /workspace/coverage/default/31.kmac_lc_escalation.1477072657
Short name T477
Test name
Test status
Simulation time 126742288 ps
CPU time 1.79 seconds
Started Aug 16 06:08:36 PM PDT 24
Finished Aug 16 06:08:38 PM PDT 24
Peak memory 226692 kb
Host smart-53aee75a-92f9-45d4-89c4-f7b537b9acb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477072657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.1477072657 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/31.kmac_lc_escalation/latest

Test location /workspace/coverage/default/31.kmac_long_msg_and_output.1668102503
Short name T208
Test name
Test status
Simulation time 41564217932 ps
CPU time 2637.99 seconds
Started Aug 16 06:08:41 PM PDT 24
Finished Aug 16 06:52:40 PM PDT 24
Peak memory 1509512 kb
Host smart-80b20b07-2e3a-4038-9f70-18879ee79bf8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668102503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_a
nd_output.1668102503 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/31.kmac_sideload.822988465
Short name T569
Test name
Test status
Simulation time 50697819299 ps
CPU time 309.22 seconds
Started Aug 16 06:08:45 PM PDT 24
Finished Aug 16 06:13:54 PM PDT 24
Peak memory 468160 kb
Host smart-49c610a9-3dc5-46dd-87a9-6dff2da97e9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822988465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.822988465 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_sideload/latest

Test location /workspace/coverage/default/31.kmac_smoke.1461232216
Short name T214
Test name
Test status
Simulation time 566064477 ps
CPU time 10.61 seconds
Started Aug 16 06:08:41 PM PDT 24
Finished Aug 16 06:08:52 PM PDT 24
Peak memory 226524 kb
Host smart-1e09c507-23c1-48fc-b49a-f57055b4241d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461232216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.1461232216 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_smoke/latest

Test location /workspace/coverage/default/31.kmac_stress_all.4112773108
Short name T692
Test name
Test status
Simulation time 129324886709 ps
CPU time 1006.11 seconds
Started Aug 16 06:08:39 PM PDT 24
Finished Aug 16 06:25:25 PM PDT 24
Peak memory 974600 kb
Host smart-1f6c1729-ba6a-4dda-82b4-d8a532f811ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4112773108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.4112773108 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_stress_all/latest

Test location /workspace/coverage/default/32.kmac_alert_test.3417140441
Short name T99
Test name
Test status
Simulation time 42579998 ps
CPU time 0.83 seconds
Started Aug 16 06:08:38 PM PDT 24
Finished Aug 16 06:08:39 PM PDT 24
Peak memory 218268 kb
Host smart-e6f57c0a-ac81-4d67-bf1e-f3ce66110f80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417140441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.3417140441 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_alert_test/latest

Test location /workspace/coverage/default/32.kmac_app.890502043
Short name T682
Test name
Test status
Simulation time 49838521065 ps
CPU time 336.97 seconds
Started Aug 16 06:08:42 PM PDT 24
Finished Aug 16 06:14:20 PM PDT 24
Peak memory 457372 kb
Host smart-4d245fff-bfef-4383-a046-d2e7d5fc50cb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890502043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.890502043 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/32.kmac_app/latest

Test location /workspace/coverage/default/32.kmac_burst_write.1855349350
Short name T222
Test name
Test status
Simulation time 139084315565 ps
CPU time 1644.94 seconds
Started Aug 16 06:08:41 PM PDT 24
Finished Aug 16 06:36:07 PM PDT 24
Peak memory 266860 kb
Host smart-2ed3d589-cbd9-4a6a-b850-648a99e117c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855349350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.185534935
0 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_burst_write/latest

Test location /workspace/coverage/default/32.kmac_entropy_refresh.12419674
Short name T588
Test name
Test status
Simulation time 5683701415 ps
CPU time 64.31 seconds
Started Aug 16 06:08:43 PM PDT 24
Finished Aug 16 06:09:47 PM PDT 24
Peak memory 244640 kb
Host smart-9c7fde98-7487-4a07-a216-bedff245b67e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12419674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.124
19674 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/32.kmac_error.1731788517
Short name T322
Test name
Test status
Simulation time 30058994046 ps
CPU time 293.57 seconds
Started Aug 16 06:08:37 PM PDT 24
Finished Aug 16 06:13:31 PM PDT 24
Peak memory 442264 kb
Host smart-4b9a7e19-ddf1-4841-a266-1687c0c30489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731788517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.1731788517 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_error/latest

Test location /workspace/coverage/default/32.kmac_key_error.3614113249
Short name T257
Test name
Test status
Simulation time 271465087 ps
CPU time 3 seconds
Started Aug 16 06:08:41 PM PDT 24
Finished Aug 16 06:08:44 PM PDT 24
Peak memory 226500 kb
Host smart-957d0558-8db3-4fa0-9216-ebd9a11e2d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614113249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.3614113249 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_key_error/latest

Test location /workspace/coverage/default/32.kmac_long_msg_and_output.3034902301
Short name T542
Test name
Test status
Simulation time 93344100916 ps
CPU time 1956.99 seconds
Started Aug 16 06:08:41 PM PDT 24
Finished Aug 16 06:41:19 PM PDT 24
Peak memory 1127324 kb
Host smart-a4c404a6-a42f-4be2-a7e3-f6d150c91316
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034902301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_a
nd_output.3034902301 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/32.kmac_sideload.2971592078
Short name T563
Test name
Test status
Simulation time 1036685207 ps
CPU time 97.64 seconds
Started Aug 16 06:08:41 PM PDT 24
Finished Aug 16 06:10:19 PM PDT 24
Peak memory 252632 kb
Host smart-6a3598f5-9ede-4295-aea1-b204b8a94c86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971592078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.2971592078 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_sideload/latest

Test location /workspace/coverage/default/32.kmac_smoke.3345797840
Short name T221
Test name
Test status
Simulation time 4217253622 ps
CPU time 57.03 seconds
Started Aug 16 06:08:40 PM PDT 24
Finished Aug 16 06:09:37 PM PDT 24
Peak memory 226872 kb
Host smart-5804fc3d-a51d-4a97-af0a-209e4cdf7237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345797840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.3345797840 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_smoke/latest

Test location /workspace/coverage/default/32.kmac_stress_all.3774597810
Short name T618
Test name
Test status
Simulation time 27082767965 ps
CPU time 59.51 seconds
Started Aug 16 06:08:40 PM PDT 24
Finished Aug 16 06:09:40 PM PDT 24
Peak memory 265644 kb
Host smart-3f20b0c2-bd21-4204-be5c-50449ca65a03
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3774597810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.3774597810 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_stress_all/latest

Test location /workspace/coverage/default/33.kmac_alert_test.3475719837
Short name T131
Test name
Test status
Simulation time 35339118 ps
CPU time 0.79 seconds
Started Aug 16 06:08:46 PM PDT 24
Finished Aug 16 06:08:47 PM PDT 24
Peak memory 218264 kb
Host smart-3dc1e5a5-21c9-4d71-b0e9-e9181648f59c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475719837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.3475719837 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_alert_test/latest

Test location /workspace/coverage/default/33.kmac_app.1547766244
Short name T650
Test name
Test status
Simulation time 6521696826 ps
CPU time 169.64 seconds
Started Aug 16 06:08:47 PM PDT 24
Finished Aug 16 06:11:37 PM PDT 24
Peak memory 278108 kb
Host smart-fc09a198-34e1-4bb2-886e-1f66ed37252d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547766244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.1547766244 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/33.kmac_app/latest

Test location /workspace/coverage/default/33.kmac_burst_write.24836205
Short name T379
Test name
Test status
Simulation time 3448855199 ps
CPU time 96.94 seconds
Started Aug 16 06:08:46 PM PDT 24
Finished Aug 16 06:10:23 PM PDT 24
Peak memory 234740 kb
Host smart-e1827226-18f9-4492-9d06-f8545cd047df
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24836205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.24836205 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_burst_write/latest

Test location /workspace/coverage/default/33.kmac_entropy_refresh.862872784
Short name T363
Test name
Test status
Simulation time 31586578327 ps
CPU time 445.32 seconds
Started Aug 16 06:08:47 PM PDT 24
Finished Aug 16 06:16:12 PM PDT 24
Peak memory 495136 kb
Host smart-f8435833-a782-4657-aba0-1fbf3a99ceba
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862872784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.86
2872784 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/33.kmac_error.427503539
Short name T712
Test name
Test status
Simulation time 32397498713 ps
CPU time 489.82 seconds
Started Aug 16 06:08:45 PM PDT 24
Finished Aug 16 06:16:56 PM PDT 24
Peak memory 570848 kb
Host smart-0edbb1f3-84ed-4349-b0b4-c51e56f7d365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427503539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.427503539 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_error/latest

Test location /workspace/coverage/default/33.kmac_key_error.770632918
Short name T277
Test name
Test status
Simulation time 3715764646 ps
CPU time 7.98 seconds
Started Aug 16 06:08:48 PM PDT 24
Finished Aug 16 06:08:56 PM PDT 24
Peak memory 226476 kb
Host smart-f3a6f67a-dd5a-446b-8ca0-ea943fff7da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770632918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.770632918 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_key_error/latest

Test location /workspace/coverage/default/33.kmac_lc_escalation.3773734434
Short name T628
Test name
Test status
Simulation time 108178558 ps
CPU time 1.32 seconds
Started Aug 16 06:08:45 PM PDT 24
Finished Aug 16 06:08:47 PM PDT 24
Peak memory 226552 kb
Host smart-2879bb12-b49f-4ffe-b190-a9e837c9d759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773734434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.3773734434 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/33.kmac_lc_escalation/latest

Test location /workspace/coverage/default/33.kmac_long_msg_and_output.4233975116
Short name T544
Test name
Test status
Simulation time 588308834864 ps
CPU time 5079.63 seconds
Started Aug 16 06:08:45 PM PDT 24
Finished Aug 16 07:33:26 PM PDT 24
Peak memory 3495352 kb
Host smart-f686c7d5-3b83-4212-9295-39a647a6842c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233975116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_a
nd_output.4233975116 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/33.kmac_sideload.741441288
Short name T212
Test name
Test status
Simulation time 18853934743 ps
CPU time 394.57 seconds
Started Aug 16 06:08:45 PM PDT 24
Finished Aug 16 06:15:20 PM PDT 24
Peak memory 530824 kb
Host smart-01e492c8-257f-42c6-ac12-1e4f0655952e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741441288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.741441288 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_sideload/latest

Test location /workspace/coverage/default/33.kmac_smoke.1836401707
Short name T704
Test name
Test status
Simulation time 429116910 ps
CPU time 2.28 seconds
Started Aug 16 06:08:38 PM PDT 24
Finished Aug 16 06:08:41 PM PDT 24
Peak memory 222884 kb
Host smart-ce459e1d-3472-483e-9104-117421261158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836401707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.1836401707 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_smoke/latest

Test location /workspace/coverage/default/33.kmac_stress_all.3181409423
Short name T56
Test name
Test status
Simulation time 36194492153 ps
CPU time 463.53 seconds
Started Aug 16 06:08:46 PM PDT 24
Finished Aug 16 06:16:30 PM PDT 24
Peak memory 426804 kb
Host smart-766d1219-78e7-4330-957e-a37c05026be6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3181409423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.3181409423 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all/latest

Test location /workspace/coverage/default/34.kmac_alert_test.406670264
Short name T357
Test name
Test status
Simulation time 29485174 ps
CPU time 0.78 seconds
Started Aug 16 06:08:58 PM PDT 24
Finished Aug 16 06:08:58 PM PDT 24
Peak memory 218248 kb
Host smart-4f81292b-4032-4275-9ba0-7d49cc7cd3f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406670264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.406670264 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/34.kmac_alert_test/latest

Test location /workspace/coverage/default/34.kmac_app.928242125
Short name T40
Test name
Test status
Simulation time 23290394803 ps
CPU time 276.43 seconds
Started Aug 16 06:08:50 PM PDT 24
Finished Aug 16 06:13:27 PM PDT 24
Peak memory 306692 kb
Host smart-bc02dc0f-bffc-4975-87f4-4d93ff46858b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928242125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.928242125 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/34.kmac_app/latest

Test location /workspace/coverage/default/34.kmac_burst_write.1302708598
Short name T209
Test name
Test status
Simulation time 9165582442 ps
CPU time 213.39 seconds
Started Aug 16 06:08:47 PM PDT 24
Finished Aug 16 06:12:20 PM PDT 24
Peak memory 230840 kb
Host smart-efe645d3-67b5-4804-bfa8-3b9d653af868
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302708598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.130270859
8 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_burst_write/latest

Test location /workspace/coverage/default/34.kmac_entropy_refresh.1805522292
Short name T113
Test name
Test status
Simulation time 2443117180 ps
CPU time 107.25 seconds
Started Aug 16 06:08:46 PM PDT 24
Finished Aug 16 06:10:34 PM PDT 24
Peak memory 255776 kb
Host smart-11bc1af1-04ee-4613-85bc-2370f778e7de
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805522292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.1
805522292 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/34.kmac_error.2529705650
Short name T278
Test name
Test status
Simulation time 1790574549 ps
CPU time 31.48 seconds
Started Aug 16 06:08:48 PM PDT 24
Finished Aug 16 06:09:20 PM PDT 24
Peak memory 258652 kb
Host smart-8db47cf1-fda5-4702-8a9b-c951672c8543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529705650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.2529705650 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_error/latest

Test location /workspace/coverage/default/34.kmac_lc_escalation.2592262348
Short name T710
Test name
Test status
Simulation time 1706013222 ps
CPU time 21.22 seconds
Started Aug 16 06:08:55 PM PDT 24
Finished Aug 16 06:09:16 PM PDT 24
Peak memory 245176 kb
Host smart-2c1e7d08-4e0c-4041-9642-5fc84b4fc0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592262348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.2592262348 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/34.kmac_lc_escalation/latest

Test location /workspace/coverage/default/34.kmac_sideload.4001280388
Short name T699
Test name
Test status
Simulation time 7357578273 ps
CPU time 137.56 seconds
Started Aug 16 06:08:47 PM PDT 24
Finished Aug 16 06:11:05 PM PDT 24
Peak memory 316904 kb
Host smart-9a036526-2fd2-480a-931f-604da6afbce3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001280388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.4001280388 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_sideload/latest

Test location /workspace/coverage/default/34.kmac_smoke.4101817142
Short name T284
Test name
Test status
Simulation time 1206314685 ps
CPU time 29.42 seconds
Started Aug 16 06:08:50 PM PDT 24
Finished Aug 16 06:09:20 PM PDT 24
Peak memory 222228 kb
Host smart-f896b961-749e-433d-8150-423ebb6a8c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101817142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.4101817142 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_smoke/latest

Test location /workspace/coverage/default/34.kmac_stress_all.2188151304
Short name T216
Test name
Test status
Simulation time 74531956570 ps
CPU time 951.18 seconds
Started Aug 16 06:08:58 PM PDT 24
Finished Aug 16 06:24:49 PM PDT 24
Peak memory 466344 kb
Host smart-c5c46e95-bd94-47ec-aeac-cac0de5c2820
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2188151304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.2188151304 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_stress_all/latest

Test location /workspace/coverage/default/35.kmac_alert_test.3707003724
Short name T538
Test name
Test status
Simulation time 17986491 ps
CPU time 0.82 seconds
Started Aug 16 06:09:05 PM PDT 24
Finished Aug 16 06:09:06 PM PDT 24
Peak memory 218148 kb
Host smart-c8403c4d-8395-42d8-bfb1-65ddcd398a05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707003724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.3707003724 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_alert_test/latest

Test location /workspace/coverage/default/35.kmac_app.898203273
Short name T598
Test name
Test status
Simulation time 4371719407 ps
CPU time 100.45 seconds
Started Aug 16 06:08:55 PM PDT 24
Finished Aug 16 06:10:35 PM PDT 24
Peak memory 299820 kb
Host smart-b9fb26cb-f228-4ed3-9ca1-be881d9a19a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898203273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.898203273 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/35.kmac_app/latest

Test location /workspace/coverage/default/35.kmac_burst_write.835279154
Short name T573
Test name
Test status
Simulation time 35137992898 ps
CPU time 1656.51 seconds
Started Aug 16 06:08:57 PM PDT 24
Finished Aug 16 06:36:34 PM PDT 24
Peak memory 264952 kb
Host smart-af426427-460c-400f-9949-796e567ac0c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835279154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.835279154
+enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_burst_write/latest

Test location /workspace/coverage/default/35.kmac_entropy_refresh.1712444391
Short name T518
Test name
Test status
Simulation time 8687317657 ps
CPU time 44.93 seconds
Started Aug 16 06:08:55 PM PDT 24
Finished Aug 16 06:09:40 PM PDT 24
Peak memory 255688 kb
Host smart-d2bbbec7-f19c-45ca-99d1-ca6a172d2f97
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712444391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.1
712444391 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/35.kmac_error.2074198958
Short name T23
Test name
Test status
Simulation time 720605319 ps
CPU time 24.86 seconds
Started Aug 16 06:08:55 PM PDT 24
Finished Aug 16 06:09:20 PM PDT 24
Peak memory 243148 kb
Host smart-cc5947d9-1949-4684-9662-fccaab06a508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074198958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.2074198958 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_error/latest

Test location /workspace/coverage/default/35.kmac_key_error.3303867093
Short name T4
Test name
Test status
Simulation time 2491926521 ps
CPU time 11.95 seconds
Started Aug 16 06:08:56 PM PDT 24
Finished Aug 16 06:09:08 PM PDT 24
Peak memory 226456 kb
Host smart-22022553-15a2-4d37-b023-6dd6c10e6f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303867093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.3303867093 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_key_error/latest

Test location /workspace/coverage/default/35.kmac_long_msg_and_output.2395728893
Short name T2
Test name
Test status
Simulation time 297095178752 ps
CPU time 3402.01 seconds
Started Aug 16 06:08:54 PM PDT 24
Finished Aug 16 07:05:36 PM PDT 24
Peak memory 2968460 kb
Host smart-98033837-051a-4921-a086-d578c15e5709
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395728893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_a
nd_output.2395728893 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/35.kmac_sideload.206008580
Short name T199
Test name
Test status
Simulation time 7507095937 ps
CPU time 201.74 seconds
Started Aug 16 06:08:57 PM PDT 24
Finished Aug 16 06:12:19 PM PDT 24
Peak memory 383520 kb
Host smart-82a8f9a3-5a00-47a4-b8a4-5d78aad6ce45
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206008580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.206008580 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_sideload/latest

Test location /workspace/coverage/default/35.kmac_smoke.4056353454
Short name T456
Test name
Test status
Simulation time 3053111168 ps
CPU time 17.08 seconds
Started Aug 16 06:08:55 PM PDT 24
Finished Aug 16 06:09:12 PM PDT 24
Peak memory 222532 kb
Host smart-636cdcbc-501b-4a42-b6e9-35b4ca4c5e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056353454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.4056353454 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_smoke/latest

Test location /workspace/coverage/default/35.kmac_stress_all.899301722
Short name T220
Test name
Test status
Simulation time 13940856320 ps
CPU time 129.79 seconds
Started Aug 16 06:08:54 PM PDT 24
Finished Aug 16 06:11:04 PM PDT 24
Peak memory 322804 kb
Host smart-e1e06445-e940-4397-b4af-1bdf3667dd59
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=899301722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.899301722 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_stress_all/latest

Test location /workspace/coverage/default/36.kmac_alert_test.1327227977
Short name T599
Test name
Test status
Simulation time 17662427 ps
CPU time 0.83 seconds
Started Aug 16 06:09:05 PM PDT 24
Finished Aug 16 06:09:06 PM PDT 24
Peak memory 218300 kb
Host smart-3cc3b749-77b1-4d35-84c0-21ede28385c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327227977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.1327227977 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_alert_test/latest

Test location /workspace/coverage/default/36.kmac_burst_write.1400834027
Short name T358
Test name
Test status
Simulation time 5840268603 ps
CPU time 536.29 seconds
Started Aug 16 06:09:03 PM PDT 24
Finished Aug 16 06:18:00 PM PDT 24
Peak memory 236420 kb
Host smart-89e78ae3-91fc-448c-959e-aa5766436e78
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400834027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.140083402
7 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_burst_write/latest

Test location /workspace/coverage/default/36.kmac_entropy_refresh.780200866
Short name T427
Test name
Test status
Simulation time 94046036022 ps
CPU time 382.95 seconds
Started Aug 16 06:09:05 PM PDT 24
Finished Aug 16 06:15:28 PM PDT 24
Peak memory 523220 kb
Host smart-1359355e-9b65-483b-b5bd-fcaa53892eb6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780200866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.78
0200866 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/36.kmac_error.819768721
Short name T690
Test name
Test status
Simulation time 3497481592 ps
CPU time 74.12 seconds
Started Aug 16 06:09:04 PM PDT 24
Finished Aug 16 06:10:18 PM PDT 24
Peak memory 258068 kb
Host smart-35178c48-86b7-42d7-a274-a69d3ef0a5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819768721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.819768721 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_error/latest

Test location /workspace/coverage/default/36.kmac_key_error.50659059
Short name T648
Test name
Test status
Simulation time 6599124508 ps
CPU time 14.99 seconds
Started Aug 16 06:09:04 PM PDT 24
Finished Aug 16 06:09:19 PM PDT 24
Peak memory 226644 kb
Host smart-ce607b90-c8aa-4e9e-9114-dcee0b0dfb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50659059 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.50659059 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_key_error/latest

Test location /workspace/coverage/default/36.kmac_lc_escalation.953022760
Short name T408
Test name
Test status
Simulation time 49536487 ps
CPU time 1.38 seconds
Started Aug 16 06:09:03 PM PDT 24
Finished Aug 16 06:09:04 PM PDT 24
Peak memory 226576 kb
Host smart-823bd029-5c65-405f-89ea-992d630b5f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953022760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.953022760 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/36.kmac_lc_escalation/latest

Test location /workspace/coverage/default/36.kmac_long_msg_and_output.1353150297
Short name T596
Test name
Test status
Simulation time 350378120748 ps
CPU time 4222.98 seconds
Started Aug 16 06:09:04 PM PDT 24
Finished Aug 16 07:19:28 PM PDT 24
Peak memory 3391272 kb
Host smart-e3772a6e-6677-4cdd-9433-aa96ecd3ed6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353150297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_a
nd_output.1353150297 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/36.kmac_sideload.974235984
Short name T237
Test name
Test status
Simulation time 21030417715 ps
CPU time 161.39 seconds
Started Aug 16 06:09:05 PM PDT 24
Finished Aug 16 06:11:46 PM PDT 24
Peak memory 333900 kb
Host smart-ef4be655-e422-4a3c-a4b5-8ae3d0a06828
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974235984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.974235984 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_sideload/latest

Test location /workspace/coverage/default/36.kmac_smoke.591013359
Short name T708
Test name
Test status
Simulation time 9025346722 ps
CPU time 89.17 seconds
Started Aug 16 06:09:05 PM PDT 24
Finished Aug 16 06:10:35 PM PDT 24
Peak memory 227804 kb
Host smart-82cce412-b4b9-43d0-a9dc-d3320e90ca2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591013359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.591013359 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_smoke/latest

Test location /workspace/coverage/default/36.kmac_stress_all.474524008
Short name T61
Test name
Test status
Simulation time 26531820409 ps
CPU time 649.04 seconds
Started Aug 16 06:09:06 PM PDT 24
Finished Aug 16 06:19:55 PM PDT 24
Peak memory 303272 kb
Host smart-b9fc07a0-6501-40d8-8409-8409f01e069e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=474524008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.474524008 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_stress_all/latest

Test location /workspace/coverage/default/37.kmac_alert_test.531401108
Short name T491
Test name
Test status
Simulation time 67304060 ps
CPU time 0.86 seconds
Started Aug 16 06:09:14 PM PDT 24
Finished Aug 16 06:09:15 PM PDT 24
Peak memory 218248 kb
Host smart-c023fd8e-f33a-4ee3-81ca-62d797ea5be3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531401108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.531401108 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/37.kmac_alert_test/latest

Test location /workspace/coverage/default/37.kmac_app.1316864640
Short name T230
Test name
Test status
Simulation time 67037926467 ps
CPU time 277.72 seconds
Started Aug 16 06:09:07 PM PDT 24
Finished Aug 16 06:13:45 PM PDT 24
Peak memory 387000 kb
Host smart-e4cba83f-6cb5-4314-a995-6d4d12eaea88
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316864640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.1316864640 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/37.kmac_app/latest

Test location /workspace/coverage/default/37.kmac_burst_write.4233960260
Short name T430
Test name
Test status
Simulation time 9760586080 ps
CPU time 236.21 seconds
Started Aug 16 06:09:03 PM PDT 24
Finished Aug 16 06:12:59 PM PDT 24
Peak memory 231768 kb
Host smart-071a420c-423c-426f-b396-de366ea61e1f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233960260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.423396026
0 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_burst_write/latest

Test location /workspace/coverage/default/37.kmac_entropy_refresh.294514057
Short name T7
Test name
Test status
Simulation time 635616957 ps
CPU time 1.85 seconds
Started Aug 16 06:09:15 PM PDT 24
Finished Aug 16 06:09:17 PM PDT 24
Peak memory 218596 kb
Host smart-b9fee519-28e6-45fe-be5d-6275e3eb91c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294514057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.29
4514057 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/37.kmac_key_error.201883760
Short name T530
Test name
Test status
Simulation time 1323379799 ps
CPU time 9.61 seconds
Started Aug 16 06:09:13 PM PDT 24
Finished Aug 16 06:09:23 PM PDT 24
Peak memory 226436 kb
Host smart-a100a3a3-3eba-4121-b46e-486ab4ab251d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201883760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.201883760 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_key_error/latest

Test location /workspace/coverage/default/37.kmac_lc_escalation.1246523140
Short name T54
Test name
Test status
Simulation time 678497714 ps
CPU time 7.84 seconds
Started Aug 16 06:09:14 PM PDT 24
Finished Aug 16 06:09:22 PM PDT 24
Peak memory 235076 kb
Host smart-1d2f05c4-5346-4424-ac67-00fdf8e7c9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246523140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.1246523140 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/37.kmac_lc_escalation/latest

Test location /workspace/coverage/default/37.kmac_long_msg_and_output.4070930470
Short name T273
Test name
Test status
Simulation time 29646065865 ps
CPU time 1796.56 seconds
Started Aug 16 06:09:03 PM PDT 24
Finished Aug 16 06:39:00 PM PDT 24
Peak memory 1019396 kb
Host smart-a6d7b244-c249-4a60-b939-d308ecbc9945
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070930470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_a
nd_output.4070930470 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/37.kmac_sideload.1430576432
Short name T543
Test name
Test status
Simulation time 4282776964 ps
CPU time 308.18 seconds
Started Aug 16 06:09:03 PM PDT 24
Finished Aug 16 06:14:12 PM PDT 24
Peak memory 330552 kb
Host smart-63abe903-afa6-42f3-a17c-27d0d5688f3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430576432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.1430576432 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_sideload/latest

Test location /workspace/coverage/default/37.kmac_smoke.3848596493
Short name T383
Test name
Test status
Simulation time 12840472048 ps
CPU time 47.64 seconds
Started Aug 16 06:09:06 PM PDT 24
Finished Aug 16 06:09:54 PM PDT 24
Peak memory 223512 kb
Host smart-d54c1b7b-3321-42d7-bab9-0a6a10c61160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848596493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.3848596493 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_smoke/latest

Test location /workspace/coverage/default/37.kmac_stress_all.2321674544
Short name T275
Test name
Test status
Simulation time 31857373293 ps
CPU time 802.9 seconds
Started Aug 16 06:09:15 PM PDT 24
Finished Aug 16 06:22:39 PM PDT 24
Peak memory 297448 kb
Host smart-3e21feb6-5e26-4c41-9d0f-53ceb7683e37
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2321674544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.2321674544 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_stress_all/latest

Test location /workspace/coverage/default/38.kmac_alert_test.2333975303
Short name T97
Test name
Test status
Simulation time 18151050 ps
CPU time 0.87 seconds
Started Aug 16 06:09:16 PM PDT 24
Finished Aug 16 06:09:17 PM PDT 24
Peak memory 218236 kb
Host smart-b9c77622-3822-43d3-8165-94508ca8ab3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333975303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.2333975303 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_alert_test/latest

Test location /workspace/coverage/default/38.kmac_app.9461049
Short name T294
Test name
Test status
Simulation time 11006227102 ps
CPU time 92.45 seconds
Started Aug 16 06:09:13 PM PDT 24
Finished Aug 16 06:10:46 PM PDT 24
Peak memory 281220 kb
Host smart-ecebed51-3a0b-4375-8ea6-abd8da6802b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9461049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.9461049 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/38.kmac_app/latest

Test location /workspace/coverage/default/38.kmac_burst_write.3445160314
Short name T589
Test name
Test status
Simulation time 62923963056 ps
CPU time 897.42 seconds
Started Aug 16 06:09:14 PM PDT 24
Finished Aug 16 06:24:12 PM PDT 24
Peak memory 250564 kb
Host smart-a89fa565-3c9e-47e0-96c0-35db536c8dd9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445160314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.344516031
4 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_burst_write/latest

Test location /workspace/coverage/default/38.kmac_entropy_refresh.893690692
Short name T612
Test name
Test status
Simulation time 15244475813 ps
CPU time 239.37 seconds
Started Aug 16 06:09:13 PM PDT 24
Finished Aug 16 06:13:12 PM PDT 24
Peak memory 295824 kb
Host smart-7a9f25d8-36b9-4d83-93bc-6ad01ace9892
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893690692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.89
3690692 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/38.kmac_error.1682958830
Short name T68
Test name
Test status
Simulation time 23197884062 ps
CPU time 403.17 seconds
Started Aug 16 06:09:13 PM PDT 24
Finished Aug 16 06:15:56 PM PDT 24
Peak memory 524936 kb
Host smart-b1e100aa-9dfc-4d32-b4f5-90a25bfc069a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682958830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.1682958830 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_error/latest

Test location /workspace/coverage/default/38.kmac_key_error.1542847421
Short name T630
Test name
Test status
Simulation time 280859331 ps
CPU time 2.74 seconds
Started Aug 16 06:09:13 PM PDT 24
Finished Aug 16 06:09:16 PM PDT 24
Peak memory 226468 kb
Host smart-c534077f-fd0f-4c0c-b8c0-4f274c70d850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542847421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.1542847421 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_key_error/latest

Test location /workspace/coverage/default/38.kmac_lc_escalation.3344167108
Short name T51
Test name
Test status
Simulation time 30215360 ps
CPU time 1.39 seconds
Started Aug 16 06:09:13 PM PDT 24
Finished Aug 16 06:09:14 PM PDT 24
Peak memory 226652 kb
Host smart-572687c5-27ca-4041-88e3-c95e0ee5e45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344167108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.3344167108 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/38.kmac_lc_escalation/latest

Test location /workspace/coverage/default/38.kmac_long_msg_and_output.3832777629
Short name T38
Test name
Test status
Simulation time 40125939742 ps
CPU time 364.95 seconds
Started Aug 16 06:09:14 PM PDT 24
Finished Aug 16 06:15:19 PM PDT 24
Peak memory 629568 kb
Host smart-65928a3f-8d8b-499c-a19e-bc6b612f75e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832777629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_a
nd_output.3832777629 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/38.kmac_sideload.144542975
Short name T136
Test name
Test status
Simulation time 1753787101 ps
CPU time 162.06 seconds
Started Aug 16 06:09:14 PM PDT 24
Finished Aug 16 06:11:57 PM PDT 24
Peak memory 270940 kb
Host smart-f4f13730-e0bb-40b1-ba80-97d3b964c2bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144542975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.144542975 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_sideload/latest

Test location /workspace/coverage/default/38.kmac_smoke.331078817
Short name T554
Test name
Test status
Simulation time 32437558415 ps
CPU time 66.97 seconds
Started Aug 16 06:09:11 PM PDT 24
Finished Aug 16 06:10:18 PM PDT 24
Peak memory 222700 kb
Host smart-62160bf1-5277-4ea5-96e1-1b2f667482a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331078817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.331078817 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_smoke/latest

Test location /workspace/coverage/default/38.kmac_stress_all.3480777020
Short name T348
Test name
Test status
Simulation time 109024428344 ps
CPU time 723.76 seconds
Started Aug 16 06:09:16 PM PDT 24
Finished Aug 16 06:21:20 PM PDT 24
Peak memory 553980 kb
Host smart-37df2212-c9a6-4552-8f6b-e08939ddef83
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3480777020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.3480777020 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all/latest

Test location /workspace/coverage/default/39.kmac_alert_test.544548794
Short name T453
Test name
Test status
Simulation time 15974774 ps
CPU time 0.84 seconds
Started Aug 16 06:09:26 PM PDT 24
Finished Aug 16 06:09:27 PM PDT 24
Peak memory 218228 kb
Host smart-de94b9d1-18a0-4873-a4c3-befc9afed9a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544548794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.544548794 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/39.kmac_alert_test/latest

Test location /workspace/coverage/default/39.kmac_app.1890994453
Short name T571
Test name
Test status
Simulation time 30694956277 ps
CPU time 114.36 seconds
Started Aug 16 06:09:22 PM PDT 24
Finished Aug 16 06:11:16 PM PDT 24
Peak memory 293552 kb
Host smart-f5f48fac-1c6e-422a-b447-7d6e5a21a149
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890994453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.1890994453 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/39.kmac_app/latest

Test location /workspace/coverage/default/39.kmac_burst_write.2069265940
Short name T653
Test name
Test status
Simulation time 7991073688 ps
CPU time 214.67 seconds
Started Aug 16 06:09:24 PM PDT 24
Finished Aug 16 06:12:59 PM PDT 24
Peak memory 228748 kb
Host smart-57099558-65e3-4655-89e7-140284488f82
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069265940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.206926594
0 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_burst_write/latest

Test location /workspace/coverage/default/39.kmac_entropy_refresh.2156365933
Short name T561
Test name
Test status
Simulation time 8685645652 ps
CPU time 357.5 seconds
Started Aug 16 06:09:26 PM PDT 24
Finished Aug 16 06:15:24 PM PDT 24
Peak memory 331260 kb
Host smart-96159013-bbe5-484f-ae39-80b453179ad3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156365933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.2
156365933 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/39.kmac_error.3483528673
Short name T24
Test name
Test status
Simulation time 6487258052 ps
CPU time 130.35 seconds
Started Aug 16 06:09:20 PM PDT 24
Finished Aug 16 06:11:30 PM PDT 24
Peak memory 275908 kb
Host smart-8ad13661-663b-443d-8a6e-784a025e22e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483528673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.3483528673 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_error/latest

Test location /workspace/coverage/default/39.kmac_key_error.1629579515
Short name T137
Test name
Test status
Simulation time 752958514 ps
CPU time 7.26 seconds
Started Aug 16 06:09:31 PM PDT 24
Finished Aug 16 06:09:39 PM PDT 24
Peak memory 225812 kb
Host smart-32265cc6-5251-474f-8dcd-e06e17119376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629579515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.1629579515 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_key_error/latest

Test location /workspace/coverage/default/39.kmac_lc_escalation.49790224
Short name T494
Test name
Test status
Simulation time 91581096 ps
CPU time 1.45 seconds
Started Aug 16 06:09:22 PM PDT 24
Finished Aug 16 06:09:24 PM PDT 24
Peak memory 226592 kb
Host smart-7d7a9619-84af-4228-b79a-825c183a7c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49790224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.49790224 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_lc_escalation/latest

Test location /workspace/coverage/default/39.kmac_sideload.3708279738
Short name T397
Test name
Test status
Simulation time 5227307337 ps
CPU time 136.61 seconds
Started Aug 16 06:09:31 PM PDT 24
Finished Aug 16 06:11:48 PM PDT 24
Peak memory 268824 kb
Host smart-91784fed-90c3-4c5c-988e-87516f73a7b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708279738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.3708279738 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_sideload/latest

Test location /workspace/coverage/default/39.kmac_stress_all.2698107771
Short name T709
Test name
Test status
Simulation time 80513030267 ps
CPU time 1352.38 seconds
Started Aug 16 06:09:23 PM PDT 24
Finished Aug 16 06:31:55 PM PDT 24
Peak memory 705864 kb
Host smart-6e78cb97-eda7-449c-973e-9d61b6e66fd3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2698107771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.2698107771 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_alert_test.3264385788
Short name T392
Test name
Test status
Simulation time 25849570 ps
CPU time 0.79 seconds
Started Aug 16 06:06:09 PM PDT 24
Finished Aug 16 06:06:10 PM PDT 24
Peak memory 218268 kb
Host smart-439969e6-63de-4a38-814b-4305c10afff1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264385788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.3264385788 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_alert_test/latest

Test location /workspace/coverage/default/4.kmac_app.3404212320
Short name T535
Test name
Test status
Simulation time 2039847179 ps
CPU time 43.15 seconds
Started Aug 16 06:06:07 PM PDT 24
Finished Aug 16 06:06:50 PM PDT 24
Peak memory 250780 kb
Host smart-f1a503d6-721c-4dc0-9ba6-90efa9e7b988
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404212320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.3404212320 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/4.kmac_app/latest

Test location /workspace/coverage/default/4.kmac_app_with_partial_data.1312647267
Short name T437
Test name
Test status
Simulation time 44828358405 ps
CPU time 361.74 seconds
Started Aug 16 06:06:07 PM PDT 24
Finished Aug 16 06:12:08 PM PDT 24
Peak memory 320024 kb
Host smart-bccc0175-4826-4285-9848-90c586a00a0b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312647267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_par
tial_data.1312647267 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/4.kmac_burst_write.608308528
Short name T590
Test name
Test status
Simulation time 31856225957 ps
CPU time 339.03 seconds
Started Aug 16 06:06:11 PM PDT 24
Finished Aug 16 06:11:50 PM PDT 24
Peak memory 243160 kb
Host smart-4160a37c-60cb-440d-b494-6f5c5e05bd7f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608308528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.608308528 +
enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_burst_write/latest

Test location /workspace/coverage/default/4.kmac_edn_timeout_error.4156115418
Short name T713
Test name
Test status
Simulation time 1178530551 ps
CPU time 9.85 seconds
Started Aug 16 06:06:11 PM PDT 24
Finished Aug 16 06:06:21 PM PDT 24
Peak memory 220660 kb
Host smart-f3ceddf0-e5b1-467a-9517-42a85074a4c0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4156115418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.4156115418 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_mode_error.1772679077
Short name T525
Test name
Test status
Simulation time 40723486 ps
CPU time 1.11 seconds
Started Aug 16 06:06:09 PM PDT 24
Finished Aug 16 06:06:10 PM PDT 24
Peak memory 222236 kb
Host smart-76d85544-590f-492c-86f2-bd7b1ff2e4ab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1772679077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.1772679077 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_ready_error.3000388206
Short name T656
Test name
Test status
Simulation time 2099327583 ps
CPU time 6.2 seconds
Started Aug 16 06:06:10 PM PDT 24
Finished Aug 16 06:06:16 PM PDT 24
Peak memory 226572 kb
Host smart-949e5942-cd04-4109-98fe-00310d66318c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000388206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.3000388206 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_refresh.2796031862
Short name T361
Test name
Test status
Simulation time 2707296072 ps
CPU time 77.76 seconds
Started Aug 16 06:06:07 PM PDT 24
Finished Aug 16 06:07:25 PM PDT 24
Peak memory 247528 kb
Host smart-694df221-af3e-4812-a1ac-524c40196bf8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796031862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.27
96031862 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/4.kmac_error.500164437
Short name T249
Test name
Test status
Simulation time 41491317764 ps
CPU time 342.93 seconds
Started Aug 16 06:06:07 PM PDT 24
Finished Aug 16 06:11:50 PM PDT 24
Peak memory 456212 kb
Host smart-a7eff656-4b4c-4809-86db-02844c64d283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500164437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.500164437 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_error/latest

Test location /workspace/coverage/default/4.kmac_key_error.3084570121
Short name T243
Test name
Test status
Simulation time 1943068729 ps
CPU time 6.99 seconds
Started Aug 16 06:06:13 PM PDT 24
Finished Aug 16 06:06:20 PM PDT 24
Peak memory 226476 kb
Host smart-2daf7d9c-f6d0-4e9b-8b7a-a5467c43b287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084570121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.3084570121 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_key_error/latest

Test location /workspace/coverage/default/4.kmac_lc_escalation.741034213
Short name T694
Test name
Test status
Simulation time 69274186 ps
CPU time 1.31 seconds
Started Aug 16 06:06:10 PM PDT 24
Finished Aug 16 06:06:12 PM PDT 24
Peak memory 226704 kb
Host smart-6f264df4-bc4d-4497-bfde-2fa860b5bbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741034213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.741034213 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_lc_escalation/latest

Test location /workspace/coverage/default/4.kmac_long_msg_and_output.11349762
Short name T63
Test name
Test status
Simulation time 135098660721 ps
CPU time 2800.84 seconds
Started Aug 16 06:06:09 PM PDT 24
Finished Aug 16 06:52:51 PM PDT 24
Peak memory 1401740 kb
Host smart-036110ce-8761-4c79-8fce-dac39f5a4d8e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11349762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and
_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and_
output.11349762 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/4.kmac_mubi.2382537251
Short name T640
Test name
Test status
Simulation time 39364323881 ps
CPU time 320.66 seconds
Started Aug 16 06:06:09 PM PDT 24
Finished Aug 16 06:11:30 PM PDT 24
Peak memory 454784 kb
Host smart-43e51b49-e5fe-4df4-a1fe-dd95edb478b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382537251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.2382537251 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mubi/latest

Test location /workspace/coverage/default/4.kmac_sec_cm.2955919913
Short name T106
Test name
Test status
Simulation time 6180042752 ps
CPU time 45.44 seconds
Started Aug 16 06:06:09 PM PDT 24
Finished Aug 16 06:06:54 PM PDT 24
Peak memory 260000 kb
Host smart-5f39b40d-2768-440d-bcb2-f761668423f3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955919913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.2955919913 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/4.kmac_sec_cm/latest

Test location /workspace/coverage/default/4.kmac_sideload.3685335281
Short name T232
Test name
Test status
Simulation time 6497550075 ps
CPU time 139.64 seconds
Started Aug 16 06:06:08 PM PDT 24
Finished Aug 16 06:08:28 PM PDT 24
Peak memory 274284 kb
Host smart-db52ff2d-a15a-45aa-ac9b-07a24c47e1c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685335281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.3685335281 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_sideload/latest

Test location /workspace/coverage/default/4.kmac_smoke.2043535876
Short name T253
Test name
Test status
Simulation time 1694681110 ps
CPU time 42.26 seconds
Started Aug 16 06:06:09 PM PDT 24
Finished Aug 16 06:06:51 PM PDT 24
Peak memory 226632 kb
Host smart-27b7912f-4723-4e7e-a9b5-ac388ee0d4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043535876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.2043535876 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_smoke/latest

Test location /workspace/coverage/default/4.kmac_stress_all.1521256859
Short name T307
Test name
Test status
Simulation time 6843276647 ps
CPU time 53.56 seconds
Started Aug 16 06:06:06 PM PDT 24
Finished Aug 16 06:06:59 PM PDT 24
Peak memory 254696 kb
Host smart-76a358ee-9d12-4d0a-bbf2-bb7798264e76
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1521256859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.1521256859 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac_xof.469400518
Short name T326
Test name
Test status
Simulation time 237287015 ps
CPU time 2.48 seconds
Started Aug 16 06:06:07 PM PDT 24
Finished Aug 16 06:06:09 PM PDT 24
Peak memory 218744 kb
Host smart-9017d9df-b45c-4308-91d8-9506b51f906a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469400518 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.kmac_test_vectors_kmac_xof.469400518 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_224.349976597
Short name T394
Test name
Test status
Simulation time 17890726080 ps
CPU time 2102.92 seconds
Started Aug 16 06:06:10 PM PDT 24
Finished Aug 16 06:41:13 PM PDT 24
Peak memory 1169092 kb
Host smart-fead5f31-45d2-4fd3-8c08-be38530c40b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=349976597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.349976597 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_256.3877266358
Short name T675
Test name
Test status
Simulation time 240403190285 ps
CPU time 3234.04 seconds
Started Aug 16 06:06:09 PM PDT 24
Finished Aug 16 07:00:04 PM PDT 24
Peak memory 2964472 kb
Host smart-9f09f739-6dea-498c-93c4-1f1e16bc78a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3877266358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.3877266358 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_384.1085916953
Short name T641
Test name
Test status
Simulation time 1994096017 ps
CPU time 25.95 seconds
Started Aug 16 06:06:12 PM PDT 24
Finished Aug 16 06:06:39 PM PDT 24
Peak memory 219860 kb
Host smart-767834bf-578d-48e0-869d-4f28a02c72c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1085916953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.1085916953 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_512.675308312
Short name T289
Test name
Test status
Simulation time 665877722 ps
CPU time 16.63 seconds
Started Aug 16 06:06:11 PM PDT 24
Finished Aug 16 06:06:28 PM PDT 24
Peak memory 218608 kb
Host smart-cbe7201f-911c-4888-ac30-bea0a1cb1ad8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=675308312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.675308312 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_128.404631698
Short name T485
Test name
Test status
Simulation time 143364934498 ps
CPU time 2751.41 seconds
Started Aug 16 06:06:10 PM PDT 24
Finished Aug 16 06:52:02 PM PDT 24
Peak memory 1372032 kb
Host smart-c47bfc88-46b5-4eb9-a87d-7ce1afeca400
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=404631698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.404631698 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_256.3907582702
Short name T396
Test name
Test status
Simulation time 22940110457 ps
CPU time 2186.04 seconds
Started Aug 16 06:06:10 PM PDT 24
Finished Aug 16 06:42:36 PM PDT 24
Peak memory 1132012 kb
Host smart-2bca0ae7-b220-4ca7-b24c-bf62f2516077
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3907582702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.3907582702 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/40.kmac_alert_test.3936419322
Short name T711
Test name
Test status
Simulation time 16396185 ps
CPU time 0.85 seconds
Started Aug 16 06:09:34 PM PDT 24
Finished Aug 16 06:09:35 PM PDT 24
Peak memory 218264 kb
Host smart-bb4ea540-a92e-4a8d-8d88-9ed1bd4ba462
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936419322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.3936419322 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_alert_test/latest

Test location /workspace/coverage/default/40.kmac_app.3000893758
Short name T489
Test name
Test status
Simulation time 8292369953 ps
CPU time 250.62 seconds
Started Aug 16 06:09:23 PM PDT 24
Finished Aug 16 06:13:33 PM PDT 24
Peak memory 396044 kb
Host smart-1d28c56c-2197-405a-9818-50de3eb32bf0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000893758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.3000893758 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/40.kmac_app/latest

Test location /workspace/coverage/default/40.kmac_burst_write.3253218296
Short name T334
Test name
Test status
Simulation time 375940674 ps
CPU time 13.03 seconds
Started Aug 16 06:09:26 PM PDT 24
Finished Aug 16 06:09:40 PM PDT 24
Peak memory 222024 kb
Host smart-8322001b-fffa-4839-ab64-8df824654136
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253218296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.325321829
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_burst_write/latest

Test location /workspace/coverage/default/40.kmac_entropy_refresh.2876580880
Short name T636
Test name
Test status
Simulation time 29307596316 ps
CPU time 315.09 seconds
Started Aug 16 06:09:23 PM PDT 24
Finished Aug 16 06:14:38 PM PDT 24
Peak memory 316884 kb
Host smart-c349ffa0-d561-4884-b595-6bab0b868ff2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876580880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.2
876580880 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/40.kmac_error.3473084800
Short name T393
Test name
Test status
Simulation time 20889333950 ps
CPU time 445.09 seconds
Started Aug 16 06:09:26 PM PDT 24
Finished Aug 16 06:16:51 PM PDT 24
Peak memory 388540 kb
Host smart-e67483b5-c460-4377-886a-607e1998db73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473084800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.3473084800 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_error/latest

Test location /workspace/coverage/default/40.kmac_key_error.3150564771
Short name T706
Test name
Test status
Simulation time 1122207028 ps
CPU time 8.07 seconds
Started Aug 16 06:09:31 PM PDT 24
Finished Aug 16 06:09:40 PM PDT 24
Peak memory 226452 kb
Host smart-7b9853f3-9484-4bcf-8c4f-67a3949ad923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150564771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.3150564771 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_key_error/latest

Test location /workspace/coverage/default/40.kmac_lc_escalation.1442677586
Short name T260
Test name
Test status
Simulation time 79057560 ps
CPU time 1.47 seconds
Started Aug 16 06:09:32 PM PDT 24
Finished Aug 16 06:09:33 PM PDT 24
Peak memory 226596 kb
Host smart-204998d8-5e6b-4681-a858-9b2847a950f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442677586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.1442677586 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/40.kmac_lc_escalation/latest

Test location /workspace/coverage/default/40.kmac_long_msg_and_output.490795557
Short name T219
Test name
Test status
Simulation time 168900194214 ps
CPU time 2071.79 seconds
Started Aug 16 06:09:27 PM PDT 24
Finished Aug 16 06:43:59 PM PDT 24
Peak memory 2118200 kb
Host smart-69270c72-b3bf-4802-b639-72a83933dbe3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490795557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_an
d_output.490795557 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/40.kmac_sideload.214026879
Short name T387
Test name
Test status
Simulation time 18463912179 ps
CPU time 163.74 seconds
Started Aug 16 06:09:26 PM PDT 24
Finished Aug 16 06:12:10 PM PDT 24
Peak memory 340344 kb
Host smart-01bb0d62-6910-49bb-b067-e4d98a5f3741
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214026879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.214026879 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_sideload/latest

Test location /workspace/coverage/default/40.kmac_smoke.431419407
Short name T528
Test name
Test status
Simulation time 1807109442 ps
CPU time 36.07 seconds
Started Aug 16 06:09:27 PM PDT 24
Finished Aug 16 06:10:03 PM PDT 24
Peak memory 224772 kb
Host smart-cb78e072-2e09-491d-afa7-1ca613ec1c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431419407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.431419407 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_smoke/latest

Test location /workspace/coverage/default/40.kmac_stress_all.725587659
Short name T351
Test name
Test status
Simulation time 92483204605 ps
CPU time 1347.38 seconds
Started Aug 16 06:09:30 PM PDT 24
Finished Aug 16 06:31:57 PM PDT 24
Peak memory 821768 kb
Host smart-cfb6b4a0-3a6f-4aa1-8e53-4188534fa6ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=725587659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.725587659 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_stress_all/latest

Test location /workspace/coverage/default/41.kmac_alert_test.896325015
Short name T478
Test name
Test status
Simulation time 60872557 ps
CPU time 0.84 seconds
Started Aug 16 06:09:32 PM PDT 24
Finished Aug 16 06:09:33 PM PDT 24
Peak memory 218228 kb
Host smart-33d9262e-b50d-4c5a-a0a4-6704728d2dd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896325015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.896325015 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/41.kmac_alert_test/latest

Test location /workspace/coverage/default/41.kmac_burst_write.56753913
Short name T486
Test name
Test status
Simulation time 5737414470 ps
CPU time 460.3 seconds
Started Aug 16 06:09:30 PM PDT 24
Finished Aug 16 06:17:10 PM PDT 24
Peak memory 234516 kb
Host smart-42e2cb9c-5c62-4272-bb67-3e5701500e59
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56753913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.56753913 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_burst_write/latest

Test location /workspace/coverage/default/41.kmac_entropy_refresh.3202529302
Short name T696
Test name
Test status
Simulation time 112551829351 ps
CPU time 503.98 seconds
Started Aug 16 06:09:36 PM PDT 24
Finished Aug 16 06:18:00 PM PDT 24
Peak memory 548388 kb
Host smart-fc9fa03f-f6a1-4aa8-8494-12de5525285b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202529302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.3
202529302 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/41.kmac_error.1361752067
Short name T635
Test name
Test status
Simulation time 10573523446 ps
CPU time 272.81 seconds
Started Aug 16 06:09:33 PM PDT 24
Finished Aug 16 06:14:06 PM PDT 24
Peak memory 308656 kb
Host smart-0d40e734-1b30-495f-8945-7405d48ff4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361752067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.1361752067 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_error/latest

Test location /workspace/coverage/default/41.kmac_key_error.3948302331
Short name T411
Test name
Test status
Simulation time 1325769086 ps
CPU time 3.33 seconds
Started Aug 16 06:09:31 PM PDT 24
Finished Aug 16 06:09:35 PM PDT 24
Peak memory 226500 kb
Host smart-55b0db3b-1ab9-453f-9026-3b57ccc824ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948302331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.3948302331 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_key_error/latest

Test location /workspace/coverage/default/41.kmac_lc_escalation.3368138639
Short name T49
Test name
Test status
Simulation time 138735457 ps
CPU time 1.36 seconds
Started Aug 16 06:09:30 PM PDT 24
Finished Aug 16 06:09:31 PM PDT 24
Peak memory 226668 kb
Host smart-eea1481f-3aeb-40ef-be5c-3288d9c8aaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368138639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.3368138639 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/41.kmac_lc_escalation/latest

Test location /workspace/coverage/default/41.kmac_long_msg_and_output.1346075208
Short name T245
Test name
Test status
Simulation time 27821251950 ps
CPU time 934.67 seconds
Started Aug 16 06:09:29 PM PDT 24
Finished Aug 16 06:25:04 PM PDT 24
Peak memory 1177556 kb
Host smart-5adecc3a-0d6f-497c-a1c0-3ad36ce2a079
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346075208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_a
nd_output.1346075208 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/41.kmac_sideload.1321447351
Short name T285
Test name
Test status
Simulation time 4832090907 ps
CPU time 376.51 seconds
Started Aug 16 06:09:36 PM PDT 24
Finished Aug 16 06:15:53 PM PDT 24
Peak memory 357816 kb
Host smart-574bc300-f284-47c9-b084-dd7fc3dec5f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321447351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.1321447351 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_sideload/latest

Test location /workspace/coverage/default/41.kmac_smoke.3506710477
Short name T108
Test name
Test status
Simulation time 5581118858 ps
CPU time 40.49 seconds
Started Aug 16 06:09:30 PM PDT 24
Finished Aug 16 06:10:10 PM PDT 24
Peak memory 226860 kb
Host smart-dfb1f095-fedd-409d-8a47-b1505fb6b0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506710477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.3506710477 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_smoke/latest

Test location /workspace/coverage/default/41.kmac_stress_all.1715155461
Short name T416
Test name
Test status
Simulation time 29134739976 ps
CPU time 1144.12 seconds
Started Aug 16 06:09:33 PM PDT 24
Finished Aug 16 06:28:37 PM PDT 24
Peak memory 509488 kb
Host smart-f207aed3-e3d9-4854-aea4-aeeb7aedefec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1715155461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.1715155461 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_stress_all/latest

Test location /workspace/coverage/default/42.kmac_alert_test.2143760196
Short name T256
Test name
Test status
Simulation time 45498300 ps
CPU time 0.81 seconds
Started Aug 16 06:09:48 PM PDT 24
Finished Aug 16 06:09:49 PM PDT 24
Peak memory 217560 kb
Host smart-d4833eed-6a23-4dba-8169-c38742c1ff1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143760196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.2143760196 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_alert_test/latest

Test location /workspace/coverage/default/42.kmac_app.574974417
Short name T382
Test name
Test status
Simulation time 13075652390 ps
CPU time 203.15 seconds
Started Aug 16 06:09:32 PM PDT 24
Finished Aug 16 06:12:56 PM PDT 24
Peak memory 384280 kb
Host smart-41245d7a-a21d-4597-9ee7-d5f24c8bf833
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574974417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.574974417 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/42.kmac_app/latest

Test location /workspace/coverage/default/42.kmac_burst_write.1400223922
Short name T148
Test name
Test status
Simulation time 45345992586 ps
CPU time 1269.44 seconds
Started Aug 16 06:09:31 PM PDT 24
Finished Aug 16 06:30:40 PM PDT 24
Peak memory 258532 kb
Host smart-f7cfa03c-e8c1-4b91-ad50-0d226c3efb98
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400223922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.140022392
2 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_burst_write/latest

Test location /workspace/coverage/default/42.kmac_entropy_refresh.3693970018
Short name T345
Test name
Test status
Simulation time 698516119 ps
CPU time 12.89 seconds
Started Aug 16 06:09:31 PM PDT 24
Finished Aug 16 06:09:44 PM PDT 24
Peak memory 228268 kb
Host smart-b3a35a95-8379-46d4-b482-3ba912946197
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693970018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.3
693970018 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/42.kmac_error.1277169298
Short name T69
Test name
Test status
Simulation time 10844042641 ps
CPU time 190.83 seconds
Started Aug 16 06:09:32 PM PDT 24
Finished Aug 16 06:12:43 PM PDT 24
Peak memory 379128 kb
Host smart-9903dc86-6858-42a5-bddc-746293cbf95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277169298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.1277169298 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_error/latest

Test location /workspace/coverage/default/42.kmac_key_error.1537715546
Short name T291
Test name
Test status
Simulation time 2561390195 ps
CPU time 9.28 seconds
Started Aug 16 06:09:48 PM PDT 24
Finished Aug 16 06:09:57 PM PDT 24
Peak memory 225784 kb
Host smart-5cbbc917-325e-4d95-aec7-2c8d64e1ffe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537715546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.1537715546 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_key_error/latest

Test location /workspace/coverage/default/42.kmac_lc_escalation.2163178993
Short name T511
Test name
Test status
Simulation time 171090371 ps
CPU time 1.46 seconds
Started Aug 16 06:09:43 PM PDT 24
Finished Aug 16 06:09:45 PM PDT 24
Peak memory 226684 kb
Host smart-d62718fa-74d0-4515-9585-7b04c5275d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163178993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.2163178993 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/42.kmac_lc_escalation/latest

Test location /workspace/coverage/default/42.kmac_long_msg_and_output.304017850
Short name T471
Test name
Test status
Simulation time 44396182541 ps
CPU time 3205.35 seconds
Started Aug 16 06:09:31 PM PDT 24
Finished Aug 16 07:02:57 PM PDT 24
Peak memory 1618644 kb
Host smart-30dcbbc8-2ec0-444d-a6f3-4f857a070a08
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304017850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_an
d_output.304017850 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/42.kmac_sideload.3550257776
Short name T551
Test name
Test status
Simulation time 5684728901 ps
CPU time 466.34 seconds
Started Aug 16 06:09:36 PM PDT 24
Finished Aug 16 06:17:23 PM PDT 24
Peak memory 392432 kb
Host smart-8a676c7d-8f16-49f5-a556-352e8bc154b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550257776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.3550257776 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_sideload/latest

Test location /workspace/coverage/default/42.kmac_smoke.1492306419
Short name T508
Test name
Test status
Simulation time 57362128 ps
CPU time 2.22 seconds
Started Aug 16 06:09:30 PM PDT 24
Finished Aug 16 06:09:32 PM PDT 24
Peak memory 219524 kb
Host smart-4abe6d1a-65e0-4b5e-ab97-7185ff837acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492306419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.1492306419 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_smoke/latest

Test location /workspace/coverage/default/42.kmac_stress_all.970096709
Short name T295
Test name
Test status
Simulation time 94993635770 ps
CPU time 1798.6 seconds
Started Aug 16 06:09:40 PM PDT 24
Finished Aug 16 06:39:39 PM PDT 24
Peak memory 1237504 kb
Host smart-f87fe7ad-65da-4dae-93f2-fbe1410fa6ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=970096709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.970096709 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_stress_all/latest

Test location /workspace/coverage/default/43.kmac_alert_test.1050060528
Short name T98
Test name
Test status
Simulation time 51334510 ps
CPU time 0.83 seconds
Started Aug 16 06:09:48 PM PDT 24
Finished Aug 16 06:09:49 PM PDT 24
Peak memory 218268 kb
Host smart-2a64e487-65aa-424c-a801-851a8411462b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050060528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.1050060528 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_alert_test/latest

Test location /workspace/coverage/default/43.kmac_app.869026061
Short name T343
Test name
Test status
Simulation time 16828827768 ps
CPU time 450.34 seconds
Started Aug 16 06:09:41 PM PDT 24
Finished Aug 16 06:17:11 PM PDT 24
Peak memory 550320 kb
Host smart-9a08cab1-17c9-42ce-b7eb-cb0b465d8463
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869026061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.869026061 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/43.kmac_app/latest

Test location /workspace/coverage/default/43.kmac_burst_write.853061865
Short name T693
Test name
Test status
Simulation time 29990799509 ps
CPU time 1466.73 seconds
Started Aug 16 06:09:41 PM PDT 24
Finished Aug 16 06:34:08 PM PDT 24
Peak memory 246412 kb
Host smart-7487635e-8a9a-4df1-ac2c-3273880a55ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853061865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.853061865
+enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_burst_write/latest

Test location /workspace/coverage/default/43.kmac_entropy_refresh.2033480954
Short name T236
Test name
Test status
Simulation time 4787009467 ps
CPU time 112.56 seconds
Started Aug 16 06:09:39 PM PDT 24
Finished Aug 16 06:11:31 PM PDT 24
Peak memory 299728 kb
Host smart-5a64cb71-aa1f-44ab-8fc5-42e5b2a78b61
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033480954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.2
033480954 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/43.kmac_error.1229602334
Short name T293
Test name
Test status
Simulation time 1773247673 ps
CPU time 53.45 seconds
Started Aug 16 06:09:49 PM PDT 24
Finished Aug 16 06:10:43 PM PDT 24
Peak memory 268460 kb
Host smart-59519c64-7ffc-4882-8be8-874e42037ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229602334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.1229602334 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_error/latest

Test location /workspace/coverage/default/43.kmac_key_error.1635138527
Short name T509
Test name
Test status
Simulation time 557725163 ps
CPU time 4.09 seconds
Started Aug 16 06:09:48 PM PDT 24
Finished Aug 16 06:09:52 PM PDT 24
Peak memory 226476 kb
Host smart-e47a6f33-9067-467d-8de9-4940f13a69f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635138527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.1635138527 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_key_error/latest

Test location /workspace/coverage/default/43.kmac_lc_escalation.1672532759
Short name T13
Test name
Test status
Simulation time 92828570 ps
CPU time 1.41 seconds
Started Aug 16 06:09:50 PM PDT 24
Finished Aug 16 06:09:51 PM PDT 24
Peak memory 226628 kb
Host smart-19810230-029d-49bb-9ccd-66d2c29f19e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672532759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.1672532759 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/43.kmac_lc_escalation/latest

Test location /workspace/coverage/default/43.kmac_sideload.1829406145
Short name T667
Test name
Test status
Simulation time 1106308143 ps
CPU time 26.7 seconds
Started Aug 16 06:09:48 PM PDT 24
Finished Aug 16 06:10:15 PM PDT 24
Peak memory 242884 kb
Host smart-01812396-8c8c-48f2-a2ff-268d6b144d43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829406145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.1829406145 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_sideload/latest

Test location /workspace/coverage/default/43.kmac_smoke.3850838943
Short name T36
Test name
Test status
Simulation time 2556343344 ps
CPU time 61.81 seconds
Started Aug 16 06:09:43 PM PDT 24
Finished Aug 16 06:10:45 PM PDT 24
Peak memory 226784 kb
Host smart-97e49b25-5a17-472c-9874-319992344247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850838943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.3850838943 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_smoke/latest

Test location /workspace/coverage/default/43.kmac_stress_all.24299075
Short name T331
Test name
Test status
Simulation time 19068997855 ps
CPU time 332.33 seconds
Started Aug 16 06:09:53 PM PDT 24
Finished Aug 16 06:15:25 PM PDT 24
Peak memory 301508 kb
Host smart-60307380-01d8-4eb3-8f84-226ea609d23c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=24299075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.24299075 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_stress_all/latest

Test location /workspace/coverage/default/44.kmac_alert_test.885726169
Short name T241
Test name
Test status
Simulation time 15275000 ps
CPU time 0.8 seconds
Started Aug 16 06:09:55 PM PDT 24
Finished Aug 16 06:09:56 PM PDT 24
Peak memory 218144 kb
Host smart-cc63699e-a737-4c00-be37-82ef6e1f1107
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885726169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.885726169 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/44.kmac_alert_test/latest

Test location /workspace/coverage/default/44.kmac_app.1789746813
Short name T369
Test name
Test status
Simulation time 4218374834 ps
CPU time 189.33 seconds
Started Aug 16 06:09:47 PM PDT 24
Finished Aug 16 06:12:57 PM PDT 24
Peak memory 290064 kb
Host smart-4e3accc4-4563-4d60-9c02-ce8a087faec1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789746813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.1789746813 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/44.kmac_app/latest

Test location /workspace/coverage/default/44.kmac_burst_write.3436876631
Short name T145
Test name
Test status
Simulation time 233617604406 ps
CPU time 977.29 seconds
Started Aug 16 06:09:48 PM PDT 24
Finished Aug 16 06:26:05 PM PDT 24
Peak memory 253296 kb
Host smart-67ee5a4f-7519-4ff8-862e-53339fd15c3d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436876631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.343687663
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_burst_write/latest

Test location /workspace/coverage/default/44.kmac_entropy_refresh.673653103
Short name T499
Test name
Test status
Simulation time 51028375625 ps
CPU time 303.52 seconds
Started Aug 16 06:09:58 PM PDT 24
Finished Aug 16 06:15:01 PM PDT 24
Peak memory 436572 kb
Host smart-d407c9fe-a2da-47ce-b6b1-7226c4c4f3b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673653103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.67
3653103 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/44.kmac_error.2669897264
Short name T270
Test name
Test status
Simulation time 2190099164 ps
CPU time 57.42 seconds
Started Aug 16 06:09:57 PM PDT 24
Finished Aug 16 06:10:54 PM PDT 24
Peak memory 275904 kb
Host smart-38426068-9861-42be-8f74-c607e85decbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669897264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.2669897264 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_error/latest

Test location /workspace/coverage/default/44.kmac_key_error.1258052385
Short name T575
Test name
Test status
Simulation time 17094096898 ps
CPU time 18.19 seconds
Started Aug 16 06:09:55 PM PDT 24
Finished Aug 16 06:10:13 PM PDT 24
Peak memory 226696 kb
Host smart-57f4c092-fade-4e34-ba32-1b11d1f0ceae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258052385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.1258052385 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_key_error/latest

Test location /workspace/coverage/default/44.kmac_lc_escalation.3940630763
Short name T604
Test name
Test status
Simulation time 112981895 ps
CPU time 1.39 seconds
Started Aug 16 06:09:56 PM PDT 24
Finished Aug 16 06:09:57 PM PDT 24
Peak memory 226684 kb
Host smart-53e699dc-5e71-4441-ac6e-fbdece502eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940630763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.3940630763 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/44.kmac_lc_escalation/latest

Test location /workspace/coverage/default/44.kmac_long_msg_and_output.390580519
Short name T215
Test name
Test status
Simulation time 39123961447 ps
CPU time 1234.2 seconds
Started Aug 16 06:09:50 PM PDT 24
Finished Aug 16 06:30:25 PM PDT 24
Peak memory 815828 kb
Host smart-d050b447-3648-4c7d-bff1-04a5d5452626
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390580519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_an
d_output.390580519 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/44.kmac_sideload.4088446350
Short name T514
Test name
Test status
Simulation time 7335107820 ps
CPU time 47.05 seconds
Started Aug 16 06:09:50 PM PDT 24
Finished Aug 16 06:10:38 PM PDT 24
Peak memory 243008 kb
Host smart-12fad0a4-9afa-4900-ab02-9e4e06a7c57a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088446350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.4088446350 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_sideload/latest

Test location /workspace/coverage/default/44.kmac_smoke.3608522684
Short name T564
Test name
Test status
Simulation time 879481392 ps
CPU time 19.42 seconds
Started Aug 16 06:09:49 PM PDT 24
Finished Aug 16 06:10:08 PM PDT 24
Peak memory 226760 kb
Host smart-51f14b14-9a45-49d4-9141-824dad7c9991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608522684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.3608522684 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_smoke/latest

Test location /workspace/coverage/default/44.kmac_stress_all.2632302528
Short name T335
Test name
Test status
Simulation time 16926909368 ps
CPU time 415.83 seconds
Started Aug 16 06:09:59 PM PDT 24
Finished Aug 16 06:16:55 PM PDT 24
Peak memory 352404 kb
Host smart-c263c143-a2a7-40bb-bc2c-25006d3e088c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2632302528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.2632302528 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_stress_all/latest

Test location /workspace/coverage/default/45.kmac_alert_test.600568917
Short name T384
Test name
Test status
Simulation time 15197357 ps
CPU time 0.83 seconds
Started Aug 16 06:09:59 PM PDT 24
Finished Aug 16 06:10:00 PM PDT 24
Peak memory 218232 kb
Host smart-432204cb-08d7-4a6d-87a6-a8140f296456
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600568917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.600568917 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/45.kmac_alert_test/latest

Test location /workspace/coverage/default/45.kmac_app.1915844881
Short name T292
Test name
Test status
Simulation time 10584530116 ps
CPU time 335.39 seconds
Started Aug 16 06:09:57 PM PDT 24
Finished Aug 16 06:15:33 PM PDT 24
Peak memory 317264 kb
Host smart-1f4e7e6a-7a17-4ae7-b0a4-39a50b4c089e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915844881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.1915844881 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/45.kmac_app/latest

Test location /workspace/coverage/default/45.kmac_burst_write.3192451694
Short name T513
Test name
Test status
Simulation time 12979093275 ps
CPU time 1275.01 seconds
Started Aug 16 06:09:56 PM PDT 24
Finished Aug 16 06:31:11 PM PDT 24
Peak memory 244924 kb
Host smart-6fc27131-334a-4c12-a576-32dc739291e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192451694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.319245169
4 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_burst_write/latest

Test location /workspace/coverage/default/45.kmac_entropy_refresh.3185632550
Short name T173
Test name
Test status
Simulation time 45706581030 ps
CPU time 254 seconds
Started Aug 16 06:09:59 PM PDT 24
Finished Aug 16 06:14:13 PM PDT 24
Peak memory 400832 kb
Host smart-8b42314d-28d2-4aab-aa9a-a5251c9c54d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185632550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.3
185632550 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/45.kmac_error.3400491761
Short name T388
Test name
Test status
Simulation time 3068909381 ps
CPU time 126.71 seconds
Started Aug 16 06:09:56 PM PDT 24
Finished Aug 16 06:12:03 PM PDT 24
Peak memory 267824 kb
Host smart-2de75619-b0a4-48b5-bbeb-f8b8777288eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400491761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.3400491761 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_error/latest

Test location /workspace/coverage/default/45.kmac_key_error.3380805129
Short name T14
Test name
Test status
Simulation time 2627184967 ps
CPU time 6.39 seconds
Started Aug 16 06:09:56 PM PDT 24
Finished Aug 16 06:10:03 PM PDT 24
Peak memory 226680 kb
Host smart-afff2063-cf98-403f-aa50-e482ca80674e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380805129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.3380805129 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_key_error/latest

Test location /workspace/coverage/default/45.kmac_lc_escalation.910904366
Short name T228
Test name
Test status
Simulation time 41536295 ps
CPU time 1.46 seconds
Started Aug 16 06:09:58 PM PDT 24
Finished Aug 16 06:09:59 PM PDT 24
Peak memory 226644 kb
Host smart-14e15142-5f92-4025-9092-f8c344e4f138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910904366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.910904366 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/45.kmac_lc_escalation/latest

Test location /workspace/coverage/default/45.kmac_long_msg_and_output.749534695
Short name T601
Test name
Test status
Simulation time 62335591360 ps
CPU time 1395.1 seconds
Started Aug 16 06:09:57 PM PDT 24
Finished Aug 16 06:33:12 PM PDT 24
Peak memory 1636576 kb
Host smart-d8c45342-01c3-4989-988c-6bdca561bda6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749534695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_an
d_output.749534695 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/45.kmac_sideload.378046159
Short name T504
Test name
Test status
Simulation time 1174649524 ps
CPU time 26.57 seconds
Started Aug 16 06:10:00 PM PDT 24
Finished Aug 16 06:10:27 PM PDT 24
Peak memory 230132 kb
Host smart-ec745161-ac3e-400b-8fba-ecc8a62e911a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378046159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.378046159 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_sideload/latest

Test location /workspace/coverage/default/45.kmac_smoke.1975678363
Short name T229
Test name
Test status
Simulation time 835928856 ps
CPU time 31.85 seconds
Started Aug 16 06:09:57 PM PDT 24
Finished Aug 16 06:10:29 PM PDT 24
Peak memory 226724 kb
Host smart-b1a4afce-cb96-4925-ae4a-37105c9b3f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975678363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.1975678363 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_smoke/latest

Test location /workspace/coverage/default/45.kmac_stress_all.1629686049
Short name T668
Test name
Test status
Simulation time 49895280970 ps
CPU time 1184.85 seconds
Started Aug 16 06:09:58 PM PDT 24
Finished Aug 16 06:29:43 PM PDT 24
Peak memory 647868 kb
Host smart-8c0f346f-10d7-496e-9886-969ea3ff24ec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1629686049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.1629686049 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_stress_all/latest

Test location /workspace/coverage/default/46.kmac_alert_test.1970892069
Short name T655
Test name
Test status
Simulation time 63314828 ps
CPU time 0.91 seconds
Started Aug 16 06:10:08 PM PDT 24
Finished Aug 16 06:10:09 PM PDT 24
Peak memory 218264 kb
Host smart-997df177-e973-4e57-8712-db3579ff6221
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970892069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.1970892069 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_alert_test/latest

Test location /workspace/coverage/default/46.kmac_app.1068100932
Short name T512
Test name
Test status
Simulation time 6335214261 ps
CPU time 208.78 seconds
Started Aug 16 06:09:56 PM PDT 24
Finished Aug 16 06:13:24 PM PDT 24
Peak memory 293140 kb
Host smart-e07099a2-cc49-4114-bc03-452ea8cfbc3a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068100932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.1068100932 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/46.kmac_app/latest

Test location /workspace/coverage/default/46.kmac_burst_write.1214909196
Short name T652
Test name
Test status
Simulation time 49167086068 ps
CPU time 1206.26 seconds
Started Aug 16 06:09:58 PM PDT 24
Finished Aug 16 06:30:04 PM PDT 24
Peak memory 243584 kb
Host smart-a7263496-f658-4222-bfd4-eb9f756dbdf6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214909196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.121490919
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_burst_write/latest

Test location /workspace/coverage/default/46.kmac_entropy_refresh.2354132108
Short name T562
Test name
Test status
Simulation time 22349321777 ps
CPU time 129.4 seconds
Started Aug 16 06:09:57 PM PDT 24
Finished Aug 16 06:12:07 PM PDT 24
Peak memory 310660 kb
Host smart-95e3949d-9b77-4f11-b45d-6ce592a94a59
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354132108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.2
354132108 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/46.kmac_error.410228282
Short name T592
Test name
Test status
Simulation time 8104495151 ps
CPU time 376.41 seconds
Started Aug 16 06:10:09 PM PDT 24
Finished Aug 16 06:16:26 PM PDT 24
Peak memory 346164 kb
Host smart-9a6e7977-5bbb-4cb8-a8b7-7334396b1268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410228282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.410228282 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_error/latest

Test location /workspace/coverage/default/46.kmac_key_error.3593497433
Short name T258
Test name
Test status
Simulation time 921773152 ps
CPU time 7.1 seconds
Started Aug 16 06:10:10 PM PDT 24
Finished Aug 16 06:10:17 PM PDT 24
Peak memory 226484 kb
Host smart-54d18aa3-a037-48d6-a353-320a9e0493c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593497433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.3593497433 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_key_error/latest

Test location /workspace/coverage/default/46.kmac_lc_escalation.2365960033
Short name T481
Test name
Test status
Simulation time 130358577 ps
CPU time 3.93 seconds
Started Aug 16 06:10:11 PM PDT 24
Finished Aug 16 06:10:15 PM PDT 24
Peak memory 226804 kb
Host smart-3ad98cbe-4cb6-458b-b8c9-c303a0b7465b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365960033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.2365960033 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/46.kmac_lc_escalation/latest

Test location /workspace/coverage/default/46.kmac_long_msg_and_output.235324754
Short name T492
Test name
Test status
Simulation time 47818958516 ps
CPU time 1287.59 seconds
Started Aug 16 06:09:54 PM PDT 24
Finished Aug 16 06:31:22 PM PDT 24
Peak memory 902700 kb
Host smart-d41125e3-2028-42b1-80c9-a945e8ba3342
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235324754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_an
d_output.235324754 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/46.kmac_sideload.1243256338
Short name T702
Test name
Test status
Simulation time 11343779503 ps
CPU time 99.52 seconds
Started Aug 16 06:09:57 PM PDT 24
Finished Aug 16 06:11:36 PM PDT 24
Peak memory 291856 kb
Host smart-de25f6a8-9f2b-4be2-9d02-7e42c5b8f928
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243256338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.1243256338 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_sideload/latest

Test location /workspace/coverage/default/46.kmac_smoke.1192836455
Short name T346
Test name
Test status
Simulation time 1881206786 ps
CPU time 33.19 seconds
Started Aug 16 06:09:57 PM PDT 24
Finished Aug 16 06:10:31 PM PDT 24
Peak memory 226692 kb
Host smart-15c32d23-5f20-4016-97e4-e464868c3a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192836455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.1192836455 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_smoke/latest

Test location /workspace/coverage/default/46.kmac_stress_all.3162598622
Short name T299
Test name
Test status
Simulation time 11325583359 ps
CPU time 60.79 seconds
Started Aug 16 06:10:13 PM PDT 24
Finished Aug 16 06:11:14 PM PDT 24
Peak memory 273976 kb
Host smart-e93c4dd8-f150-4f0f-97cf-bbe27addbc06
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3162598622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.3162598622 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_stress_all/latest

Test location /workspace/coverage/default/47.kmac_alert_test.2928264851
Short name T417
Test name
Test status
Simulation time 116178826 ps
CPU time 0.8 seconds
Started Aug 16 06:10:09 PM PDT 24
Finished Aug 16 06:10:10 PM PDT 24
Peak memory 218264 kb
Host smart-42218ca2-6f92-436a-88ff-23a75416b8c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928264851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.2928264851 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_alert_test/latest

Test location /workspace/coverage/default/47.kmac_burst_write.1489876147
Short name T524
Test name
Test status
Simulation time 35254470659 ps
CPU time 1504.22 seconds
Started Aug 16 06:10:12 PM PDT 24
Finished Aug 16 06:35:17 PM PDT 24
Peak memory 265540 kb
Host smart-b2f9d3c7-f5eb-491d-b9c7-1f1f21a17a9a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489876147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.148987614
7 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_burst_write/latest

Test location /workspace/coverage/default/47.kmac_entropy_refresh.1926870098
Short name T381
Test name
Test status
Simulation time 3595021792 ps
CPU time 44 seconds
Started Aug 16 06:10:10 PM PDT 24
Finished Aug 16 06:10:54 PM PDT 24
Peak memory 252472 kb
Host smart-d3527e0b-4467-45d0-b10a-160b2a29ae82
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926870098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.1
926870098 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/47.kmac_error.3468686517
Short name T570
Test name
Test status
Simulation time 78036513292 ps
CPU time 467.37 seconds
Started Aug 16 06:10:09 PM PDT 24
Finished Aug 16 06:17:56 PM PDT 24
Peak memory 566872 kb
Host smart-5510153a-0ffa-477f-8460-c50b4187589f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468686517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.3468686517 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_error/latest

Test location /workspace/coverage/default/47.kmac_key_error.3284521038
Short name T436
Test name
Test status
Simulation time 163748863 ps
CPU time 1.59 seconds
Started Aug 16 06:10:09 PM PDT 24
Finished Aug 16 06:10:11 PM PDT 24
Peak memory 224980 kb
Host smart-da72f76c-f8c0-420b-a327-cd93a6a81a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284521038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.3284521038 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_key_error/latest

Test location /workspace/coverage/default/47.kmac_lc_escalation.2926847829
Short name T82
Test name
Test status
Simulation time 40260807 ps
CPU time 1.67 seconds
Started Aug 16 06:10:10 PM PDT 24
Finished Aug 16 06:10:12 PM PDT 24
Peak memory 226616 kb
Host smart-baae85fc-2444-42a0-a805-a61d8abe68c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926847829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.2926847829 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/47.kmac_lc_escalation/latest

Test location /workspace/coverage/default/47.kmac_long_msg_and_output.816329144
Short name T347
Test name
Test status
Simulation time 403860573389 ps
CPU time 3966.16 seconds
Started Aug 16 06:10:08 PM PDT 24
Finished Aug 16 07:16:15 PM PDT 24
Peak memory 3208340 kb
Host smart-12822372-d86e-446d-b210-ea454a0accb8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816329144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_an
d_output.816329144 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/47.kmac_sideload.763439848
Short name T282
Test name
Test status
Simulation time 11054788408 ps
CPU time 499.81 seconds
Started Aug 16 06:10:10 PM PDT 24
Finished Aug 16 06:18:31 PM PDT 24
Peak memory 391316 kb
Host smart-74afc30d-925c-4337-b0e9-a76b0bead755
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763439848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.763439848 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_sideload/latest

Test location /workspace/coverage/default/47.kmac_smoke.1459042934
Short name T107
Test name
Test status
Simulation time 1419582793 ps
CPU time 42.53 seconds
Started Aug 16 06:10:09 PM PDT 24
Finished Aug 16 06:10:51 PM PDT 24
Peak memory 226740 kb
Host smart-353af16a-89a0-479c-8f5f-661d271105e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459042934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.1459042934 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_smoke/latest

Test location /workspace/coverage/default/47.kmac_stress_all.1551632354
Short name T634
Test name
Test status
Simulation time 17858900871 ps
CPU time 1534.25 seconds
Started Aug 16 06:10:11 PM PDT 24
Finished Aug 16 06:35:45 PM PDT 24
Peak memory 718252 kb
Host smart-7ba3aba2-b80c-41cc-ad43-eb85773674ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1551632354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.1551632354 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_stress_all/latest

Test location /workspace/coverage/default/48.kmac_alert_test.4164022560
Short name T684
Test name
Test status
Simulation time 17642245 ps
CPU time 0.85 seconds
Started Aug 16 06:10:18 PM PDT 24
Finished Aug 16 06:10:19 PM PDT 24
Peak memory 218280 kb
Host smart-c2e36125-0dd6-49c9-9f24-fa8a691d8f1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164022560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.4164022560 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_alert_test/latest

Test location /workspace/coverage/default/48.kmac_app.1833269448
Short name T286
Test name
Test status
Simulation time 15484050979 ps
CPU time 230.14 seconds
Started Aug 16 06:10:27 PM PDT 24
Finished Aug 16 06:14:17 PM PDT 24
Peak memory 400356 kb
Host smart-9e3b4b2a-d606-4e80-b5ea-bfdae3317505
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833269448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.1833269448 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/48.kmac_app/latest

Test location /workspace/coverage/default/48.kmac_burst_write.3489891051
Short name T261
Test name
Test status
Simulation time 4040772636 ps
CPU time 180.95 seconds
Started Aug 16 06:10:28 PM PDT 24
Finished Aug 16 06:13:30 PM PDT 24
Peak memory 230812 kb
Host smart-c1647227-91c8-403a-8f62-7f66a5cb3a5a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489891051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.348989105
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_burst_write/latest

Test location /workspace/coverage/default/48.kmac_error.1601871563
Short name T312
Test name
Test status
Simulation time 1826876864 ps
CPU time 117.13 seconds
Started Aug 16 06:10:19 PM PDT 24
Finished Aug 16 06:12:16 PM PDT 24
Peak memory 275016 kb
Host smart-772b2b6e-dfb2-401f-a547-344ef3df8a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601871563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.1601871563 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_error/latest

Test location /workspace/coverage/default/48.kmac_key_error.2241462796
Short name T301
Test name
Test status
Simulation time 7031863344 ps
CPU time 13.22 seconds
Started Aug 16 06:10:21 PM PDT 24
Finished Aug 16 06:10:34 PM PDT 24
Peak memory 226496 kb
Host smart-f1d113b1-6300-4deb-bc5c-897197f2ab64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241462796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.2241462796 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_key_error/latest

Test location /workspace/coverage/default/48.kmac_lc_escalation.1021401710
Short name T187
Test name
Test status
Simulation time 46479087 ps
CPU time 1.48 seconds
Started Aug 16 06:10:18 PM PDT 24
Finished Aug 16 06:10:20 PM PDT 24
Peak memory 226620 kb
Host smart-67fd94e7-b24b-487f-9c03-2cc38794b97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021401710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.1021401710 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/48.kmac_lc_escalation/latest

Test location /workspace/coverage/default/48.kmac_long_msg_and_output.2916150657
Short name T404
Test name
Test status
Simulation time 10381906843 ps
CPU time 202.1 seconds
Started Aug 16 06:10:20 PM PDT 24
Finished Aug 16 06:13:42 PM PDT 24
Peak memory 321048 kb
Host smart-8727f487-640b-4a86-8460-01d41f4d7bdb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916150657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_a
nd_output.2916150657 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/48.kmac_sideload.4022071109
Short name T510
Test name
Test status
Simulation time 79009013 ps
CPU time 2.39 seconds
Started Aug 16 06:10:19 PM PDT 24
Finished Aug 16 06:10:21 PM PDT 24
Peak memory 226648 kb
Host smart-28822de9-bfb3-46ba-a852-daff7d2cfb32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022071109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.4022071109 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_sideload/latest

Test location /workspace/coverage/default/48.kmac_smoke.3052532646
Short name T344
Test name
Test status
Simulation time 3674177296 ps
CPU time 83.77 seconds
Started Aug 16 06:10:09 PM PDT 24
Finished Aug 16 06:11:33 PM PDT 24
Peak memory 221764 kb
Host smart-d69e9911-3013-44ff-a5ae-f4a710ed3de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052532646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.3052532646 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_smoke/latest

Test location /workspace/coverage/default/48.kmac_stress_all.1156995825
Short name T707
Test name
Test status
Simulation time 66649796667 ps
CPU time 1769.72 seconds
Started Aug 16 06:10:18 PM PDT 24
Finished Aug 16 06:39:48 PM PDT 24
Peak memory 978476 kb
Host smart-5edd4a88-3141-4890-ab2e-306a0022e530
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1156995825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.1156995825 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_stress_all/latest

Test location /workspace/coverage/default/49.kmac_alert_test.47179033
Short name T332
Test name
Test status
Simulation time 17511031 ps
CPU time 0.85 seconds
Started Aug 16 06:10:30 PM PDT 24
Finished Aug 16 06:10:31 PM PDT 24
Peak memory 218220 kb
Host smart-e6b93382-1884-41a8-9ada-04c7b2ba6578
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47179033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.47179033 +enable_mas
king=1 +sw_key_masked=0
Directory /workspace/49.kmac_alert_test/latest

Test location /workspace/coverage/default/49.kmac_app.981244640
Short name T521
Test name
Test status
Simulation time 158880141 ps
CPU time 2.33 seconds
Started Aug 16 06:10:18 PM PDT 24
Finished Aug 16 06:10:20 PM PDT 24
Peak memory 226612 kb
Host smart-e1950d8b-06e3-46ca-a7c1-9813e1f874c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981244640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.981244640 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/49.kmac_app/latest

Test location /workspace/coverage/default/49.kmac_burst_write.959666913
Short name T146
Test name
Test status
Simulation time 15329914580 ps
CPU time 825.82 seconds
Started Aug 16 06:10:16 PM PDT 24
Finished Aug 16 06:24:02 PM PDT 24
Peak memory 249980 kb
Host smart-9dcb9338-5fe5-495a-afe2-1e137aeeccdd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959666913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.959666913
+enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_burst_write/latest

Test location /workspace/coverage/default/49.kmac_entropy_refresh.564606792
Short name T676
Test name
Test status
Simulation time 3051873669 ps
CPU time 124.43 seconds
Started Aug 16 06:10:15 PM PDT 24
Finished Aug 16 06:12:20 PM PDT 24
Peak memory 262992 kb
Host smart-2a19eea8-fcf3-4e89-af40-01636a4882e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564606792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.56
4606792 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/49.kmac_error.140424811
Short name T20
Test name
Test status
Simulation time 9634490734 ps
CPU time 280.97 seconds
Started Aug 16 06:10:27 PM PDT 24
Finished Aug 16 06:15:08 PM PDT 24
Peak memory 442280 kb
Host smart-54e050d0-ea83-4039-b004-f1637c924d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140424811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.140424811 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_error/latest

Test location /workspace/coverage/default/49.kmac_key_error.3481579640
Short name T103
Test name
Test status
Simulation time 1252350648 ps
CPU time 3.27 seconds
Started Aug 16 06:10:27 PM PDT 24
Finished Aug 16 06:10:30 PM PDT 24
Peak memory 226556 kb
Host smart-0936d34e-c249-457e-9e01-30f0f0293391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481579640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.3481579640 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_key_error/latest

Test location /workspace/coverage/default/49.kmac_lc_escalation.2010569887
Short name T372
Test name
Test status
Simulation time 860090867 ps
CPU time 46.6 seconds
Started Aug 16 06:10:28 PM PDT 24
Finished Aug 16 06:11:14 PM PDT 24
Peak memory 248040 kb
Host smart-72e2ba94-0d3a-4988-a1eb-b51e4c576e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010569887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.2010569887 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/49.kmac_lc_escalation/latest

Test location /workspace/coverage/default/49.kmac_long_msg_and_output.1722097188
Short name T607
Test name
Test status
Simulation time 39158723226 ps
CPU time 783.62 seconds
Started Aug 16 06:10:30 PM PDT 24
Finished Aug 16 06:23:34 PM PDT 24
Peak memory 1129340 kb
Host smart-f4a2bba9-18ed-4867-ad40-4a7b8028e4b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722097188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_a
nd_output.1722097188 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/49.kmac_sideload.229578669
Short name T201
Test name
Test status
Simulation time 125383321892 ps
CPU time 516.69 seconds
Started Aug 16 06:10:19 PM PDT 24
Finished Aug 16 06:18:56 PM PDT 24
Peak memory 598736 kb
Host smart-db624ae5-6c44-4c11-9826-6e3ec24e20f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229578669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.229578669 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_sideload/latest

Test location /workspace/coverage/default/49.kmac_smoke.1691263030
Short name T129
Test name
Test status
Simulation time 14814297232 ps
CPU time 67.65 seconds
Started Aug 16 06:10:21 PM PDT 24
Finished Aug 16 06:11:28 PM PDT 24
Peak memory 223528 kb
Host smart-7b8da1c0-63db-4a09-a429-1082c67b043c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691263030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.1691263030 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_smoke/latest

Test location /workspace/coverage/default/49.kmac_stress_all.864757030
Short name T677
Test name
Test status
Simulation time 1880217717 ps
CPU time 14.12 seconds
Started Aug 16 06:10:37 PM PDT 24
Finished Aug 16 06:10:51 PM PDT 24
Peak memory 225264 kb
Host smart-d48aab76-3e17-4d77-a004-0a4e9c278ba3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=864757030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.864757030 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all/latest

Test location /workspace/coverage/default/5.kmac_alert_test.1504434194
Short name T410
Test name
Test status
Simulation time 32723828 ps
CPU time 0.83 seconds
Started Aug 16 06:06:17 PM PDT 24
Finished Aug 16 06:06:18 PM PDT 24
Peak memory 218168 kb
Host smart-2a0e34d2-a96d-45bf-a8aa-2fb1e28463e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504434194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.1504434194 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_alert_test/latest

Test location /workspace/coverage/default/5.kmac_app.1907803136
Short name T424
Test name
Test status
Simulation time 2789927973 ps
CPU time 60.39 seconds
Started Aug 16 06:06:19 PM PDT 24
Finished Aug 16 06:07:19 PM PDT 24
Peak memory 272300 kb
Host smart-25f847af-d511-4627-bf6b-380b71cff7f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907803136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.1907803136 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/5.kmac_app/latest

Test location /workspace/coverage/default/5.kmac_app_with_partial_data.867016047
Short name T451
Test name
Test status
Simulation time 12422543776 ps
CPU time 74.61 seconds
Started Aug 16 06:06:22 PM PDT 24
Finished Aug 16 06:07:37 PM PDT 24
Peak memory 275812 kb
Host smart-5c26d77d-91d1-4467-beeb-73fca4dd6af2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867016047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_parti
al_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_part
ial_data.867016047 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/5.kmac_burst_write.1992135195
Short name T623
Test name
Test status
Simulation time 1384662144 ps
CPU time 121.05 seconds
Started Aug 16 06:06:09 PM PDT 24
Finished Aug 16 06:08:10 PM PDT 24
Peak memory 234480 kb
Host smart-bce5097a-b5cf-4da0-be30-de619c976989
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992135195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.1992135195
+enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_burst_write/latest

Test location /workspace/coverage/default/5.kmac_edn_timeout_error.2106555139
Short name T395
Test name
Test status
Simulation time 631571054 ps
CPU time 49.15 seconds
Started Aug 16 06:06:24 PM PDT 24
Finished Aug 16 06:07:13 PM PDT 24
Peak memory 227960 kb
Host smart-d8f639ac-5be6-4e1e-b45e-aa3700bf2ce7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2106555139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.2106555139 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_mode_error.575540256
Short name T556
Test name
Test status
Simulation time 24691408 ps
CPU time 0.96 seconds
Started Aug 16 06:06:21 PM PDT 24
Finished Aug 16 06:06:22 PM PDT 24
Peak memory 220180 kb
Host smart-8925cd55-7f3f-4650-8efe-36b03dd22908
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=575540256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.575540256 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_ready_error.3736888472
Short name T597
Test name
Test status
Simulation time 9394674833 ps
CPU time 28.98 seconds
Started Aug 16 06:06:24 PM PDT 24
Finished Aug 16 06:06:53 PM PDT 24
Peak memory 221408 kb
Host smart-25457ea0-29ae-4b00-9d9a-97ec6434cc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736888472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.3736888472 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_refresh.493452085
Short name T373
Test name
Test status
Simulation time 7996059035 ps
CPU time 312.23 seconds
Started Aug 16 06:06:24 PM PDT 24
Finished Aug 16 06:11:36 PM PDT 24
Peak memory 310408 kb
Host smart-99c86ce2-6b3e-4ae4-ab7a-dd1e28db67cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493452085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.493
452085 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/5.kmac_error.449758296
Short name T133
Test name
Test status
Simulation time 6734334490 ps
CPU time 117.71 seconds
Started Aug 16 06:06:19 PM PDT 24
Finished Aug 16 06:08:17 PM PDT 24
Peak memory 323816 kb
Host smart-0eaa92f3-8b00-428d-88c0-635ec6a294f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449758296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.449758296 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_error/latest

Test location /workspace/coverage/default/5.kmac_key_error.3241686602
Short name T360
Test name
Test status
Simulation time 1303664713 ps
CPU time 5.52 seconds
Started Aug 16 06:06:15 PM PDT 24
Finished Aug 16 06:06:21 PM PDT 24
Peak memory 226516 kb
Host smart-12d2aa8c-6f07-4444-8a3f-a1e2262c3511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241686602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.3241686602 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_key_error/latest

Test location /workspace/coverage/default/5.kmac_lc_escalation.2072073651
Short name T664
Test name
Test status
Simulation time 106527841 ps
CPU time 1.37 seconds
Started Aug 16 06:06:16 PM PDT 24
Finished Aug 16 06:06:17 PM PDT 24
Peak memory 226708 kb
Host smart-5923fdd4-1f14-42c8-b2d9-966230dfd5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072073651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.2072073651 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/5.kmac_lc_escalation/latest

Test location /workspace/coverage/default/5.kmac_sideload.3071575646
Short name T110
Test name
Test status
Simulation time 3503553437 ps
CPU time 60.08 seconds
Started Aug 16 06:06:12 PM PDT 24
Finished Aug 16 06:07:12 PM PDT 24
Peak memory 269724 kb
Host smart-8c88cf2e-517e-496d-92bb-864114ada6b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071575646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.3071575646 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_sideload/latest

Test location /workspace/coverage/default/5.kmac_smoke.2078369874
Short name T654
Test name
Test status
Simulation time 15860826283 ps
CPU time 42.25 seconds
Started Aug 16 06:06:08 PM PDT 24
Finished Aug 16 06:06:50 PM PDT 24
Peak memory 226664 kb
Host smart-5ba35f03-3484-431b-bf45-d08ccc8b355f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078369874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.2078369874 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_smoke/latest

Test location /workspace/coverage/default/5.kmac_stress_all.2723558581
Short name T533
Test name
Test status
Simulation time 62904070871 ps
CPU time 2151.43 seconds
Started Aug 16 06:06:24 PM PDT 24
Finished Aug 16 06:42:16 PM PDT 24
Peak memory 1400436 kb
Host smart-35790531-a41c-47e8-a44e-22bcb189c9a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2723558581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.2723558581 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all/latest

Test location /workspace/coverage/default/6.kmac_alert_test.721287324
Short name T695
Test name
Test status
Simulation time 62538640 ps
CPU time 0.86 seconds
Started Aug 16 06:06:17 PM PDT 24
Finished Aug 16 06:06:18 PM PDT 24
Peak memory 218328 kb
Host smart-a73436f9-cd79-47f6-8de4-55dc6036c448
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721287324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.721287324 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/6.kmac_alert_test/latest

Test location /workspace/coverage/default/6.kmac_app.205824144
Short name T685
Test name
Test status
Simulation time 746603431 ps
CPU time 56.44 seconds
Started Aug 16 06:06:18 PM PDT 24
Finished Aug 16 06:07:15 PM PDT 24
Peak memory 239560 kb
Host smart-490f27c5-8f65-4b3d-b2eb-22bafeed58f4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205824144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.205824144 +enable_masking=1
+sw_key_masked=0
Directory /workspace/6.kmac_app/latest

Test location /workspace/coverage/default/6.kmac_app_with_partial_data.3590753067
Short name T362
Test name
Test status
Simulation time 11688233130 ps
CPU time 319.36 seconds
Started Aug 16 06:06:22 PM PDT 24
Finished Aug 16 06:11:41 PM PDT 24
Peak memory 452536 kb
Host smart-80f8c3e2-ad8a-4506-8f80-69311564aca8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590753067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_par
tial_data.3590753067 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/6.kmac_burst_write.1129928793
Short name T252
Test name
Test status
Simulation time 89349972033 ps
CPU time 944.36 seconds
Started Aug 16 06:06:18 PM PDT 24
Finished Aug 16 06:22:02 PM PDT 24
Peak memory 254628 kb
Host smart-e5be90d5-50d5-4c07-a046-876c6b2e80f0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129928793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.1129928793
+enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_burst_write/latest

Test location /workspace/coverage/default/6.kmac_edn_timeout_error.1085398729
Short name T501
Test name
Test status
Simulation time 18583515 ps
CPU time 0.93 seconds
Started Aug 16 06:06:16 PM PDT 24
Finished Aug 16 06:06:17 PM PDT 24
Peak memory 218092 kb
Host smart-a21c65a5-beaf-4001-97c8-0d74aa5c58de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1085398729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.1085398729 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_mode_error.2642133248
Short name T532
Test name
Test status
Simulation time 22607479 ps
CPU time 0.78 seconds
Started Aug 16 06:06:15 PM PDT 24
Finished Aug 16 06:06:16 PM PDT 24
Peak memory 220524 kb
Host smart-c7f0f599-d5d1-42c4-938c-e0049b2a385f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2642133248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.2642133248 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_ready_error.518851345
Short name T523
Test name
Test status
Simulation time 27721852513 ps
CPU time 64.55 seconds
Started Aug 16 06:06:19 PM PDT 24
Finished Aug 16 06:07:23 PM PDT 24
Peak memory 224308 kb
Host smart-fc7af403-2b5d-4f7b-af73-9b85f4190f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518851345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.518851345 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_refresh.2194723732
Short name T309
Test name
Test status
Simulation time 28812164785 ps
CPU time 243.88 seconds
Started Aug 16 06:06:18 PM PDT 24
Finished Aug 16 06:10:22 PM PDT 24
Peak memory 416716 kb
Host smart-2de90eb1-0db4-4111-99d8-39c0bb70ade2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194723732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.21
94723732 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/6.kmac_key_error.1115678487
Short name T605
Test name
Test status
Simulation time 64599055 ps
CPU time 1.26 seconds
Started Aug 16 06:06:16 PM PDT 24
Finished Aug 16 06:06:17 PM PDT 24
Peak memory 226196 kb
Host smart-62713199-a651-497a-8bcf-5800ca7fcee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115678487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.1115678487 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_key_error/latest

Test location /workspace/coverage/default/6.kmac_lc_escalation.4123348023
Short name T567
Test name
Test status
Simulation time 137899414 ps
CPU time 1.37 seconds
Started Aug 16 06:06:19 PM PDT 24
Finished Aug 16 06:06:20 PM PDT 24
Peak memory 226604 kb
Host smart-1a9813d5-35e9-479a-bed0-2e1a5edfb1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123348023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.4123348023 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/6.kmac_lc_escalation/latest

Test location /workspace/coverage/default/6.kmac_long_msg_and_output.3073765695
Short name T402
Test name
Test status
Simulation time 78939440483 ps
CPU time 3715.44 seconds
Started Aug 16 06:06:16 PM PDT 24
Finished Aug 16 07:08:12 PM PDT 24
Peak memory 3087024 kb
Host smart-d79624cf-3b50-4c1f-858f-134f1e277b27
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073765695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_an
d_output.3073765695 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/6.kmac_mubi.54510955
Short name T502
Test name
Test status
Simulation time 8143716617 ps
CPU time 204.96 seconds
Started Aug 16 06:06:18 PM PDT 24
Finished Aug 16 06:09:43 PM PDT 24
Peak memory 384936 kb
Host smart-02a2226f-d33d-444a-9c3f-7b2f83b65da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54510955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.54510955 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_mubi/latest

Test location /workspace/coverage/default/6.kmac_sideload.545849184
Short name T327
Test name
Test status
Simulation time 5422550415 ps
CPU time 70.94 seconds
Started Aug 16 06:06:22 PM PDT 24
Finished Aug 16 06:07:33 PM PDT 24
Peak memory 283236 kb
Host smart-0b27809a-cd60-4dca-b422-3805d4196b8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545849184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.545849184 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_sideload/latest

Test location /workspace/coverage/default/6.kmac_smoke.3684632856
Short name T352
Test name
Test status
Simulation time 4959684717 ps
CPU time 57.3 seconds
Started Aug 16 06:06:16 PM PDT 24
Finished Aug 16 06:07:13 PM PDT 24
Peak memory 226812 kb
Host smart-915f69d4-6a8c-4545-9df4-e4c487d2ee9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684632856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.3684632856 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_smoke/latest

Test location /workspace/coverage/default/7.kmac_alert_test.3833120350
Short name T665
Test name
Test status
Simulation time 46806074 ps
CPU time 0.83 seconds
Started Aug 16 06:06:27 PM PDT 24
Finished Aug 16 06:06:28 PM PDT 24
Peak memory 218240 kb
Host smart-a71da05e-12b5-4fdb-bb6d-796ffc128ef9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833120350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.3833120350 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_alert_test/latest

Test location /workspace/coverage/default/7.kmac_app.3501120438
Short name T407
Test name
Test status
Simulation time 22320728765 ps
CPU time 299.71 seconds
Started Aug 16 06:06:16 PM PDT 24
Finished Aug 16 06:11:15 PM PDT 24
Peak memory 418844 kb
Host smart-6e2a1960-e05e-49c3-b48b-a48836180f6c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501120438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.3501120438 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/7.kmac_app/latest

Test location /workspace/coverage/default/7.kmac_app_with_partial_data.611550374
Short name T625
Test name
Test status
Simulation time 7714690639 ps
CPU time 147.69 seconds
Started Aug 16 06:06:21 PM PDT 24
Finished Aug 16 06:08:48 PM PDT 24
Peak memory 336448 kb
Host smart-518a4a13-6eb3-4732-b5df-2cb751195f63
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611550374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_parti
al_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_part
ial_data.611550374 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/7.kmac_burst_write.2923327530
Short name T227
Test name
Test status
Simulation time 7367949056 ps
CPU time 788.85 seconds
Started Aug 16 06:06:16 PM PDT 24
Finished Aug 16 06:19:25 PM PDT 24
Peak memory 243320 kb
Host smart-5a8d1d80-3b03-47d9-a895-fe7a934740e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923327530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.2923327530
+enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_burst_write/latest

Test location /workspace/coverage/default/7.kmac_edn_timeout_error.657505932
Short name T466
Test name
Test status
Simulation time 74930907 ps
CPU time 0.82 seconds
Started Aug 16 06:06:16 PM PDT 24
Finished Aug 16 06:06:17 PM PDT 24
Peak memory 218180 kb
Host smart-7ba6c2a2-cc56-47a3-a6a8-35f97eac9ac9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=657505932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.657505932 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_mode_error.3666005876
Short name T522
Test name
Test status
Simulation time 7157433232 ps
CPU time 26.11 seconds
Started Aug 16 06:06:26 PM PDT 24
Finished Aug 16 06:06:52 PM PDT 24
Peak memory 226544 kb
Host smart-b024631c-4168-46bd-826e-bc6c9380c3dd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3666005876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.3666005876 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_ready_error.2239787334
Short name T541
Test name
Test status
Simulation time 5812188758 ps
CPU time 24.81 seconds
Started Aug 16 06:06:24 PM PDT 24
Finished Aug 16 06:06:49 PM PDT 24
Peak memory 221572 kb
Host smart-bd4ef0f1-8e11-4fc4-a026-02fec7640436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239787334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.2239787334 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_refresh.4021220910
Short name T444
Test name
Test status
Simulation time 8866177107 ps
CPU time 396.32 seconds
Started Aug 16 06:06:19 PM PDT 24
Finished Aug 16 06:12:55 PM PDT 24
Peak memory 345744 kb
Host smart-b4438b98-f3d5-4527-a669-cd455be6364d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021220910 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.40
21220910 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/7.kmac_error.3142655884
Short name T267
Test name
Test status
Simulation time 23910103498 ps
CPU time 173.65 seconds
Started Aug 16 06:06:19 PM PDT 24
Finished Aug 16 06:09:13 PM PDT 24
Peak memory 341448 kb
Host smart-08bf771e-93ac-44d0-b93f-b3cec19be155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142655884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.3142655884 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_error/latest

Test location /workspace/coverage/default/7.kmac_key_error.1386116859
Short name T439
Test name
Test status
Simulation time 1559595604 ps
CPU time 3.85 seconds
Started Aug 16 06:06:17 PM PDT 24
Finished Aug 16 06:06:21 PM PDT 24
Peak memory 226636 kb
Host smart-27accb50-d3be-49fb-a20d-265a0ba5dce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386116859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.1386116859 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_key_error/latest

Test location /workspace/coverage/default/7.kmac_lc_escalation.1007939345
Short name T428
Test name
Test status
Simulation time 64189308 ps
CPU time 1.38 seconds
Started Aug 16 06:06:26 PM PDT 24
Finished Aug 16 06:06:27 PM PDT 24
Peak memory 226660 kb
Host smart-494563bb-71c7-40d6-a6fd-f72100bd1175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007939345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.1007939345 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/7.kmac_lc_escalation/latest

Test location /workspace/coverage/default/7.kmac_mubi.508501004
Short name T608
Test name
Test status
Simulation time 7320042689 ps
CPU time 117.26 seconds
Started Aug 16 06:06:15 PM PDT 24
Finished Aug 16 06:08:12 PM PDT 24
Peak memory 318316 kb
Host smart-4b09f5d1-3658-4bfe-8fdd-607696d8975b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508501004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.508501004 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_mubi/latest

Test location /workspace/coverage/default/7.kmac_sideload.3656380099
Short name T637
Test name
Test status
Simulation time 41793278730 ps
CPU time 546.09 seconds
Started Aug 16 06:06:18 PM PDT 24
Finished Aug 16 06:15:24 PM PDT 24
Peak memory 628488 kb
Host smart-f7d41668-8214-4593-bdd1-169a607f582f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656380099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.3656380099 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_sideload/latest

Test location /workspace/coverage/default/7.kmac_smoke.1211677378
Short name T218
Test name
Test status
Simulation time 4057020125 ps
CPU time 87.33 seconds
Started Aug 16 06:06:19 PM PDT 24
Finished Aug 16 06:07:46 PM PDT 24
Peak memory 227640 kb
Host smart-a2eae5c9-14c8-4a5c-83fc-da5c3922704b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211677378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.1211677378 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_smoke/latest

Test location /workspace/coverage/default/7.kmac_stress_all.3668507069
Short name T186
Test name
Test status
Simulation time 1649154394 ps
CPU time 17.1 seconds
Started Aug 16 06:06:24 PM PDT 24
Finished Aug 16 06:06:42 PM PDT 24
Peak memory 232204 kb
Host smart-6b4cc049-8795-48ca-92c7-9fa49f19a95e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3668507069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.3668507069 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all/latest

Test location /workspace/coverage/default/8.kmac_alert_test.3306323444
Short name T461
Test name
Test status
Simulation time 28016313 ps
CPU time 0.86 seconds
Started Aug 16 06:06:36 PM PDT 24
Finished Aug 16 06:06:37 PM PDT 24
Peak memory 218112 kb
Host smart-f6a7411a-1e51-4669-88e1-71b584fe6c55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306323444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.3306323444 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_alert_test/latest

Test location /workspace/coverage/default/8.kmac_app.2352540855
Short name T19
Test name
Test status
Simulation time 46344038013 ps
CPU time 383.53 seconds
Started Aug 16 06:06:26 PM PDT 24
Finished Aug 16 06:12:50 PM PDT 24
Peak memory 496788 kb
Host smart-f52143b0-7a91-4517-a44d-deef6f2a05e3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352540855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.2352540855 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/8.kmac_app/latest

Test location /workspace/coverage/default/8.kmac_app_with_partial_data.3291970790
Short name T500
Test name
Test status
Simulation time 7632539125 ps
CPU time 192.43 seconds
Started Aug 16 06:06:29 PM PDT 24
Finished Aug 16 06:09:42 PM PDT 24
Peak memory 352376 kb
Host smart-82ab938a-fa2e-4214-a2cf-4ea1b6b56208
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291970790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_par
tial_data.3291970790 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/8.kmac_burst_write.1333933413
Short name T568
Test name
Test status
Simulation time 122378767970 ps
CPU time 1389.29 seconds
Started Aug 16 06:06:26 PM PDT 24
Finished Aug 16 06:29:36 PM PDT 24
Peak memory 263384 kb
Host smart-199cd0eb-4939-4950-8636-f6eebf83c279
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333933413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.1333933413
+enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_burst_write/latest

Test location /workspace/coverage/default/8.kmac_edn_timeout_error.1096860451
Short name T366
Test name
Test status
Simulation time 786184082 ps
CPU time 25.14 seconds
Started Aug 16 06:06:27 PM PDT 24
Finished Aug 16 06:06:53 PM PDT 24
Peak memory 227116 kb
Host smart-89d2346a-f437-48d1-a107-0b838b6da64c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1096860451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.1096860451 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_mode_error.381961112
Short name T487
Test name
Test status
Simulation time 12798692 ps
CPU time 0.82 seconds
Started Aug 16 06:06:27 PM PDT 24
Finished Aug 16 06:06:27 PM PDT 24
Peak memory 220280 kb
Host smart-5216b016-9eec-4e57-8516-6683048026df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=381961112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.381961112 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_ready_error.3522658657
Short name T365
Test name
Test status
Simulation time 16482291370 ps
CPU time 34.79 seconds
Started Aug 16 06:06:26 PM PDT 24
Finished Aug 16 06:07:01 PM PDT 24
Peak memory 223332 kb
Host smart-e9047170-0738-4d06-91b2-ebe5ccc2f5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522658657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.3522658657 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_refresh.3568896574
Short name T272
Test name
Test status
Simulation time 53988921836 ps
CPU time 403.95 seconds
Started Aug 16 06:06:27 PM PDT 24
Finished Aug 16 06:13:12 PM PDT 24
Peak memory 497744 kb
Host smart-3601f996-b711-405f-a77e-22362c0daa8a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568896574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.35
68896574 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/8.kmac_error.1484079766
Short name T115
Test name
Test status
Simulation time 5599967207 ps
CPU time 106.45 seconds
Started Aug 16 06:06:25 PM PDT 24
Finished Aug 16 06:08:11 PM PDT 24
Peak memory 276064 kb
Host smart-07a92183-f628-442f-8871-2282aca0d443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484079766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.1484079766 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_error/latest

Test location /workspace/coverage/default/8.kmac_key_error.3789229247
Short name T649
Test name
Test status
Simulation time 1736604214 ps
CPU time 12.65 seconds
Started Aug 16 06:06:26 PM PDT 24
Finished Aug 16 06:06:38 PM PDT 24
Peak memory 226644 kb
Host smart-bca9ac0b-bffe-4f00-a1c5-b8c986a126fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789229247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.3789229247 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_key_error/latest

Test location /workspace/coverage/default/8.kmac_lc_escalation.176124517
Short name T638
Test name
Test status
Simulation time 52570474 ps
CPU time 1.37 seconds
Started Aug 16 06:06:26 PM PDT 24
Finished Aug 16 06:06:27 PM PDT 24
Peak memory 226548 kb
Host smart-93f78bce-7efe-49e9-b741-a65a82010b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176124517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.176124517 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_lc_escalation/latest

Test location /workspace/coverage/default/8.kmac_long_msg_and_output.385824784
Short name T587
Test name
Test status
Simulation time 29743147896 ps
CPU time 2005.29 seconds
Started Aug 16 06:06:25 PM PDT 24
Finished Aug 16 06:39:50 PM PDT 24
Peak memory 1064964 kb
Host smart-285ba59e-5917-41ed-b204-eafb45c332bd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385824784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_and
_output.385824784 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/8.kmac_mubi.666676658
Short name T423
Test name
Test status
Simulation time 1631380097 ps
CPU time 28.36 seconds
Started Aug 16 06:06:25 PM PDT 24
Finished Aug 16 06:06:53 PM PDT 24
Peak memory 230588 kb
Host smart-5ff05e88-ade5-4cf5-b752-9214fbf6e2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666676658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.666676658 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_mubi/latest

Test location /workspace/coverage/default/8.kmac_sideload.494846949
Short name T560
Test name
Test status
Simulation time 3943178121 ps
CPU time 313.41 seconds
Started Aug 16 06:06:25 PM PDT 24
Finished Aug 16 06:11:38 PM PDT 24
Peak memory 335276 kb
Host smart-a2d79f89-2f6d-4c40-9912-f86cb81821f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494846949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.494846949 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_sideload/latest

Test location /workspace/coverage/default/8.kmac_smoke.117979944
Short name T469
Test name
Test status
Simulation time 2697139307 ps
CPU time 77.58 seconds
Started Aug 16 06:06:24 PM PDT 24
Finished Aug 16 06:07:42 PM PDT 24
Peak memory 226896 kb
Host smart-28ae0c2a-dff1-4613-a79f-ddc55dd11aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117979944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.117979944 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_smoke/latest

Test location /workspace/coverage/default/8.kmac_stress_all.509231552
Short name T611
Test name
Test status
Simulation time 61135461141 ps
CPU time 977.67 seconds
Started Aug 16 06:06:27 PM PDT 24
Finished Aug 16 06:22:44 PM PDT 24
Peak memory 398520 kb
Host smart-4c4365f1-99a5-42e1-b417-4a11b890e4e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=509231552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.509231552 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all/latest

Test location /workspace/coverage/default/9.kmac_alert_test.916284857
Short name T626
Test name
Test status
Simulation time 70414195 ps
CPU time 0.87 seconds
Started Aug 16 06:06:44 PM PDT 24
Finished Aug 16 06:06:46 PM PDT 24
Peak memory 218220 kb
Host smart-7f02ec06-4f85-433e-93f3-cb2f8452e773
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916284857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.916284857 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/9.kmac_alert_test/latest

Test location /workspace/coverage/default/9.kmac_app.2485356711
Short name T547
Test name
Test status
Simulation time 14052984517 ps
CPU time 86.4 seconds
Started Aug 16 06:06:44 PM PDT 24
Finished Aug 16 06:08:11 PM PDT 24
Peak memory 292796 kb
Host smart-1b942594-877e-47ef-81af-4d709942d9ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485356711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.2485356711 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/9.kmac_app/latest

Test location /workspace/coverage/default/9.kmac_app_with_partial_data.3943867224
Short name T176
Test name
Test status
Simulation time 61606661405 ps
CPU time 335.33 seconds
Started Aug 16 06:06:44 PM PDT 24
Finished Aug 16 06:12:20 PM PDT 24
Peak memory 325280 kb
Host smart-60655657-961a-4374-811a-6458a493ee53
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943867224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_par
tial_data.3943867224 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/9.kmac_burst_write.1603172920
Short name T354
Test name
Test status
Simulation time 4807600878 ps
CPU time 271.89 seconds
Started Aug 16 06:06:34 PM PDT 24
Finished Aug 16 06:11:06 PM PDT 24
Peak memory 231220 kb
Host smart-ccda1387-8420-421b-9344-daf55b4dcfb5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603172920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.1603172920
+enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_burst_write/latest

Test location /workspace/coverage/default/9.kmac_edn_timeout_error.4098464617
Short name T74
Test name
Test status
Simulation time 94120519 ps
CPU time 1 seconds
Started Aug 16 06:06:34 PM PDT 24
Finished Aug 16 06:06:35 PM PDT 24
Peak memory 218180 kb
Host smart-dc46fafe-4eee-4861-b460-c4a22da22433
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4098464617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.4098464617 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_mode_error.3965158463
Short name T21
Test name
Test status
Simulation time 2131455425 ps
CPU time 28.77 seconds
Started Aug 16 06:06:44 PM PDT 24
Finished Aug 16 06:07:13 PM PDT 24
Peak memory 226360 kb
Host smart-f7a8000c-0812-46d5-ae4c-b083da8fca71
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3965158463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.3965158463 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_ready_error.1578628666
Short name T6
Test name
Test status
Simulation time 8748281330 ps
CPU time 50.81 seconds
Started Aug 16 06:06:36 PM PDT 24
Finished Aug 16 06:07:26 PM PDT 24
Peak memory 224140 kb
Host smart-673ad797-ead9-4947-8300-50b5f994f3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578628666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.1578628666 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_refresh.1788867367
Short name T450
Test name
Test status
Simulation time 6632069873 ps
CPU time 83.7 seconds
Started Aug 16 06:06:34 PM PDT 24
Finished Aug 16 06:07:57 PM PDT 24
Peak memory 248484 kb
Host smart-5f5dd5ab-ea4c-48d1-a3a2-304e2c493a12
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788867367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.17
88867367 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/9.kmac_error.2891485057
Short name T484
Test name
Test status
Simulation time 9620145777 ps
CPU time 203.21 seconds
Started Aug 16 06:06:34 PM PDT 24
Finished Aug 16 06:09:57 PM PDT 24
Peak memory 306996 kb
Host smart-9e0c8c45-37c9-4ce1-b83e-382028277d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891485057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.2891485057 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_error/latest

Test location /workspace/coverage/default/9.kmac_key_error.357269640
Short name T465
Test name
Test status
Simulation time 745198105 ps
CPU time 4.92 seconds
Started Aug 16 06:06:33 PM PDT 24
Finished Aug 16 06:06:38 PM PDT 24
Peak memory 226652 kb
Host smart-8ddaf924-4a6c-4ae5-9775-66d205b98984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357269640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.357269640 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_key_error/latest

Test location /workspace/coverage/default/9.kmac_long_msg_and_output.2750090049
Short name T283
Test name
Test status
Simulation time 114936886322 ps
CPU time 3910.6 seconds
Started Aug 16 06:06:38 PM PDT 24
Finished Aug 16 07:11:49 PM PDT 24
Peak memory 1874632 kb
Host smart-fb3f2e6d-6776-4d4b-b762-2b3f212397b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750090049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_an
d_output.2750090049 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/9.kmac_mubi.2896133799
Short name T60
Test name
Test status
Simulation time 21294122375 ps
CPU time 189.82 seconds
Started Aug 16 06:06:44 PM PDT 24
Finished Aug 16 06:09:54 PM PDT 24
Peak memory 356576 kb
Host smart-3d562d71-20de-4312-a70f-c90b325fcd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896133799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.2896133799 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_mubi/latest

Test location /workspace/coverage/default/9.kmac_sideload.3047024339
Short name T234
Test name
Test status
Simulation time 2980947285 ps
CPU time 68.15 seconds
Started Aug 16 06:06:44 PM PDT 24
Finished Aug 16 06:07:53 PM PDT 24
Peak memory 273580 kb
Host smart-831db0c4-a4df-44de-8c8f-df7ecb95e3e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047024339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.3047024339 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_sideload/latest

Test location /workspace/coverage/default/9.kmac_smoke.2188102604
Short name T378
Test name
Test status
Simulation time 4502281643 ps
CPU time 21.59 seconds
Started Aug 16 06:06:35 PM PDT 24
Finished Aug 16 06:06:56 PM PDT 24
Peak memory 226844 kb
Host smart-0b4c9125-a5d7-4bd1-b93c-aad42b802f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188102604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.2188102604 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_smoke/latest

Test location /workspace/coverage/default/9.kmac_stress_all.3025958251
Short name T342
Test name
Test status
Simulation time 88006426124 ps
CPU time 1272.69 seconds
Started Aug 16 06:06:32 PM PDT 24
Finished Aug 16 06:27:45 PM PDT 24
Peak memory 970968 kb
Host smart-c107c001-a2dd-487e-910d-35462cd09450
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3025958251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.3025958251 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%