Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

41523933

1

T1

97113

T2

163

T3

44153

full_word

42484739

1

T1

71717

T2

308

T3

56871

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	84008372	1			T1	168830		T2	471		T3	101024
auto[TlIntgErrCmd]	115	1			T107	5		T115	4		T116	7
auto[TlIntgErrData]	98	1			T107	9		T115	2		T116	8
auto[TlIntgErrBoth]	87	1			T107	6		T115	4		T116	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46795615

1

T1

90981

T2

183

T3

64417

auto[1]

37213057

1

T1

77849

T2

288

T3

36607

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	27872361	1			T1	62486		T2	101		T3	27451
auto[TlIntgErrNone]	partial	auto[1]	13651288	1			T1	34627		T2	62		T3	16702
auto[TlIntgErrNone]	full_word	auto[0]	18923117	1			T1	28495		T2	82		T3	36966
auto[TlIntgErrNone]	full_word	auto[1]	23561606	1			T1	43222		T2	226		T3	19905
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T107	3		T116	2		T132	3
auto[TlIntgErrCmd]	partial	auto[1]	64	1			T107	2		T115	4		T116	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T116	1		T170	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T171	1		T172	1		-	-
auto[TlIntgErrData]	partial	auto[0]	49	1			T107	3		T115	1		T116	5
auto[TlIntgErrData]	partial	auto[1]	42	1			T107	5		T115	1		T116	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T173	1		T174	1		T170	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T107	1		T166	1		T175	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T107	5		T115	2		T116	3
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T107	1		T115	2		T116	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T176	1		T166	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T173	1		T174	1		T177	1