Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	500367742	54489	0	0
RunThenComplete_M	500367742	649578	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500367742	54489	0	0
T1	358983	26	0	0
T2	6991	3	0	0
T3	153639	90	0	0
T4	0	9	0	0
T7	0	36	0	0
T8	0	195	0	0
T12	2057	0	0	0
T13	466383	0	0	0
T14	266059	0	0	0
T15	0	323	0	0
T33	457419	70	0	0
T34	1783	0	0	0
T35	1045	0	0	0
T36	80731	64	0	0
T40	0	113	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	500367742	649578	0	0
T1	358983	1033	0	0
T2	6991	10	0	0
T3	153639	536	0	0
T7	0	179	0	0
T8	0	1018	0	0
T12	2057	1	0	0
T13	466383	0	0	0
T14	266059	0	0	0
T15	0	3190	0	0
T33	457419	2451	0	0
T34	1783	0	0	0
T35	1045	0	0	0
T36	80731	172	0	0
T40	0	4604	0	0