Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	501668935	5845	0	0
entropy_period_rd_A	501668935	1398	0	0
intr_enable_rd_A	501668935	2203	0	0
prefix_0_rd_A	501668935	1431	0	0
prefix_10_rd_A	501668935	1431	0	0
prefix_1_rd_A	501668935	1506	0	0
prefix_2_rd_A	501668935	1509	0	0
prefix_3_rd_A	501668935	1479	0	0
prefix_4_rd_A	501668935	1433	0	0
prefix_5_rd_A	501668935	1394	0	0
prefix_6_rd_A	501668935	1517	0	0
prefix_7_rd_A	501668935	1410	0	0
prefix_8_rd_A	501668935	1399	0	0
prefix_9_rd_A	501668935	1514	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501668935	5845	0	0
T44	4600	0	0	0
T68	99057	1390	0	0
T69	0	1727	0	0
T72	341173	0	0	0
T107	0	5	0	0
T109	2335	0	0	0
T110	71739	0	0	0
T114	0	3	0	0
T115	0	1	0	0
T116	0	2	0	0
T117	0	88	0	0
T123	0	112	0	0
T127	0	250	0	0
T131	0	3	0	0
T134	146670	0	0	0
T135	169875	0	0	0
T136	170050	0	0	0
T137	734080	0	0	0
T138	139217	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501668935	1398	0	0
T92	5196	21	0	0
T100	10087	37	0	0
T130	3454	2	0	0
T146	2566	3	0	0
T147	2661	1	0	0
T148	5796	13	0	0
T149	6972	58	0	0
T150	124589	108	0	0
T151	6865	35	0	0
T152	11828	98	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501668935	2203	0	0
T92	5196	31	0	0
T100	10087	33	0	0
T130	3454	19	0	0
T147	2661	8	0	0
T148	5796	16	0	0
T149	6972	29	0	0
T150	124589	242	0	0
T153	1296	15	0	0
T154	1891	16	0	0
T155	1698	28	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501668935	1431	0	0
T92	5196	20	0	0
T100	10087	22	0	0
T130	3454	16	0	0
T146	2566	4	0	0
T147	2661	5	0	0
T148	5796	9	0	0
T149	6972	18	0	0
T150	124589	257	0	0
T151	6865	49	0	0
T152	11828	51	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501668935	1431	0	0
T92	5196	17	0	0
T100	10087	35	0	0
T130	3454	13	0	0
T146	2566	5	0	0
T147	2661	1	0	0
T148	5796	13	0	0
T149	6972	22	0	0
T150	124589	277	0	0
T151	6865	16	0	0
T152	11828	63	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501668935	1506	0	0
T92	5196	6	0	0
T100	10087	53	0	0
T130	3454	8	0	0
T146	2566	1	0	0
T147	2661	8	0	0
T148	5796	34	0	0
T149	6972	30	0	0
T150	124589	291	0	0
T151	6865	23	0	0
T152	11828	54	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501668935	1509	0	0
T92	5196	16	0	0
T100	10087	11	0	0
T130	3454	9	0	0
T147	2661	11	0	0
T148	5796	60	0	0
T149	6972	69	0	0
T150	124589	296	0	0
T151	6865	31	0	0
T152	11828	49	0	0
T156	6637	36	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501668935	1479	0	0
T92	5196	26	0	0
T100	10087	25	0	0
T130	3454	19	0	0
T146	2566	8	0	0
T147	2661	9	0	0
T148	5796	10	0	0
T149	6972	4	0	0
T150	124589	222	0	0
T151	6865	25	0	0
T152	11828	59	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501668935	1433	0	0
T92	5196	28	0	0
T100	10087	38	0	0
T130	3454	9	0	0
T146	2566	1	0	0
T147	2661	12	0	0
T148	5796	4	0	0
T149	6972	17	0	0
T150	124589	279	0	0
T151	6865	34	0	0
T152	11828	47	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501668935	1394	0	0
T92	5196	11	0	0
T100	10087	28	0	0
T130	3454	8	0	0
T146	2566	1	0	0
T147	2661	4	0	0
T148	5796	3	0	0
T149	6972	5	0	0
T150	124589	297	0	0
T151	6865	29	0	0
T152	11828	53	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501668935	1517	0	0
T92	5196	13	0	0
T100	10087	21	0	0
T130	3454	16	0	0
T146	2566	3	0	0
T147	2661	6	0	0
T148	5796	23	0	0
T149	6972	33	0	0
T150	124589	269	0	0
T151	6865	23	0	0
T152	11828	66	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501668935	1410	0	0
T92	5196	29	0	0
T100	10087	20	0	0
T130	3454	11	0	0
T146	2566	7	0	0
T147	2661	3	0	0
T148	5796	16	0	0
T149	6972	30	0	0
T150	124589	283	0	0
T151	6865	35	0	0
T152	11828	57	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501668935	1399	0	0
T92	5196	31	0	0
T100	10087	23	0	0
T117	7994	3	0	0
T130	3454	19	0	0
T146	2566	2	0	0
T147	2661	8	0	0
T148	5796	13	0	0
T149	6972	41	0	0
T150	124589	282	0	0
T151	6865	30	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501668935	1514	0	0
T92	5196	39	0	0
T100	10087	16	0	0
T130	3454	14	0	0
T146	2566	7	0	0
T147	2661	6	0	0
T148	5796	17	0	0
T149	6972	47	0	0
T150	124589	270	0	0
T151	6865	27	0	0
T152	11828	70	0	0