Module Definition
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Module : prim_trivium
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.62 100.00 88.37 94.12 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_trivium_0.1/rtl/prim_trivium.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_entropy.u_entropy.u_prim_trivium 95.62 100.00 88.37 94.12 100.00


Module Instance : tb.dut.gen_entropy.u_entropy.u_prim_trivium

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.62 100.00 88.37 94.12 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.62 100.00 88.37 94.12 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.57 100.00 87.83 100.00 100.00 100.00 gen_entropy.u_entropy


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_trivium
Line No.TotalCoveredPercent
TOTAL2828100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN12211100.00
ALWAYS13144100.00
ALWAYS17044100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
ALWAYS19433100.00
CONT_ASSIGN20211100.00
ALWAYS20433100.00
CONT_ASSIGN21011100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
ALWAYS28833100.00
CONT_ASSIGN29611100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_trivium_0.1/rtl/prim_trivium.sv' or '../src/lowrisc_prim_trivium_0.1/rtl/prim_trivium.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
119 1 1
120 1 1
121 1 1
122 1 1
131 1 1
132 1 1
133 1 1
134 1 1
170 1 1
172 1 1
173 1 1
175 1 1
188 1 1
189 1 1
194 1 1
195 1 1
197 1 1
202 1 1
204 1 1
205 1 1
207 1 1
210 1 1
284 1 1
285 1 1
288 1 1
289 1 1
291 1 1
296 1 1
300 unreachable

Cond Coverage for Module : prim_trivium
TotalCoveredPercent
Conditions433888.37
Logical433888.37
Non-Logical00
Event00

 LINE       119
 EXPRESSION (en_i | update_init)
             --1-   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3 

 LINE       120
 EXPRESSION (seed_req_o & seed_ack_i)
             -----1----   -----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       170
 EXPRESSION (((!update)) ? state_q : state_update)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       188
 EXPRESSION (lockup & ((StrictLockupProtection | (~allow_lockup_i))))
             ---1--   -----------------------2----------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Not Covered 

 LINE       189
 EXPRESSION (restore ? StateSeed : (wr_en_seed ? state_seed : (update ? state_update : state_q)))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       189
 SUB-EXPRESSION (wr_en_seed ? state_seed : (update ? state_update : state_q))
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       189
 SUB-EXPRESSION (update ? state_update : state_q)
                 ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       202
 EXPRESSION ((seed_en_i | seed_req_q) & (((~seed_ack_i)) | ((~last_state_part))))
             ------------1-----------   --------------------2-------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       202
 SUB-EXPRESSION (seed_en_i | seed_req_q)
                 ----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3 

 LINE       202
 SUB-EXPRESSION (((~seed_ack_i)) | ((~last_state_part)))
                 -------1-------   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3 

 LINE       210
 EXPRESSION (seed_en_i | seed_req_q)
             ----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3 

 LINE       284
 EXPRESSION (state_idx_q == LastStatePart[(StateIdxWidth - 1):0])
            --------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       285
 EXPRESSION ((wr_en_seed & last_state_part) ? '0 : ((wr_en_seed & ((~last_state_part))) ? ((state_idx_q + 1'b1)) : state_idx_q))
             ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       285
 SUB-EXPRESSION (wr_en_seed & last_state_part)
                 -----1----   -------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       285
 SUB-EXPRESSION ((wr_en_seed & ((~last_state_part))) ? ((state_idx_q + 1'b1)) : state_idx_q)
                 -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       285
 SUB-EXPRESSION (wr_en_seed & ((~last_state_part)))
                 -----1----   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3 

 LINE       296
 EXPRESSION (seed_req_o & seed_ack_i & last_state_part)
             -----1----   -----2----   -------3-------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3
Branch Coverage for Module : prim_trivium
Line No.TotalCoveredPercent
Branches 17 16 94.12
TERNARY 189 4 3 75.00
TERNARY 285 3 3 100.00
IF 194 2 2 100.00
IF 204 2 2 100.00
TERNARY 170 2 2 100.00
IF 172 2 2 100.00
IF 288 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_trivium_0.1/rtl/prim_trivium.sv' or '../src/lowrisc_prim_trivium_0.1/rtl/prim_trivium.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	189	(restore) ? 
-2-:	189	(wr_en_seed) ? 
-3-:	189	(update) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	285	((wr_en_seed & last_state_part)) ? 
-2-:	285	((wr_en_seed & (~last_state_part))) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	194	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	204	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	170	((!update)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	172	if (last_state_part)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	288	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Assert Coverage for Module : prim_trivium
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
PrimTriviumPartialStateSeedWhileUpdate_A 500367742 1154 0 0


PrimTriviumPartialStateSeedWhileUpdate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 500367742 1154 0 0
T1 358983 1 0 0
T2 6991 1 0 0
T3 153639 1 0 0
T4 0 1 0 0
T7 0 1 0 0
T8 0 1 0 0
T12 2057 1 0 0
T13 466383 0 0 0
T14 266059 0 0 0
T15 0 12 0 0
T33 457419 0 0 0
T34 1783 0 0 0
T35 1045 0 0 0
T36 80731 1 0 0
T40 0 10 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%