Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

45896336

1

T1

47709

T2

216289

T4

104

full_word

46397690

1

T1

106409

T2

273579

T3

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	92293726	1			T1	154118		T2	489868		T3	4
auto[TlIntgErrCmd]	99	1			T118	5		T119	7		T120	3
auto[TlIntgErrData]	98	1			T118	7		T119	7		T120	5
auto[TlIntgErrBoth]	103	1			T118	8		T119	6		T120	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51171556

1

T1

113926

T2

244494

T3

1

auto[1]

41122470

1

T1

40192

T2

245374

T3

3

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	30490313	1			T1	28262		T2	141236		T4	86
auto[TlIntgErrNone]	partial	auto[1]	15405744	1			T1	19447		T2	75053		T4	18
auto[TlIntgErrNone]	full_word	auto[0]	20681108	1			T1	85664		T2	103258		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	25716561	1			T1	20745		T2	170321		T3	3
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T118	2		T119	2		T120	3
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T118	3		T119	4		T174	4
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T174	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T119	1		T125	1		T176	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T118	2		T119	3		T120	2
auto[TlIntgErrData]	partial	auto[1]	46	1			T118	4		T119	3		T120	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T119	1		T174	2		T172	2
auto[TlIntgErrData]	full_word	auto[1]	1	1			T118	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T118	1		T119	2		T120	2
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T118	5		T119	4		T174	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T118	1		T174	1		T171	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T118	1		T173	1		T178	2