Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.05	87.50	92.68			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_app_intf.u_appid_arb	95.05	87.50	92.68			100.00	100.00

---

Module Instance : tb.dut.u_app_intf.u_appid_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.05	87.50	92.68			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.05	87.50	92.68			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.71	94.57	86.30		46.67	91.01	100.00	u_app_intf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		32	28	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	97	1	1	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	0	0.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	3	3
87	0	3
89	3	3
97	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	0	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	41	38	92.68
Logical	41	38	92.68
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T7,T8
1	0	Covered	T2,T4,T5

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T7,T8
1	0	Covered	T2,T4,T5

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T8
0	1	Unreachable
1	0	Covered	T2,T7,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T2,T7,T8
1	Covered	T2,T7,T8

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T4,T5

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T4,T5

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T2,T7,T8
1	Covered	T2,T7,T8

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T4,T5

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T7,T9
1	1	Covered	T2,T4,T5

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Not Covered
1	1	Covered	T2,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T7,T9

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T2,T7,T8
1	1	Not Covered

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T8
0	Covered	T2,T7,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T8
0	Covered	T2,T7,T8

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	613647730	613501254	0	0
CheckNGreaterZero_A	655	655	0	0
GntImpliesReady_A	613647730	7893	0	0
GntImpliesValid_A	613647730	7893	0	0
GrantKnown_A	613647730	613501254	0	0
IdxKnown_A	613647730	613501254	0	0
IndexIsCorrect_A	613647730	7893	0	0
NoReadyValidNoGrant_A	613647730	610306725	0	0
Priority_A	613647730	3194529	0	0
ReadyAndValidImplyGrant_A	613647730	7893	0	0
ReqAndReadyImplyGrant_A	613647730	7893	0	0
ReqImpliesValid_A	613647730	3194529	0	0
ValidKnown_A	613647730	613501254	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613647730	613501254	0	0
T1	232866	232856	0	0
T2	358130	358096	0	0
T3	1619	1526	0	0
T4	33232	33142	0	0
T5	33798	33738	0	0
T6	21998	21930	0	0
T7	131433	131361	0	0
T8	1495	1320	0	0
T16	135502	135493	0	0
T32	169853	169846	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655	655	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T16	1	1	0	0
T32	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613647730	7893	0	0
T2	358130	17	0	0
T3	1619	0	0	0
T4	33232	5	0	0
T5	33798	4	0	0
T6	21998	3	0	0
T7	131433	34	0	0
T8	1495	1	0	0
T9	0	35	0	0
T16	135502	0	0	0
T32	169853	0	0	0
T33	244250	0	0	0
T34	0	61	0	0
T35	0	12	0	0
T36	0	65	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613647730	7893	0	0
T2	358130	17	0	0
T3	1619	0	0	0
T4	33232	5	0	0
T5	33798	4	0	0
T6	21998	3	0	0
T7	131433	34	0	0
T8	1495	1	0	0
T9	0	35	0	0
T16	135502	0	0	0
T32	169853	0	0	0
T33	244250	0	0	0
T34	0	61	0	0
T35	0	12	0	0
T36	0	65	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613647730	613501254	0	0
T1	232866	232856	0	0
T2	358130	358096	0	0
T3	1619	1526	0	0
T4	33232	33142	0	0
T5	33798	33738	0	0
T6	21998	21930	0	0
T7	131433	131361	0	0
T8	1495	1320	0	0
T16	135502	135493	0	0
T32	169853	169846	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613647730	613501254	0	0
T1	232866	232856	0	0
T2	358130	358096	0	0
T3	1619	1526	0	0
T4	33232	33142	0	0
T5	33798	33738	0	0
T6	21998	21930	0	0
T7	131433	131361	0	0
T8	1495	1320	0	0
T16	135502	135493	0	0
T32	169853	169846	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613647730	7893	0	0
T2	358130	17	0	0
T3	1619	0	0	0
T4	33232	5	0	0
T5	33798	4	0	0
T6	21998	3	0	0
T7	131433	34	0	0
T8	1495	1	0	0
T9	0	35	0	0
T16	135502	0	0	0
T32	169853	0	0	0
T33	244250	0	0	0
T34	0	61	0	0
T35	0	12	0	0
T36	0	65	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613647730	610306725	0	0
T1	232866	232856	0	0
T2	358130	357843	0	0
T3	1619	1526	0	0
T4	33232	32659	0	0
T5	33798	33413	0	0
T6	21998	21738	0	0
T7	131433	130924	0	0
T8	1495	428	0	0
T16	135502	135493	0	0
T32	169853	169846	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613647730	3194529	0	0
T2	358130	2530	0	0
T3	1619	0	0	0
T4	33232	483	0	0
T5	33798	325	0	0
T6	21998	192	0	0
T7	131433	4379	0	0
T8	1495	892	0	0
T9	0	15961	0	0
T16	135502	0	0	0
T32	169853	0	0	0
T33	244250	0	0	0
T34	0	3879	0	0
T35	0	2077	0	0
T36	0	10447	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613647730	7893	0	0
T2	358130	17	0	0
T3	1619	0	0	0
T4	33232	5	0	0
T5	33798	4	0	0
T6	21998	3	0	0
T7	131433	34	0	0
T8	1495	1	0	0
T9	0	35	0	0
T16	135502	0	0	0
T32	169853	0	0	0
T33	244250	0	0	0
T34	0	61	0	0
T35	0	12	0	0
T36	0	65	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613647730	7893	0	0
T2	358130	17	0	0
T3	1619	0	0	0
T4	33232	5	0	0
T5	33798	4	0	0
T6	21998	3	0	0
T7	131433	34	0	0
T8	1495	1	0	0
T9	0	35	0	0
T16	135502	0	0	0
T32	169853	0	0	0
T33	244250	0	0	0
T34	0	61	0	0
T35	0	12	0	0
T36	0	65	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613647730	3194529	0	0
T2	358130	2530	0	0
T3	1619	0	0	0
T4	33232	483	0	0
T5	33798	325	0	0
T6	21998	192	0	0
T7	131433	4379	0	0
T8	1495	892	0	0
T9	0	15961	0	0
T16	135502	0	0	0
T32	169853	0	0	0
T33	244250	0	0	0
T34	0	3879	0	0
T35	0	2077	0	0
T36	0	10447	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613647730	613501254	0	0
T1	232866	232856	0	0
T2	358130	358096	0	0
T3	1619	1526	0	0
T4	33232	33142	0	0
T5	33798	33738	0	0
T6	21998	21930	0	0
T7	131433	131361	0	0
T8	1495	1320	0	0
T16	135502	135493	0	0
T32	169853	169846	0	0