Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	613647730	56770	0	0
RunThenComplete_M	613647730	708731	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613647730	56770	0	0
T1	232866	1246	0	0
T2	358130	223	0	0
T3	1619	0	0	0
T4	33232	5	0	0
T5	33798	4	0	0
T6	21998	3	0	0
T7	131433	333	0	0
T8	1495	0	0	0
T9	0	90	0	0
T16	135502	89	0	0
T32	169853	100	0	0
T33	0	16	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	613647730	708731	0	0
T1	232866	1246	0	0
T2	358130	4451	0	0
T3	1619	0	0	0
T4	33232	15	0	0
T5	33798	12	0	0
T6	21998	9	0	0
T7	131433	4031	0	0
T8	1495	1	0	0
T16	135502	3593	0	0
T32	169853	5250	0	0
T33	0	594	0	0