Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	614913617	7271	0	0
entropy_period_rd_A	614913617	915	0	0
intr_enable_rd_A	614913617	1499	0	0
prefix_0_rd_A	614913617	988	0	0
prefix_10_rd_A	614913617	943	0	0
prefix_1_rd_A	614913617	993	0	0
prefix_2_rd_A	614913617	912	0	0
prefix_3_rd_A	614913617	1017	0	0
prefix_4_rd_A	614913617	1027	0	0
prefix_5_rd_A	614913617	1013	0	0
prefix_6_rd_A	614913617	999	0	0
prefix_7_rd_A	614913617	1064	0	0
prefix_8_rd_A	614913617	1115	0	0
prefix_9_rd_A	614913617	1009	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614913617	7271	0	0
T42	137653	2102	0	0
T43	0	1592	0	0
T49	3551	0	0	0
T103	0	9	0	0
T115	0	67	0	0
T117	0	210	0	0
T118	0	2	0	0
T119	0	1	0	0
T121	0	131	0	0
T130	0	2	0	0
T131	0	15	0	0
T132	231911	0	0	0
T133	931132	0	0	0
T134	268279	0	0	0
T135	168458	0	0	0
T136	627133	0	0	0
T137	523683	0	0	0
T138	1131	0	0	0
T139	223416	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614913617	915	0	0
T83	3993	13	0	0
T84	11257	62	0	0
T130	4068	4	0	0
T150	11537	80	0	0
T151	7417	45	0	0
T152	2954	5	0	0
T153	4878	17	0	0
T154	9541	60	0	0
T155	6188	5	0	0
T156	72366	123	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614913617	1499	0	0
T83	3993	12	0	0
T84	11257	91	0	0
T122	1208	11	0	0
T130	4068	10	0	0
T150	11537	103	0	0
T151	7417	80	0	0
T157	1260	4	0	0
T158	1166	9	0	0
T159	1233	22	0	0
T160	1211	5	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614913617	988	0	0
T83	3993	16	0	0
T84	11257	65	0	0
T130	4068	5	0	0
T150	11537	47	0	0
T151	7417	30	0	0
T152	2954	9	0	0
T153	4878	38	0	0
T154	9541	39	0	0
T155	6188	24	0	0
T161	7627	6	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614913617	943	0	0
T83	3993	15	0	0
T84	11257	36	0	0
T130	4068	7	0	0
T150	11537	43	0	0
T151	7417	28	0	0
T152	2954	2	0	0
T154	9541	38	0	0
T155	6188	56	0	0
T156	72366	234	0	0
T161	7627	3	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614913617	993	0	0
T83	3993	9	0	0
T84	11257	44	0	0
T130	4068	10	0	0
T150	11537	42	0	0
T151	7417	38	0	0
T152	2954	8	0	0
T153	4878	18	0	0
T154	9541	33	0	0
T155	6188	18	0	0
T161	7627	14	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614913617	912	0	0
T81	3079	8	0	0
T83	3993	5	0	0
T84	11257	41	0	0
T130	4068	8	0	0
T150	11537	29	0	0
T151	7417	38	0	0
T152	2954	2	0	0
T153	4878	8	0	0
T154	9541	14	0	0
T161	7627	19	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614913617	1017	0	0
T81	3079	9	0	0
T83	3993	12	0	0
T84	11257	65	0	0
T130	4068	5	0	0
T150	11537	47	0	0
T151	7417	28	0	0
T152	2954	5	0	0
T153	4878	6	0	0
T154	9541	26	0	0
T161	7627	5	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614913617	1027	0	0
T83	3993	12	0	0
T84	11257	53	0	0
T130	4068	11	0	0
T150	11537	44	0	0
T151	7417	31	0	0
T152	2954	1	0	0
T153	4878	7	0	0
T154	9541	25	0	0
T155	6188	17	0	0
T161	7627	10	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614913617	1013	0	0
T81	3079	9	0	0
T83	3993	7	0	0
T84	11257	37	0	0
T130	4068	16	0	0
T150	11537	53	0	0
T151	7417	37	0	0
T153	4878	9	0	0
T154	9541	24	0	0
T155	6188	12	0	0
T156	72366	216	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614913617	999	0	0
T81	3079	10	0	0
T83	3993	12	0	0
T84	11257	49	0	0
T130	4068	7	0	0
T150	11537	46	0	0
T151	7417	38	0	0
T153	4878	3	0	0
T154	9541	35	0	0
T155	6188	24	0	0
T161	7627	12	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614913617	1064	0	0
T81	3079	2	0	0
T83	3993	12	0	0
T84	11257	51	0	0
T130	4068	13	0	0
T150	11537	33	0	0
T151	7417	30	0	0
T152	2954	9	0	0
T153	4878	18	0	0
T154	9541	56	0	0
T161	7627	10	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614913617	1115	0	0
T81	3079	6	0	0
T83	3993	6	0	0
T84	11257	68	0	0
T130	4068	2	0	0
T150	11537	46	0	0
T151	7417	40	0	0
T152	2954	8	0	0
T153	4878	22	0	0
T154	9541	68	0	0
T161	7627	6	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614913617	1009	0	0
T81	3079	3	0	0
T83	3993	13	0	0
T84	11257	60	0	0
T130	4068	8	0	0
T150	11537	39	0	0
T151	7417	44	0	0
T154	9541	36	0	0
T155	6188	9	0	0
T156	72366	235	0	0
T161	7627	1	0	0