Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

43367530

1

T1

25048

T2

121

T3

4758

full_word

42704368

1

T1

41460

T2

135

T3

6659

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	86071558	1			T1	66508		T2	256		T3	11417
auto[TlIntgErrCmd]	127	1			T95	9		T109	2		T110	4
auto[TlIntgErrData]	109	1			T95	5		T109	5		T110	4
auto[TlIntgErrBoth]	104	1			T95	6		T109	3		T110	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47782014

1

T1

46318

T2

81

T3

6199

auto[1]

38289884

1

T1

20190

T2

175

T3

5218

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	28602363	1			T1	16374		T2	50		T3	2657
auto[TlIntgErrNone]	partial	auto[1]	14764855	1			T1	8674		T2	71		T3	2101
auto[TlIntgErrNone]	full_word	auto[0]	19179477	1			T1	29944		T2	31		T3	3542
auto[TlIntgErrNone]	full_word	auto[1]	23524863	1			T1	11516		T2	104		T3	3117
auto[TlIntgErrCmd]	partial	auto[0]	56	1			T95	3		T109	2		T110	2
auto[TlIntgErrCmd]	partial	auto[1]	64	1			T95	5		T110	2		T125	5
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T128	1		T155	1		T157	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T95	1		T158	1		T159	1
auto[TlIntgErrData]	partial	auto[0]	52	1			T95	2		T109	1		T110	2
auto[TlIntgErrData]	partial	auto[1]	46	1			T95	2		T109	3		T110	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T110	1		T125	1		T120	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T95	1		T109	1		T125	1
auto[TlIntgErrBoth]	partial	auto[0]	51	1			T95	2		T109	3		T110	1
auto[TlIntgErrBoth]	partial	auto[1]	43	1			T95	3		T110	1		T125	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T125	1		T120	1		T155	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T95	1		T158	2		T159	1