Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	52561383	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

50435267

1

T1

6606

T2

7888

T3

8454

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	56840143	1			T1	6257		T2	8833		T3	8325
values[0x0]	22339646	1			T1	2536		T2	3807		T3	3955
values[0x1]	23816861	1			T1	2740		T2	4255		T3	4183

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	40448554	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

62548096

1

T1

7739

T2

9913

T3

10289

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	553007	1			T1	41		T43	33		T30	5
valid_sources[0x01]	298899	1			T1	43		T43	24		T30	7
valid_sources[0x02]	368608	1			T1	37		T43	16		T30	3
valid_sources[0x03]	300906	1			T1	54		T43	19		T30	1
valid_sources[0x04]	430129	1			T1	36		T43	16		T30	1
valid_sources[0x05]	302230	1			T1	57		T43	27		T30	4
valid_sources[0x06]	297660	1			T1	62		T43	35		T30	6
valid_sources[0x07]	338835	1			T1	54		T43	28		T30	4
valid_sources[0x08]	355671	1			T1	38		T43	29		T30	4
valid_sources[0x09]	299720	1			T1	61		T43	31		T30	2
valid_sources[0x0a]	558501	1			T1	55		T43	18		T30	2
valid_sources[0x0b]	298875	1			T1	33		T43	24		T30	1
valid_sources[0x0c]	303025	1			T1	41		T43	22		T30	7
valid_sources[0x0d]	500682	1			T1	45		T43	13		T31	6
valid_sources[0x0e]	298138	1			T1	33		T43	28		T30	3
valid_sources[0x0f]	299559	1			T1	39		T43	25		T20	90
valid_sources[0x10]	301242	1			T1	34		T43	24		T31	2
valid_sources[0x11]	302619	1			T1	52		T43	19		T30	5
valid_sources[0x12]	300472	1			T1	63		T43	21		T30	7
valid_sources[0x13]	303409	1			T1	35		T43	29		T30	3
valid_sources[0x14]	302616	1			T1	48		T43	32		T30	5
valid_sources[0x15]	299250	1			T1	37		T43	39		T30	3
valid_sources[0x16]	493919	1			T1	52		T43	34		T30	4
valid_sources[0x17]	295812	1			T1	40		T43	22		T30	3
valid_sources[0x18]	318406	1			T1	40		T43	21		T30	2
valid_sources[0x19]	1078252	1			T1	38		T43	25		T31	1
valid_sources[0x1a]	368010	1			T1	34		T43	28		T30	7
valid_sources[0x1b]	314610	1			T1	46		T43	54		T30	1
valid_sources[0x1c]	551155	1			T1	47		T43	32		T30	2
valid_sources[0x1d]	299058	1			T1	34		T43	20		T30	3
valid_sources[0x1e]	355980	1			T1	52		T43	19		T30	1
valid_sources[0x1f]	300773	1			T1	68		T43	30		T30	6
valid_sources[0x20]	419752	1			T1	46		T43	20		T30	1
valid_sources[0x21]	394168	1			T1	37		T43	24		T30	4
valid_sources[0x22]	433138	1			T1	45		T43	41		T30	9
valid_sources[0x23]	298381	1			T1	50		T43	23		T30	3
valid_sources[0x24]	296838	1			T1	44		T43	37		T30	2
valid_sources[0x25]	298604	1			T1	51		T43	32		T30	3
valid_sources[0x26]	303124	1			T1	42		T43	26		T30	4
valid_sources[0x27]	1967182	1			T1	50		T43	37		T30	1
valid_sources[0x28]	425295	1			T1	43		T43	11		T30	1
valid_sources[0x29]	298262	1			T1	59		T43	31		T31	2
valid_sources[0x2a]	301019	1			T1	50		T43	31		T30	5
valid_sources[0x2b]	302527	1			T1	45		T43	21		T30	3
valid_sources[0x2c]	296817	1			T1	37		T43	35		T30	6
valid_sources[0x2d]	299700	1			T1	65		T43	27		T30	2
valid_sources[0x2e]	301477	1			T1	41		T43	20		T30	1
valid_sources[0x2f]	303044	1			T1	33		T43	27		T30	1
valid_sources[0x30]	304771	1			T1	35		T43	27		T30	3
valid_sources[0x31]	303067	1			T1	48		T43	35		T30	1
valid_sources[0x32]	303367	1			T1	33		T43	22		T30	3
valid_sources[0x33]	298419	1			T1	44		T43	36		T30	1
valid_sources[0x34]	409376	1			T1	49		T43	44		T30	2
valid_sources[0x35]	303883	1			T1	40		T43	22		T30	5
valid_sources[0x36]	519633	1			T1	29		T43	22		T30	7
valid_sources[0x37]	300704	1			T1	46		T43	41		T30	3
valid_sources[0x38]	299332	1			T1	40		T43	23		T30	11
valid_sources[0x39]	322562	1			T1	47		T43	38		T30	3
valid_sources[0x3a]	299132	1			T1	46		T43	22		T30	5
valid_sources[0x3b]	514044	1			T1	55		T43	33		T30	2
valid_sources[0x3c]	299872	1			T1	42		T43	25		T30	3
valid_sources[0x3d]	301440	1			T1	45		T43	27		T30	2
valid_sources[0x3e]	470276	1			T1	39		T43	28		T30	4
valid_sources[0x3f]	300504	1			T1	54		T43	30		T30	5
valid_sources[0x40]	296796	1			T1	55		T43	30		T30	6
valid_sources[0x41]	295045	1			T1	67		T43	32		T31	6
valid_sources[0x42]	297282	1			T1	54		T43	27		T30	5
valid_sources[0x43]	298315	1			T1	37		T43	29		T30	7
valid_sources[0x44]	299873	1			T1	41		T43	35		T30	4
valid_sources[0x45]	300018	1			T1	39		T43	26		T30	2
valid_sources[0x46]	300442	1			T1	45		T43	27		T30	5
valid_sources[0x47]	394375	1			T1	31		T43	22		T30	11
valid_sources[0x48]	772405	1			T1	44		T43	17		T30	4
valid_sources[0x49]	402457	1			T1	29		T43	21		T30	3
valid_sources[0x4a]	475728	1			T1	37		T43	22		T30	2
valid_sources[0x4b]	304478	1			T1	57		T43	20		T30	4
valid_sources[0x4c]	303374	1			T1	34		T43	34		T30	2
valid_sources[0x4d]	299741	1			T1	55		T43	29		T30	1
valid_sources[0x4e]	349258	1			T1	52		T43	25		T30	1
valid_sources[0x4f]	382023	1			T1	38		T43	32		T30	3
valid_sources[0x50]	336258	1			T1	42		T43	34		T30	1
valid_sources[0x51]	299588	1			T1	33		T43	34		T30	2
valid_sources[0x52]	512346	1			T1	54		T43	21		T30	3
valid_sources[0x53]	381934	1			T1	49		T43	27		T30	2
valid_sources[0x54]	923063	1			T1	39		T43	23		T30	3
valid_sources[0x55]	304093	1			T1	51		T43	28		T30	4
valid_sources[0x56]	297569	1			T1	52		T43	28		T30	3
valid_sources[0x57]	541796	1			T1	66		T43	21		T30	9
valid_sources[0x58]	351763	1			T1	43		T43	29		T20	115
valid_sources[0x59]	298933	1			T1	36		T43	31		T30	5
valid_sources[0x5a]	581960	1			T1	46		T43	24		T30	4
valid_sources[0x5b]	298697	1			T1	44		T43	23		T30	2
valid_sources[0x5c]	298711	1			T1	35		T43	39		T30	1
valid_sources[0x5d]	295548	1			T1	30		T43	26		T30	1
valid_sources[0x5e]	297407	1			T1	64		T43	22		T30	8
valid_sources[0x5f]	301356	1			T1	49		T43	33		T30	3
valid_sources[0x60]	304208	1			T1	43		T43	41		T30	2
valid_sources[0x61]	1072164	1			T1	40		T43	29		T30	3
valid_sources[0x62]	312258	1			T1	48		T3	16463		T43	25
valid_sources[0x63]	300259	1			T1	43		T43	30		T30	4
valid_sources[0x64]	297439	1			T1	51		T43	22		T30	3
valid_sources[0x65]	299506	1			T1	39		T43	20		T30	4
valid_sources[0x66]	297057	1			T1	38		T43	19		T30	5
valid_sources[0x67]	648629	1			T1	30		T43	22		T30	4
valid_sources[0x68]	300507	1			T1	52		T43	34		T30	1
valid_sources[0x69]	418353	1			T1	49		T43	25		T30	5
valid_sources[0x6a]	424502	1			T1	45		T43	26		T30	2
valid_sources[0x6b]	1127379	1			T1	57		T43	24		T30	3
valid_sources[0x6c]	307838	1			T1	45		T43	21		T30	1
valid_sources[0x6d]	309317	1			T1	59		T43	29		T30	5
valid_sources[0x6e]	296433	1			T1	48		T43	32		T30	5
valid_sources[0x6f]	297517	1			T1	31		T43	42		T30	3
valid_sources[0x70]	301427	1			T1	46		T43	30		T30	2
valid_sources[0x71]	296312	1			T1	40		T43	22		T30	2
valid_sources[0x72]	297761	1			T1	49		T43	23		T30	2
valid_sources[0x73]	298253	1			T1	61		T43	30		T30	4
valid_sources[0x74]	303980	1			T1	36		T43	34		T30	2
valid_sources[0x75]	300821	1			T1	55		T43	39		T30	1
valid_sources[0x76]	1728110	1			T1	32		T43	33		T30	3
valid_sources[0x77]	298478	1			T1	43		T43	40		T30	4
valid_sources[0x78]	413920	1			T1	54		T43	30		T30	2
valid_sources[0x79]	775225	1			T1	37		T43	41		T30	8
valid_sources[0x7a]	298705	1			T1	50		T43	34		T30	2
valid_sources[0x7b]	299181	1			T1	45		T43	38		T30	8
valid_sources[0x7c]	2115407	1			T1	37		T43	20		T30	3
valid_sources[0x7d]	307421	1			T1	38		T43	34		T30	2
valid_sources[0x7e]	313281	1			T1	55		T2	16895		T43	41
valid_sources[0x7f]	297259	1			T1	29		T43	34		T30	1
valid_sources[0x80]	295411	1			T1	38		T43	33		T30	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

22211782

1

T1

3507

T2

3845

T3

3850

values[0x0]

all_enables

biggest_size

14857936

1

T1

1626

T2

2178

T3

2458

values[0x1]

all_enables

biggest_size

13365549

1

T1

1473

T2

1865

T3

2146