Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

52640897

1

T1

4927

T2

9007

T3

8009

full_word

50440080

1

T1

6606

T2

7888

T3

8454

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	103080677	1			T1	11533		T2	16895		T3	16463
auto[TlIntgErrCmd]	104	1			T115	3		T116	5		T117	5
auto[TlIntgErrData]	89	1			T115	3		T116	11		T117	1
auto[TlIntgErrBoth]	107	1			T115	4		T116	4		T117	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56858139

1

T1

6257

T2

8833

T3

8325

auto[1]

46222838

1

T1

5276

T2

8062

T3

8138

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	34644880	1			T1	2750		T2	4988		T3	4475
auto[TlIntgErrNone]	partial	auto[1]	17995741	1			T1	2177		T2	4019		T3	3534
auto[TlIntgErrNone]	full_word	auto[0]	22213120	1			T1	3507		T2	3845		T3	3850
auto[TlIntgErrNone]	full_word	auto[1]	28226936	1			T1	3099		T2	4043		T3	4604
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T116	3		T117	3		T165	5
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T115	2		T116	2		T165	1
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T115	1		T117	1		T165	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T117	1		T165	1		T166	1
auto[TlIntgErrData]	partial	auto[0]	38	1			T115	2		T116	4		T117	1
auto[TlIntgErrData]	partial	auto[1]	43	1			T115	1		T116	5		T167	4
auto[TlIntgErrData]	full_word	auto[0]	4	1			T116	1		T168	1		T169	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T116	1		T166	1		T170	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T115	1		T116	1		T117	2
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T115	3		T116	3		T117	2
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T171	1		T170	2		-	-