Unified Coverage Report :: Module :: prim_packer

Module : prim_packer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	100.00			92.31	100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_msgfifo.u_packer	98.08	100.00	100.00			92.31	100.00

---

Module Instance : tb.dut.u_msgfifo.u_packer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	100.00			92.31	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.41	100.00	100.00	89.74		92.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.21	100.00			100.00	92.86	100.00	u_msgfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_pos_dupcnt.u_pos	89.74			89.74

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_packer

	Line No.	Total	Covered	Percent
TOTAL		62	62	100.00
ALWAYS	65	3	3	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	110	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
ALWAYS	120	3	3	100.00
ALWAYS	157	4	4	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
ALWAYS	185	9	9	100.00
ALWAYS	214	8	8	100.00
ALWAYS	235	3	3	100.00
ALWAYS	243	14	14	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	291	0	0
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	296	1	1	100.00
CONT_ASSIGN	299	0	0

64                          // counting mask_i ones
65         1/1              inmask_ones = '0;
           Tests:       T1 T2 T3 
66         1/1              for (int i = 0 ; i < InW ; i++) begin
           Tests:       T1 T2 T3 
67         1/1                inmask_ones = inmask_ones + OnesCntW'(mask_i[i]);
           Tests:       T1 T2 T3 
68                          end
69                        end
70                      
71                        logic [PtrW-1:0] pos_with_input;
72         1/1            assign pos_with_input = pos_q + PtrW'(inmask_ones);
           Tests:       T1 T2 T3 
73                      
74                        if (EnProtection == 1'b 0) begin : g_pos_nodup
75                          logic [PtrW-1:0] pos_d;
76                      
77                          always_comb begin
78                            pos_d = pos_q;
79                      
80                            unique case ({ack_in, ack_out})
81                              2'b00: pos_d = pos_q;
82                              2'b01: pos_d = (int'(pos_q) <= OutW) ? '0 : pos_q - PtrW'(OutW);
83                              2'b10: pos_d = pos_with_input;
84                              2'b11: pos_d = (int'(pos_with_input) <= OutW) ? '0 : pos_with_input - PtrW'(OutW);
85                              default: pos_d = pos_q;
86                            endcase
87                          end
88                      
89                          always_ff @(posedge clk_i or negedge rst_ni) begin
90                            if (!rst_ni) begin
91                              pos_q <= '0;
92                            end else if (flush_done) begin
93                              pos_q <= '0;
94                            end else begin
95                              pos_q <= pos_d;
96                            end
97                          end
98                      
99                          assign err_o = 1'b 0; // No checker logic
100                     
101                       end else begin : g_pos_dupcnt // EnProtection == 1'b 1
102                         // incr_en: Increase the pos by cnt_step. ack_in && !ack_out
103                         // decr_en: Decrease the pos by cnt_step. !ack_in && ack_out
104                         // set_en:  Set to specific value in case of ack_in && ack_out.
105                         //          This case, the value could be increased or descreased based on
106                         //          the input size (inmask_ones)
107                         logic            cnt_incr_en, cnt_decr_en, cnt_set_en;
108                         logic [PtrW-1:0] cnt_step, cnt_set;
109                     
110        1/1              assign cnt_incr_en =  ack_in && !ack_out;
           Tests:       T1 T2 T3 
111        1/1              assign cnt_decr_en = !ack_in &&  ack_out;
           Tests:       T1 T2 T3 
112        1/1              assign cnt_set_en  =  ack_in &&  ack_out;
           Tests:       T1 T2 T3 
113                     
114                         // counter has underflow protection.
115        1/1              assign cnt_step = (cnt_incr_en) ? PtrW'(inmask_ones) : PtrW'(OutW);
           Tests:       T1 T2 T3 
116                     
117                         always_comb begin : cnt_set_logic
118                     
119                           // default, consuming all data
120        1/1                cnt_set = '0;
           Tests:       T1 T2 T3 
121                     
122        1/1                if (pos_with_input > PtrW'(OutW)) begin
           Tests:       T1 T2 T3 
123                             // pos_q + inmask_ones is bigger than Output width. Still data remained.
124        1/1                  cnt_set = pos_with_input - PtrW'(OutW);
           Tests:       T1 T2 T3 
125                           end
                        MISSING_ELSE
126                         end : cnt_set_logic
127                     
128                     
129                         prim_count #(
130                           .Width      (PtrW),
131                           .ResetValue ('0  )
132                         ) u_pos (
133                           .clk_i,
134                           .rst_ni,
135                     
136                           .clr_i              (flush_done),
137                     
138                           .set_i              (cnt_set_en),
139                           .set_cnt_i          (cnt_set   ),
140                     
141                           .incr_en_i          (cnt_incr_en),
142                           .decr_en_i          (cnt_decr_en),
143                           .step_i             (cnt_step   ),
144                           .commit_i           (1'b1       ),
145                     
146                           .cnt_o              (pos_q     ), // Current counter state
147                           .cnt_after_commit_o (          ), // Next counter state
148                     
149                           .err_o
150                         );
151                       end // g_pos_dupcnt
152                     
153                       //---------------------------------------------------------------------------
154                     
155                       // Leading one detector for mask_i
156                       always_comb begin
157        1/1              lod_idx = 0;
           Tests:       T1 T2 T3 
158        1/1              for (int i = InW-1; i >= 0 ; i--) begin
           Tests:       T1 T2 T3 
159        1/1                if (mask_i[i] == 1'b1) begin
           Tests:       T1 T2 T3 
160        1/1                  lod_idx = IdxW'(unsigned'(i));
           Tests:       T1 T2 T3 
161                           end
                        MISSING_ELSE
162                         end
163                       end
164                     
165        1/1            assign ack_in  = valid_i & ready_o;
           Tests:       T1 T2 T3 
166        1/1            assign ack_out = valid_o & ready_i;
           Tests:       T1 T2 T3 
167                     
168                       // Data process =============================================================
169                       //  shiftr : Input data shifted right to put the leading one at bit zero
170        1/1            assign shiftr_data = (valid_i) ? data_i >> lod_idx : '0;
           Tests:       T1 T2 T3 
171        1/1            assign shiftr_mask = (valid_i) ? mask_i >> lod_idx : '0;
           Tests:       T1 T2 T3 
172                     
173                       //  shiftl : Input data shifted into the current stored position
174        1/1            assign shiftl_data = ConcatW'(shiftr_data) << pos_q;
           Tests:       T1 T2 T3 
175        1/1            assign shiftl_mask = ConcatW'(shiftr_mask) << pos_q;
           Tests:       T1 T2 T3 
176                     
177                       // concat : Merging stored and shiftl
178        1/1            assign concat_data = {{(InW){1'b0}}, stored_data & stored_mask} |
           Tests:       T1 T2 T3 
179                                            (shiftl_data & shiftl_mask);
180        1/1            assign concat_mask = {{(InW){1'b0}}, stored_mask} | shiftl_mask;
           Tests:       T1 T2 T3 
181                     
182                       logic [Width-1:0] stored_data_next, stored_mask_next;
183                     
184                       always_comb begin
185        1/1              unique case ({ack_in, ack_out})
           Tests:       T1 T2 T3 
186                           2'b 00: begin
187        1/1                  stored_data_next = stored_data;
           Tests:       T1 T2 T3 
188        1/1                  stored_mask_next = stored_mask;
           Tests:       T1 T2 T3 
189                           end
190                           2'b 01: begin
191                             // ack_out : shift the amount of OutW
192        1/1                  stored_data_next = {{OutW{1'b0}}, stored_data[Width-1:OutW]};
           Tests:       T1 T2 T3 
193        1/1                  stored_mask_next = {{OutW{1'b0}}, stored_mask[Width-1:OutW]};
           Tests:       T1 T2 T3 
194                           end
195                           2'b 10: begin
196                             // ack_in : Store concat data
197        1/1                  stored_data_next = concat_data[0+:Width];
           Tests:       T1 T2 T3 
198        1/1                  stored_mask_next = concat_mask[0+:Width];
           Tests:       T1 T2 T3 
199                           end
200                           2'b 11: begin
201                             // both : shift the concat_data
202        1/1                  stored_data_next = concat_data[ConcatW-1:OutW];
           Tests:       T4 T9 T10 
203        1/1                  stored_mask_next = concat_mask[ConcatW-1:OutW];
           Tests:       T4 T9 T10 
204                           end
205                           default: begin
206                             stored_data_next = stored_data;
207                             stored_mask_next = stored_mask;
208                           end
209                         endcase
210                       end
211                     
212                       // Store the data temporary if it doesn't exceed OutW
213                       always_ff @(posedge clk_i or negedge rst_ni) begin
214        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
215        1/1                stored_data <= '0;
           Tests:       T1 T2 T3 
216        1/1                stored_mask <= '0;
           Tests:       T1 T2 T3 
217        1/1              end else if (flush_done) begin
           Tests:       T1 T2 T3 
218        1/1                stored_data <= '0;
           Tests:       T1 T2 T3 
219        1/1                stored_mask <= '0;
           Tests:       T1 T2 T3 
220                         end else begin
221        1/1                stored_data <= stored_data_next;
           Tests:       T1 T2 T3 
222        1/1                stored_mask <= stored_mask_next;
           Tests:       T1 T2 T3 
223                         end
224                       end
225                       //---------------------------------------------------------------------------
226                     
227                       // flush handling
228                       typedef enum logic {
229                         FlushIdle,
230                         FlushSend
231                       } flush_st_e;
232                       flush_st_e flush_st, flush_st_next;
233                     
234                       always_ff @(posedge clk_i or negedge rst_ni) begin
235        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
236        1/1                flush_st <= FlushIdle;
           Tests:       T1 T2 T3 
237                         end else begin
238        1/1                flush_st <= flush_st_next;
           Tests:       T1 T2 T3 
239                         end
240                       end
241                     
242                       always_comb begin
243        1/1              flush_st_next = FlushIdle;
           Tests:       T1 T2 T3 
244                     
245        1/1              flush_valid = 1'b0;
           Tests:       T1 T2 T3 
246        1/1              flush_done  = 1'b0;
           Tests:       T1 T2 T3 
247                     
248        1/1              unique case (flush_st)
           Tests:       T1 T2 T3 
249                           FlushIdle: begin
250        1/1                  if (flush_i) begin
           Tests:       T1 T2 T3 
251        1/1                    flush_st_next = FlushSend;
           Tests:       T1 T2 T3 
252                             end else begin
253        1/1                    flush_st_next = FlushIdle;
           Tests:       T1 T2 T3 
254                             end
255                           end
256                     
257                           FlushSend: begin
258        1/1                  if (pos_q == '0) begin
           Tests:       T1 T2 T3 
259        1/1                    flush_st_next = FlushIdle;
           Tests:       T1 T2 T3 
260                     
261        1/1                    flush_valid = 1'b 0;
           Tests:       T1 T2 T3 
262        1/1                    flush_done  = 1'b 1;
           Tests:       T1 T2 T3 
263                             end else begin
264        1/1                    flush_st_next = FlushSend;
           Tests:       T1 T2 T3 
265                     
266        1/1                    flush_valid = 1'b 1;
           Tests:       T1 T2 T3 
267        1/1                    flush_done  = 1'b 0;
           Tests:       T1 T2 T3 
268                             end
269                           end
270                           default: begin
271                             flush_st_next = FlushIdle;
272                     
273                             flush_valid = 1'b 0;
274                             flush_done  = 1'b 0;
275                           end
276                         endcase
277                       end
278                     
279        1/1            assign flush_done_o = flush_done;
           Tests:       T1 T2 T3 
280                     
281                     
282                       // Output signals ===========================================================
283        1/1            assign valid_next = (int'(pos_q) >= OutW) ? 1'b 1 : flush_valid;
           Tests:       T1 T2 T3 
284                     
285                       // storage space is InW + OutW. So technically, ready_o can be asserted even
286                       // if `pos_q` is greater than OutW. But in order to do that, the logic should
287                       // use `inmask_ones` value whether pos_q+inmask_ones is less than (InW+OutW)
288                       // with `valid_i`. It creates a path from `valid_i` --> `ready_o`.
289                       // It may create a timing loop in some modules that use `ready_o` to
290                       // `valid_i` (which is not a good practice though)
291        unreachable    assign ready_next = int'(pos_q) <= OutW;
292                     
293                       // Output request
294        1/1            assign valid_o = valid_next;
           Tests:       T1 T2 T3 
295        1/1            assign data_o  = stored_data[OutW-1:0];
           Tests:       T1 T2 T3 
296        1/1            assign mask_o  = stored_mask[OutW-1:0];
           Tests:       T1 T2 T3 
297                     
298                       // ready_o
299        unreachable    assign ready_o = ready_next;

---

Cond Coverage for Module : prim_packer

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       110
 EXPRESSION (ack_in && ((!ack_out)))
             ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T9,T10
1	1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (((!ack_in)) && ack_out)
             -----1-----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (ack_in && ack_out)
             ---1--    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T9,T10

 LINE       115
 EXPRESSION (g_pos_dupcnt.cnt_incr_en ? (8'(inmask_ones)) : (8'(OutW)))
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       159
 EXPRESSION (mask_i[i] == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       165
 EXPRESSION (valid_i & ready_o)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable	T9,T10,T16
1	1	Covered	T1,T2,T3

 LINE       166
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T10,T16
1	1	Covered	T1,T2,T3

 LINE       170
 EXPRESSION (valid_i ? ((data_i >> lod_idx)) : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       171
 EXPRESSION (valid_i ? ((mask_i >> lod_idx)) : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       258
 EXPRESSION (pos_q == '0)
            ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       283
 EXPRESSION ((int'(pos_q) >= OutW) ? 1'b1 : flush_valid)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable	T1,T2,T3

---

Branch Coverage for Module : prim_packer

	Line No.	Total	Covered	Percent
Branches		26	24	92.31
TERNARY	170	2	2	100.00
TERNARY	171	2	2	100.00
TERNARY	283	1	1	100.00
TERNARY	115	2	2	100.00
IF	159	2	2	100.00
CASE	185	5	4	80.00
IF	214	3	3	100.00
IF	235	2	2	100.00
CASE	248	5	4	80.00
IF	122	2	2	100.00

170          assign shiftr_data = (valid_i) ? data_i >> lod_idx : '0;
                                            -1-  
                                            ==>  
                                            ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

171          assign shiftr_mask = (valid_i) ? mask_i >> lod_idx : '0;
                                            -1-  
                                            ==>  
                                            ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

283          assign valid_next = (int'(pos_q) >= OutW) ? 1'b 1 : flush_valid;
                                                       -1-  
                                                       ==> (Unreachable)  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Unreachable	T1,T2,T3
0	Covered	T1,T2,T3

115            assign cnt_step = (cnt_incr_en) ? PtrW'(inmask_ones) : PtrW'(OutW);
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

159              if (mask_i[i] == 1'b1) begin
                 -1-  
160                lod_idx = IdxW'(unsigned'(i));
                   ==>
161              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

185            unique case ({ack_in, ack_out})
                      -1-  
186              2'b 00: begin
187                stored_data_next = stored_data;
                   ==>
188                stored_mask_next = stored_mask;
189              end
190              2'b 01: begin
191                // ack_out : shift the amount of OutW
192                stored_data_next = {{OutW{1'b0}}, stored_data[Width-1:OutW]};
                   ==>
193                stored_mask_next = {{OutW{1'b0}}, stored_mask[Width-1:OutW]};
194              end
195              2'b 10: begin
196                // ack_in : Store concat data
197                stored_data_next = concat_data[0+:Width];
                   ==>
198                stored_mask_next = concat_mask[0+:Width];
199              end
200              2'b 11: begin
201                // both : shift the concat_data
202                stored_data_next = concat_data[ConcatW-1:OutW];
                   ==>
203                stored_mask_next = concat_mask[ConcatW-1:OutW];
204              end
205              default: begin
206                stored_data_next = stored_data;
                   ==>

Branches:

-1-	Status	Tests
2'b00	Covered	T1,T2,T3
2'b01	Covered	T1,T2,T3
2'b10	Covered	T1,T2,T3
2'b11	Covered	T4,T9,T10
default	Not Covered

214            if (!rst_ni) begin
               -1-  
215              stored_data <= '0;
                 ==>
216              stored_mask <= '0;
217            end else if (flush_done) begin
                        -2-  
218              stored_data <= '0;
                 ==>
219              stored_mask <= '0;
220            end else begin
221              stored_data <= stored_data_next;
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

235            if (!rst_ni) begin
               -1-  
236              flush_st <= FlushIdle;
                 ==>
237            end else begin
238              flush_st <= flush_st_next;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

248            unique case (flush_st)
                      -1-  
249              FlushIdle: begin
250                if (flush_i) begin
                   -2-  
251                  flush_st_next = FlushSend;
                     ==>
252                end else begin
253                  flush_st_next = FlushIdle;
                     ==>
254                end
255              end
256        
257              FlushSend: begin
258                if (pos_q == '0) begin
                   -3-  
259                  flush_st_next = FlushIdle;
                     ==>
260        
261                  flush_valid = 1'b 0;
262                  flush_done  = 1'b 1;
263                end else begin
264                  flush_st_next = FlushSend;
                     ==>
265        
266                  flush_valid = 1'b 1;
267                  flush_done  = 1'b 0;
268                end
269              end
270              default: begin
271                flush_st_next = FlushIdle;
                   ==>

Branches:

-1-	-2-	-3-	Status	Tests
FlushIdle	1	-	Covered	T1,T2,T3
FlushIdle	0	-	Covered	T1,T2,T3
FlushSend	-	1	Covered	T1,T2,T3
FlushSend	-	0	Covered	T1,T2,T3
default	-	-	Not Covered

122              if (pos_with_input > PtrW'(OutW)) begin
                 -1-  
123                // pos_q + inmask_ones is bigger than Output width. Still data remained.
124                cnt_set = pos_with_input - PtrW'(OutW);
                   ==>
125              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_packer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	28	28	100.00	28	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	28	28	100.00	28	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataIStable_M	640180531	465569	0	665
DataOStableWhenPending_A	640180531	665317	0	665
ExFlushValid_M	640180531	56349	0	0
ExcessiveDataStored_A	640180531	51707	0	0
ExcessiveMaskStored_A	640180531	51707	0	0
FlushFollowedByDone_A	640180531	56349	0	665
ValidIDeassertedOnFlush_M	640180531	112500	0	0
ValidOAssertedForStoredDataGTEOutW_A	640180531	12693777	0	0
ValidOPairedWidthReadyI_A	640180531	665317	0	0
g_byte_assert.InputDividedBy8_A	665	665	0	0
g_byte_assert.OutputDividedBy8_A	665	665	0	0
g_byte_assert.g_byte_input_masking[0].InputMaskContiguous_A	640180531	26841106	0	0
g_byte_assert.g_byte_input_masking[1].InputMaskContiguous_A	640180531	26841106	0	0
g_byte_assert.g_byte_input_masking[2].InputMaskContiguous_A	640180531	26841106	0	0
g_byte_assert.g_byte_input_masking[3].InputMaskContiguous_A	640180531	26841106	0	0
g_byte_assert.g_byte_input_masking[4].InputMaskContiguous_A	640180531	26841106	0	0
g_byte_assert.g_byte_input_masking[5].InputMaskContiguous_A	640180531	26841106	0	0
g_byte_assert.g_byte_input_masking[6].InputMaskContiguous_A	640180531	26841106	0	0
g_byte_assert.g_byte_input_masking[7].InputMaskContiguous_A	640180531	26841106	0	0
g_byte_assert.g_byte_output_masking[0].OutputMaskContiguous_A	640180531	12743510	0	0
g_byte_assert.g_byte_output_masking[1].OutputMaskContiguous_A	640180531	12743510	0	0
g_byte_assert.g_byte_output_masking[2].OutputMaskContiguous_A	640180531	12743510	0	0
g_byte_assert.g_byte_output_masking[3].OutputMaskContiguous_A	640180531	12743510	0	0
g_byte_assert.g_byte_output_masking[4].OutputMaskContiguous_A	640180531	12743510	0	0
g_byte_assert.g_byte_output_masking[5].OutputMaskContiguous_A	640180531	12743510	0	0
g_byte_assert.g_byte_output_masking[6].OutputMaskContiguous_A	640180531	12743510	0	0
g_byte_assert.g_byte_output_masking[7].OutputMaskContiguous_A	640180531	12743510	0	0
gen_mask_assert.ContiguousOnesMask_M	640180531	26841106	0	0

DataIStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	465569	0	665
T9	68458	2340	0	1
T10	225064	3084	0	1
T12	0	6	0	0
T13	0	9669	0	0
T15	745929	0	0	1
T16	0	1224	0	0
T27	0	8	0	0
T32	0	1427	0	0
T34	0	13912	0	0
T46	1219	0	0	1
T47	30194	0	0	1
T48	56730	0	0	1
T49	9834	0	0	1
T50	4147	0	0	1
T51	529539	0	0	1
T79	0	9	0	0
T88	0	1	0	0
T106	100607	0	0	1

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	665317	0	665
T9	68458	2340	0	1
T10	225064	3182	0	1
T13	0	8690	0	0
T15	745929	0	0	1
T16	0	1322	0	0
T24	0	35	0	0
T25	0	41	0	0
T32	0	1427	0	0
T34	0	12727	0	0
T37	0	109	0	0
T46	1219	0	0	1
T47	30194	0	0	1
T48	56730	0	0	1
T49	9834	0	0	1
T50	4147	0	0	1
T51	529539	0	0	1
T106	100607	0	0	1
T107	0	1349	0	0

ExFlushValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	56349	0	0
T1	84512	105	0	0
T2	116868	145	0	0
T3	201179	137	0	0
T4	0	16	0	0
T7	14564	3	0	0
T20	311127	29	0	0
T29	448588	197	0	0
T30	4435	3	0	0
T31	9839	3	0	0
T43	159485	73	0	0
T44	1227	0	0	0

ExcessiveDataStored_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	51707	0	0
T9	68458	332	0	0
T10	225064	408	0	0
T11	0	10	0	0
T12	0	2	0	0
T13	0	422	0	0
T15	745929	0	0	0
T16	0	170	0	0
T17	0	2	0	0
T25	0	33	0	0
T32	0	311	0	0
T42	0	2	0	0
T46	1219	0	0	0
T47	30194	0	0	0
T48	56730	0	0	0
T49	9834	0	0	0
T50	4147	0	0	0
T51	529539	0	0	0
T106	100607	0	0	0

ExcessiveMaskStored_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	51707	0	0
T9	68458	332	0	0
T10	225064	408	0	0
T11	0	10	0	0
T12	0	2	0	0
T13	0	422	0	0
T15	745929	0	0	0
T16	0	170	0	0
T17	0	2	0	0
T25	0	33	0	0
T32	0	311	0	0
T42	0	2	0	0
T46	1219	0	0	0
T47	30194	0	0	0
T48	56730	0	0	0
T49	9834	0	0	0
T50	4147	0	0	0
T51	529539	0	0	0
T106	100607	0	0	0

FlushFollowedByDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	56349	0	665
T1	84512	105	0	1
T2	116868	145	0	1
T3	201179	137	0	1
T4	0	16	0	0
T7	14564	3	0	1
T20	311127	29	0	1
T29	448588	197	0	1
T30	4435	3	0	1
T31	9839	3	0	1
T43	159485	73	0	1
T44	1227	0	0	1

ValidIDeassertedOnFlush_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	112500	0	0
T1	84512	196	0	0
T2	116868	271	0	0
T3	201179	256	0	0
T4	0	16	0	0
T7	14564	3	0	0
T20	311127	57	0	0
T29	448588	368	0	0
T30	4435	6	0	0
T31	9839	6	0	0
T43	159485	136	0	0
T44	1227	0	0	0

ValidOAssertedForStoredDataGTEOutW_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	12693777	0	0
T1	84512	637	0	0
T2	116868	1242	0	0
T3	201179	1105	0	0
T4	0	1127	0	0
T7	14564	0	0	0
T9	0	3275	0	0
T20	311127	1716	0	0
T29	448588	307	0	0
T30	4435	50	0	0
T31	9839	50	0	0
T43	159485	297	0	0
T44	1227	0	0	0

ValidOPairedWidthReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	665317	0	0
T9	68458	2340	0	0
T10	225064	3182	0	0
T13	0	8690	0	0
T15	745929	0	0	0
T16	0	1322	0	0
T24	0	35	0	0
T25	0	41	0	0
T32	0	1427	0	0
T34	0	12727	0	0
T37	0	109	0	0
T46	1219	0	0	0
T47	30194	0	0	0
T48	56730	0	0	0
T49	9834	0	0	0
T50	4147	0	0	0
T51	529539	0	0	0
T106	100607	0	0	0
T107	0	1349	0	0

g_byte_assert.InputDividedBy8_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665	665	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0

g_byte_assert.OutputDividedBy8_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665	665	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0

g_byte_assert.g_byte_input_masking[0].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	26841106	0	0
T1	84512	1658	0	0
T2	116868	3111	0	0
T3	201179	2792	0	0
T4	0	1127	0	0
T7	14564	0	0	0
T9	0	4131	0	0
T20	311127	3981	0	0
T29	448588	1105	0	0
T30	4435	123	0	0
T31	9839	127	0	0
T43	159485	823	0	0
T44	1227	0	0	0

g_byte_assert.g_byte_input_masking[1].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	26841106	0	0
T1	84512	1658	0	0
T2	116868	3111	0	0
T3	201179	2792	0	0
T4	0	1127	0	0
T7	14564	0	0	0
T9	0	4131	0	0
T20	311127	3981	0	0
T29	448588	1105	0	0
T30	4435	123	0	0
T31	9839	127	0	0
T43	159485	823	0	0
T44	1227	0	0	0

g_byte_assert.g_byte_input_masking[2].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	26841106	0	0
T1	84512	1658	0	0
T2	116868	3111	0	0
T3	201179	2792	0	0
T4	0	1127	0	0
T7	14564	0	0	0
T9	0	4131	0	0
T20	311127	3981	0	0
T29	448588	1105	0	0
T30	4435	123	0	0
T31	9839	127	0	0
T43	159485	823	0	0
T44	1227	0	0	0

g_byte_assert.g_byte_input_masking[3].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	26841106	0	0
T1	84512	1658	0	0
T2	116868	3111	0	0
T3	201179	2792	0	0
T4	0	1127	0	0
T7	14564	0	0	0
T9	0	4131	0	0
T20	311127	3981	0	0
T29	448588	1105	0	0
T30	4435	123	0	0
T31	9839	127	0	0
T43	159485	823	0	0
T44	1227	0	0	0

g_byte_assert.g_byte_input_masking[4].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	26841106	0	0
T1	84512	1658	0	0
T2	116868	3111	0	0
T3	201179	2792	0	0
T4	0	1127	0	0
T7	14564	0	0	0
T9	0	4131	0	0
T20	311127	3981	0	0
T29	448588	1105	0	0
T30	4435	123	0	0
T31	9839	127	0	0
T43	159485	823	0	0
T44	1227	0	0	0

g_byte_assert.g_byte_input_masking[5].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	26841106	0	0
T1	84512	1658	0	0
T2	116868	3111	0	0
T3	201179	2792	0	0
T4	0	1127	0	0
T7	14564	0	0	0
T9	0	4131	0	0
T20	311127	3981	0	0
T29	448588	1105	0	0
T30	4435	123	0	0
T31	9839	127	0	0
T43	159485	823	0	0
T44	1227	0	0	0

g_byte_assert.g_byte_input_masking[6].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	26841106	0	0
T1	84512	1658	0	0
T2	116868	3111	0	0
T3	201179	2792	0	0
T4	0	1127	0	0
T7	14564	0	0	0
T9	0	4131	0	0
T20	311127	3981	0	0
T29	448588	1105	0	0
T30	4435	123	0	0
T31	9839	127	0	0
T43	159485	823	0	0
T44	1227	0	0	0

g_byte_assert.g_byte_input_masking[7].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	26841106	0	0
T1	84512	1658	0	0
T2	116868	3111	0	0
T3	201179	2792	0	0
T4	0	1127	0	0
T7	14564	0	0	0
T9	0	4131	0	0
T20	311127	3981	0	0
T29	448588	1105	0	0
T30	4435	123	0	0
T31	9839	127	0	0
T43	159485	823	0	0
T44	1227	0	0	0

g_byte_assert.g_byte_output_masking[0].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	12743510	0	0
T1	84512	728	0	0
T2	116868	1368	0	0
T3	201179	1224	0	0
T4	0	1127	0	0
T7	14564	0	0	0
T9	0	3282	0	0
T20	311127	1744	0	0
T29	448588	478	0	0
T30	4435	53	0	0
T31	9839	53	0	0
T43	159485	360	0	0
T44	1227	0	0	0

g_byte_assert.g_byte_output_masking[1].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	12743510	0	0
T1	84512	728	0	0
T2	116868	1368	0	0
T3	201179	1224	0	0
T4	0	1127	0	0
T7	14564	0	0	0
T9	0	3282	0	0
T20	311127	1744	0	0
T29	448588	478	0	0
T30	4435	53	0	0
T31	9839	53	0	0
T43	159485	360	0	0
T44	1227	0	0	0

g_byte_assert.g_byte_output_masking[2].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	12743510	0	0
T1	84512	728	0	0
T2	116868	1368	0	0
T3	201179	1224	0	0
T4	0	1127	0	0
T7	14564	0	0	0
T9	0	3282	0	0
T20	311127	1744	0	0
T29	448588	478	0	0
T30	4435	53	0	0
T31	9839	53	0	0
T43	159485	360	0	0
T44	1227	0	0	0

g_byte_assert.g_byte_output_masking[3].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	12743510	0	0
T1	84512	728	0	0
T2	116868	1368	0	0
T3	201179	1224	0	0
T4	0	1127	0	0
T7	14564	0	0	0
T9	0	3282	0	0
T20	311127	1744	0	0
T29	448588	478	0	0
T30	4435	53	0	0
T31	9839	53	0	0
T43	159485	360	0	0
T44	1227	0	0	0

g_byte_assert.g_byte_output_masking[4].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	12743510	0	0
T1	84512	728	0	0
T2	116868	1368	0	0
T3	201179	1224	0	0
T4	0	1127	0	0
T7	14564	0	0	0
T9	0	3282	0	0
T20	311127	1744	0	0
T29	448588	478	0	0
T30	4435	53	0	0
T31	9839	53	0	0
T43	159485	360	0	0
T44	1227	0	0	0

g_byte_assert.g_byte_output_masking[5].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	12743510	0	0
T1	84512	728	0	0
T2	116868	1368	0	0
T3	201179	1224	0	0
T4	0	1127	0	0
T7	14564	0	0	0
T9	0	3282	0	0
T20	311127	1744	0	0
T29	448588	478	0	0
T30	4435	53	0	0
T31	9839	53	0	0
T43	159485	360	0	0
T44	1227	0	0	0

g_byte_assert.g_byte_output_masking[6].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	12743510	0	0
T1	84512	728	0	0
T2	116868	1368	0	0
T3	201179	1224	0	0
T4	0	1127	0	0
T7	14564	0	0	0
T9	0	3282	0	0
T20	311127	1744	0	0
T29	448588	478	0	0
T30	4435	53	0	0
T31	9839	53	0	0
T43	159485	360	0	0
T44	1227	0	0	0

g_byte_assert.g_byte_output_masking[7].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	12743510	0	0
T1	84512	728	0	0
T2	116868	1368	0	0
T3	201179	1224	0	0
T4	0	1127	0	0
T7	14564	0	0	0
T9	0	3282	0	0
T20	311127	1744	0	0
T29	448588	478	0	0
T30	4435	53	0	0
T31	9839	53	0	0
T43	159485	360	0	0
T44	1227	0	0	0

gen_mask_assert.ContiguousOnesMask_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	26841106	0	0
T1	84512	1658	0	0
T2	116868	3111	0	0
T3	201179	2792	0	0
T4	0	1127	0	0
T7	14564	0	0	0
T9	0	4131	0	0
T20	311127	3981	0	0
T29	448588	1105	0	0
T30	4435	123	0	0
T31	9839	127	0	0
T43	159485	823	0	0
T44	1227	0	0	0