Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

45077695

1

T1

1234

T2

2548

T3

276

full_word

44888523

1

T1

5240

T2

4600

T3

314

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	89965918	1			T1	6474		T2	7148		T3	590
auto[TlIntgErrCmd]	101	1			T135	2		T136	4		T137	6
auto[TlIntgErrData]	96	1			T135	1		T136	3		T137	6
auto[TlIntgErrBoth]	103	1			T135	7		T136	3		T137	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49979060

1

T1

3827

T2

4207

T3

241

auto[1]

39987158

1

T1

2647

T2

2941

T3

349

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	30059452	1			T1	691		T2	1376		T3	150
auto[TlIntgErrNone]	partial	auto[1]	15017984	1			T1	543		T2	1172		T3	126
auto[TlIntgErrNone]	full_word	auto[0]	19919463	1			T1	3136		T2	2831		T3	91
auto[TlIntgErrNone]	full_word	auto[1]	24969019	1			T1	2104		T2	1769		T3	223
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T137	1		T182	2		T184	1
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T135	1		T136	3		T137	5
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T135	1		T136	1		T184	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T181	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	37	1			T135	1		T136	2		T137	2
auto[TlIntgErrData]	partial	auto[1]	40	1			T136	1		T137	3		T182	1
auto[TlIntgErrData]	full_word	auto[0]	8	1			T184	2		T185	1		T186	1
auto[TlIntgErrData]	full_word	auto[1]	11	1			T137	1		T182	1		T184	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T135	4		T136	1		T137	2
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T135	2		T136	1		T137	5
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T135	1		T136	1		T137	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T184	1		T187	1		T186	1