Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	544303189	54780	0	0
RunThenComplete_M	544303189	680033	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544303189	54780	0	0
T1	68449	40	0	0
T2	57396	73	0	0
T3	3518	3	0	0
T7	102771	12	0	0
T9	3428	1	0	0
T10	0	63	0	0
T11	6114	0	0	0
T21	651022	72	0	0
T28	7017	3	0	0
T41	1979	0	0	0
T42	967	0	0	0
T43	0	273	0	0
T45	0	337	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	544303189	680033	0	0
T1	68449	104	0	0
T2	57396	74	0	0
T3	3518	10	0	0
T7	102771	36	0	0
T9	3428	4	0	0
T10	0	309	0	0
T11	6114	0	0	0
T21	651022	378	0	0
T28	7017	10	0	0
T41	1979	0	0	0
T42	967	0	0	0
T43	0	411	0	0
T45	0	507	0	0