Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	545624455	10864	0	0
entropy_period_rd_A	545624455	1397	0	0
intr_enable_rd_A	545624455	2180	0	0
prefix_0_rd_A	545624455	1354	0	0
prefix_10_rd_A	545624455	1296	0	0
prefix_1_rd_A	545624455	1447	0	0
prefix_2_rd_A	545624455	1358	0	0
prefix_3_rd_A	545624455	1383	0	0
prefix_4_rd_A	545624455	1469	0	0
prefix_5_rd_A	545624455	1347	0	0
prefix_6_rd_A	545624455	1459	0	0
prefix_7_rd_A	545624455	1310	0	0
prefix_8_rd_A	545624455	1433	0	0
prefix_9_rd_A	545624455	1393	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545624455	10864	0	0
T4	533049	0	0	0
T12	802582	0	0	0
T13	87865	645	0	0
T18	187476	0	0	0
T58	91068	0	0	0
T63	0	1162	0	0
T64	0	4539	0	0
T65	209142	0	0	0
T88	0	1125	0	0
T97	9200	0	0	0
T98	102641	0	0	0
T112	8393	0	0	0
T113	703746	0	0	0
T135	0	2	0	0
T136	0	2	0	0
T141	0	212	0	0
T142	0	4	0	0
T143	0	51	0	0
T144	0	3	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545624455	1397	0	0
T63	193086	13	0	0
T83	1940	0	0	0
T99	696262	0	0	0
T101	0	22	0	0
T102	0	10	0	0
T135	0	56	0	0
T137	0	37	0	0
T142	0	2	0	0
T153	170319	0	0	0
T158	0	39	0	0
T159	0	220	0	0
T160	0	3	0	0
T161	0	9	0	0
T162	181187	0	0	0
T163	735730	0	0	0
T164	212508	0	0	0
T165	226910	0	0	0
T166	191760	0	0	0
T167	202470	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545624455	2180	0	0
T63	193086	4	0	0
T83	1940	0	0	0
T99	696262	0	0	0
T101	0	50	0	0
T102	0	22	0	0
T135	0	94	0	0
T142	0	7	0	0
T153	170319	0	0	0
T158	0	50	0	0
T159	0	240	0	0
T160	0	18	0	0
T161	0	3	0	0
T162	181187	0	0	0
T163	735730	0	0	0
T164	212508	0	0	0
T165	226910	0	0	0
T166	191760	0	0	0
T167	202470	0	0	0
T168	0	27	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545624455	1354	0	0
T63	193086	25	0	0
T83	1940	0	0	0
T99	696262	0	0	0
T101	0	23	0	0
T102	0	27	0	0
T135	0	39	0	0
T137	0	36	0	0
T142	0	12	0	0
T153	170319	0	0	0
T158	0	25	0	0
T159	0	191	0	0
T160	0	1	0	0
T161	0	10	0	0
T162	181187	0	0	0
T163	735730	0	0	0
T164	212508	0	0	0
T165	226910	0	0	0
T166	191760	0	0	0
T167	202470	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545624455	1296	0	0
T63	193086	2	0	0
T83	1940	0	0	0
T99	696262	0	0	0
T101	0	24	0	0
T102	0	7	0	0
T135	0	68	0	0
T137	0	34	0	0
T142	0	5	0	0
T153	170319	0	0	0
T158	0	3	0	0
T159	0	199	0	0
T160	0	1	0	0
T161	0	10	0	0
T162	181187	0	0	0
T163	735730	0	0	0
T164	212508	0	0	0
T165	226910	0	0	0
T166	191760	0	0	0
T167	202470	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545624455	1447	0	0
T63	193086	4	0	0
T83	1940	0	0	0
T99	696262	0	0	0
T101	0	22	0	0
T102	0	17	0	0
T106	0	31	0	0
T135	0	34	0	0
T137	0	41	0	0
T142	0	8	0	0
T153	170319	0	0	0
T158	0	27	0	0
T159	0	218	0	0
T160	0	10	0	0
T162	181187	0	0	0
T163	735730	0	0	0
T164	212508	0	0	0
T165	226910	0	0	0
T166	191760	0	0	0
T167	202470	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545624455	1358	0	0
T63	193086	4	0	0
T83	1940	0	0	0
T99	696262	0	0	0
T101	0	28	0	0
T102	0	11	0	0
T106	0	33	0	0
T135	0	47	0	0
T137	0	45	0	0
T142	0	4	0	0
T153	170319	0	0	0
T158	0	56	0	0
T159	0	209	0	0
T160	0	2	0	0
T162	181187	0	0	0
T163	735730	0	0	0
T164	212508	0	0	0
T165	226910	0	0	0
T166	191760	0	0	0
T167	202470	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545624455	1383	0	0
T63	193086	7	0	0
T83	1940	0	0	0
T99	696262	0	0	0
T101	0	39	0	0
T102	0	13	0	0
T106	0	20	0	0
T135	0	44	0	0
T137	0	51	0	0
T153	170319	0	0	0
T158	0	26	0	0
T159	0	189	0	0
T160	0	5	0	0
T161	0	1	0	0
T162	181187	0	0	0
T163	735730	0	0	0
T164	212508	0	0	0
T165	226910	0	0	0
T166	191760	0	0	0
T167	202470	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545624455	1469	0	0
T63	193086	5	0	0
T83	1940	0	0	0
T99	696262	0	0	0
T101	0	24	0	0
T102	0	24	0	0
T106	0	31	0	0
T135	0	42	0	0
T137	0	57	0	0
T142	0	8	0	0
T153	170319	0	0	0
T158	0	48	0	0
T159	0	241	0	0
T161	0	13	0	0
T162	181187	0	0	0
T163	735730	0	0	0
T164	212508	0	0	0
T165	226910	0	0	0
T166	191760	0	0	0
T167	202470	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545624455	1347	0	0
T63	193086	11	0	0
T83	1940	0	0	0
T99	696262	0	0	0
T101	0	24	0	0
T102	0	13	0	0
T135	0	39	0	0
T137	0	42	0	0
T142	0	1	0	0
T153	170319	0	0	0
T158	0	32	0	0
T159	0	220	0	0
T160	0	4	0	0
T161	0	9	0	0
T162	181187	0	0	0
T163	735730	0	0	0
T164	212508	0	0	0
T165	226910	0	0	0
T166	191760	0	0	0
T167	202470	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545624455	1459	0	0
T63	193086	6	0	0
T83	1940	0	0	0
T99	696262	0	0	0
T101	0	44	0	0
T102	0	21	0	0
T135	0	43	0	0
T137	0	41	0	0
T142	0	1	0	0
T153	170319	0	0	0
T158	0	68	0	0
T159	0	198	0	0
T160	0	8	0	0
T161	0	19	0	0
T162	181187	0	0	0
T163	735730	0	0	0
T164	212508	0	0	0
T165	226910	0	0	0
T166	191760	0	0	0
T167	202470	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545624455	1310	0	0
T101	11222	25	0	0
T102	4221	23	0	0
T106	6055	32	0	0
T135	11984	41	0	0
T137	20671	55	0	0
T142	4232	5	0	0
T158	11214	56	0	0
T159	26610	198	0	0
T160	1847	5	0	0
T161	2666	2	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545624455	1433	0	0
T63	193086	9	0	0
T83	1940	0	0	0
T99	696262	0	0	0
T101	0	22	0	0
T102	0	21	0	0
T135	0	43	0	0
T137	0	43	0	0
T142	0	3	0	0
T153	170319	0	0	0
T158	0	61	0	0
T159	0	224	0	0
T160	0	8	0	0
T161	0	11	0	0
T162	181187	0	0	0
T163	735730	0	0	0
T164	212508	0	0	0
T165	226910	0	0	0
T166	191760	0	0	0
T167	202470	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545624455	1393	0	0
T63	193086	21	0	0
T83	1940	0	0	0
T99	696262	0	0	0
T101	0	13	0	0
T102	0	22	0	0
T135	0	34	0	0
T137	0	26	0	0
T142	0	5	0	0
T153	170319	0	0	0
T158	0	82	0	0
T159	0	234	0	0
T160	0	1	0	0
T161	0	3	0	0
T162	181187	0	0	0
T163	735730	0	0	0
T164	212508	0	0	0
T165	226910	0	0	0
T166	191760	0	0	0
T167	202470	0	0	0