Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47454445	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

46454688

1

T1

12597

T2

4621

T3

445

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	52018291	1			T1	14739		T2	4187		T3	397
values[0x0]	20281174	1			T1	3803		T2	1412		T3	234
values[0x1]	21609668	1			T1	4335		T2	1514		T3	236

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36488504	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

57420629

1

T1

14986

T2

5202

T3

538

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	298537	1			T1	143		T2	21		T3	4
valid_sources[0x01]	301893	1			T1	121		T2	27		T3	3
valid_sources[0x02]	293670	1			T1	84		T2	22		T3	3
valid_sources[0x03]	302875	1			T1	105		T2	30		T3	3
valid_sources[0x04]	427832	1			T1	103		T2	25		T3	11
valid_sources[0x05]	299170	1			T1	105		T2	32		T41	71
valid_sources[0x06]	302870	1			T1	47		T2	35		T41	68
valid_sources[0x07]	296365	1			T1	143		T2	24		T3	3
valid_sources[0x08]	300564	1			T1	95		T2	15		T3	2
valid_sources[0x09]	315867	1			T1	100		T2	17		T3	3
valid_sources[0x0a]	298320	1			T1	97		T2	28		T3	2
valid_sources[0x0b]	301000	1			T1	136		T2	15		T41	55
valid_sources[0x0c]	413038	1			T1	50		T2	32		T3	4
valid_sources[0x0d]	295394	1			T1	71		T2	29		T3	4
valid_sources[0x0e]	315017	1			T1	91		T2	32		T3	5
valid_sources[0x0f]	297790	1			T1	88		T2	34		T3	1
valid_sources[0x10]	383699	1			T1	52		T2	19		T3	9
valid_sources[0x11]	322749	1			T1	71		T2	26		T3	4
valid_sources[0x12]	304422	1			T1	55		T2	23		T3	1
valid_sources[0x13]	299527	1			T1	78		T2	39		T3	6
valid_sources[0x14]	434871	1			T1	78		T2	10		T41	62
valid_sources[0x15]	302809	1			T1	79		T2	23		T3	1
valid_sources[0x16]	392511	1			T1	75		T2	20		T3	8
valid_sources[0x17]	304412	1			T1	66		T2	30		T41	59
valid_sources[0x18]	298807	1			T1	135		T2	26		T3	5
valid_sources[0x19]	302589	1			T1	139		T2	30		T3	10
valid_sources[0x1a]	1217913	1			T1	61		T2	25		T3	1
valid_sources[0x1b]	299455	1			T1	181		T2	22		T3	5
valid_sources[0x1c]	312132	1			T1	71		T2	30		T3	4
valid_sources[0x1d]	392004	1			T1	82		T2	29		T41	70
valid_sources[0x1e]	304324	1			T1	98		T2	18		T3	3
valid_sources[0x1f]	298523	1			T1	36		T2	30		T3	9
valid_sources[0x20]	301461	1			T1	66		T2	40		T3	2
valid_sources[0x21]	297567	1			T1	107		T2	39		T3	4
valid_sources[0x22]	301990	1			T1	91		T2	27		T3	9
valid_sources[0x23]	300741	1			T1	83		T2	25		T3	22
valid_sources[0x24]	299673	1			T1	115		T2	28		T41	70
valid_sources[0x25]	298138	1			T1	97		T2	34		T3	5
valid_sources[0x26]	579066	1			T1	53		T2	24		T3	4
valid_sources[0x27]	296590	1			T1	39		T2	13		T3	6
valid_sources[0x28]	485628	1			T1	117		T2	27		T41	69
valid_sources[0x29]	301921	1			T1	73		T2	35		T3	4
valid_sources[0x2a]	304198	1			T1	106		T2	28		T41	59
valid_sources[0x2b]	301100	1			T1	54		T2	50		T3	3
valid_sources[0x2c]	369025	1			T1	93		T2	23		T3	3
valid_sources[0x2d]	302784	1			T1	62		T2	26		T3	4
valid_sources[0x2e]	298807	1			T1	151		T2	26		T3	16
valid_sources[0x2f]	297082	1			T1	85		T2	23		T3	1
valid_sources[0x30]	710675	1			T1	71		T2	21		T3	2
valid_sources[0x31]	300112	1			T1	95		T2	22		T3	1
valid_sources[0x32]	299434	1			T1	62		T2	27		T41	74
valid_sources[0x33]	306764	1			T1	71		T2	31		T3	13
valid_sources[0x34]	297894	1			T1	69		T2	24		T3	7
valid_sources[0x35]	299824	1			T1	97		T2	24		T41	71
valid_sources[0x36]	297925	1			T1	64		T2	55		T3	13
valid_sources[0x37]	563309	1			T1	42		T2	22		T3	1
valid_sources[0x38]	300971	1			T1	103		T2	38		T3	3
valid_sources[0x39]	300958	1			T1	75		T2	15		T41	58
valid_sources[0x3a]	295105	1			T1	107		T2	19		T3	11
valid_sources[0x3b]	296047	1			T1	135		T2	26		T3	1
valid_sources[0x3c]	295316	1			T1	101		T2	30		T3	11
valid_sources[0x3d]	481747	1			T1	51		T2	20		T3	2
valid_sources[0x3e]	312439	1			T1	86		T2	9		T3	2
valid_sources[0x3f]	325737	1			T1	125		T2	33		T41	55
valid_sources[0x40]	297753	1			T1	50		T2	26		T41	54
valid_sources[0x41]	300385	1			T1	67		T2	43		T41	87
valid_sources[0x42]	298530	1			T1	75		T2	35		T3	5
valid_sources[0x43]	298711	1			T1	82		T2	36		T3	3
valid_sources[0x44]	300573	1			T1	63		T2	26		T41	102
valid_sources[0x45]	303982	1			T1	98		T2	30		T3	8
valid_sources[0x46]	298374	1			T1	68		T2	41		T41	65
valid_sources[0x47]	382319	1			T1	100		T2	35		T3	4
valid_sources[0x48]	299662	1			T1	106		T2	43		T41	58
valid_sources[0x49]	294862	1			T1	85		T2	18		T41	77
valid_sources[0x4a]	302669	1			T1	142		T2	21		T41	66
valid_sources[0x4b]	295795	1			T1	78		T2	36		T3	6
valid_sources[0x4c]	304790	1			T1	129		T2	26		T41	84
valid_sources[0x4d]	461805	1			T1	119		T2	35		T3	6
valid_sources[0x4e]	308900	1			T1	116		T2	24		T3	10
valid_sources[0x4f]	464862	1			T1	118		T2	28		T41	62
valid_sources[0x50]	300357	1			T1	78		T2	48		T3	2
valid_sources[0x51]	302274	1			T1	172		T2	25		T41	54
valid_sources[0x52]	480688	1			T1	69		T2	32		T3	11
valid_sources[0x53]	297333	1			T1	70		T2	27		T3	9
valid_sources[0x54]	643931	1			T1	88		T2	45		T41	70
valid_sources[0x55]	384732	1			T1	105		T2	22		T3	3
valid_sources[0x56]	294994	1			T1	92		T2	19		T3	1
valid_sources[0x57]	298667	1			T1	154		T2	36		T3	12
valid_sources[0x58]	302947	1			T1	76		T2	33		T3	1
valid_sources[0x59]	297288	1			T1	102		T2	18		T41	68
valid_sources[0x5a]	432447	1			T1	76		T2	16		T41	72
valid_sources[0x5b]	299142	1			T1	71		T2	57		T3	6
valid_sources[0x5c]	298254	1			T1	80		T2	21		T41	77
valid_sources[0x5d]	339047	1			T1	75		T2	24		T3	1
valid_sources[0x5e]	308910	1			T1	107		T2	37		T3	6
valid_sources[0x5f]	304994	1			T1	74		T2	23		T41	70
valid_sources[0x60]	360392	1			T1	50		T2	44		T3	5
valid_sources[0x61]	300691	1			T1	71		T2	43		T41	50
valid_sources[0x62]	296640	1			T1	84		T2	34		T3	20
valid_sources[0x63]	301826	1			T1	71		T2	21		T3	2
valid_sources[0x64]	303104	1			T1	71		T2	36		T41	70
valid_sources[0x65]	298254	1			T1	112		T2	25		T3	1
valid_sources[0x66]	298290	1			T1	87		T2	21		T41	57
valid_sources[0x67]	298148	1			T1	70		T2	33		T41	60
valid_sources[0x68]	465036	1			T1	121		T2	23		T3	15
valid_sources[0x69]	300907	1			T1	101		T2	37		T3	2
valid_sources[0x6a]	302120	1			T1	73		T2	29		T3	2
valid_sources[0x6b]	298103	1			T1	92		T2	24		T41	73
valid_sources[0x6c]	429504	1			T1	122		T2	31		T41	47
valid_sources[0x6d]	299557	1			T1	66		T2	22		T41	47
valid_sources[0x6e]	884746	1			T1	42		T2	18		T41	55
valid_sources[0x6f]	299246	1			T1	123		T2	33		T3	8
valid_sources[0x70]	741388	1			T1	64		T2	28		T3	1
valid_sources[0x71]	297689	1			T1	87		T2	9		T41	65
valid_sources[0x72]	393039	1			T1	116		T2	30		T3	12
valid_sources[0x73]	302010	1			T1	57		T2	23		T3	3
valid_sources[0x74]	433626	1			T1	36		T2	36		T41	61
valid_sources[0x75]	298951	1			T1	95		T2	37		T41	68
valid_sources[0x76]	852228	1			T1	113		T2	29		T3	2
valid_sources[0x77]	298652	1			T1	140		T2	24		T41	77
valid_sources[0x78]	299213	1			T1	86		T2	41		T41	64
valid_sources[0x79]	1393868	1			T1	63		T2	20		T3	5
valid_sources[0x7a]	580906	1			T1	75		T2	30		T3	2
valid_sources[0x7b]	383137	1			T1	40		T2	35		T3	2
valid_sources[0x7c]	297320	1			T1	82		T2	17		T3	3
valid_sources[0x7d]	297349	1			T1	107		T2	26		T41	60
valid_sources[0x7e]	318358	1			T1	62		T2	31		T3	4
valid_sources[0x7f]	299188	1			T1	61		T2	40		T41	51
valid_sources[0x80]	329083	1			T1	71		T2	25		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

20688624

1

T1

8386

T2

2841

T3

169

values[0x0]

all_enables

biggest_size

13555704

1

T1

2226

T2

931

T3

143

values[0x1]

all_enables

biggest_size

12210360

1

T1

1985

T2

849

T3

133