Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

47512468

1

T1

10280

T2

2492

T3

422

full_word

46458345

1

T1

12597

T2

4621

T3

445

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	93970533	1			T1	22877		T2	7113		T3	867
auto[TlIntgErrCmd]	104	1			T127	3		T128	4		T129	6
auto[TlIntgErrData]	91	1			T127	6		T128	2		T129	7
auto[TlIntgErrBoth]	85	1			T127	1		T128	4		T129	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52032661

1

T1

14739

T2

4187

T3

397

auto[1]

41938152

1

T1

8138

T2

2926

T3

470

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	31342879	1			T1	6353		T2	1346		T3	228
auto[TlIntgErrNone]	partial	auto[1]	16169337	1			T1	3927		T2	1146		T3	194
auto[TlIntgErrNone]	full_word	auto[0]	20689674	1			T1	8386		T2	2841		T3	169
auto[TlIntgErrNone]	full_word	auto[1]	25768643	1			T1	4211		T2	1780		T3	276
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T128	2		T129	3		T160	2
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T127	3		T128	2		T129	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T170	1		T176	1		T175	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T174	1		T177	1		T178	1
auto[TlIntgErrData]	partial	auto[0]	28	1			T127	1		T128	1		T129	1
auto[TlIntgErrData]	partial	auto[1]	50	1			T127	3		T128	1		T129	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T129	1		T173	1		T178	2
auto[TlIntgErrData]	full_word	auto[1]	8	1			T127	2		T129	3		T173	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T128	1		T129	2		T160	1
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T127	1		T128	3		T129	5
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T170	1		T179	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T170	1		T180	1		T179	1