Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.05	87.50	92.68			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_app_intf.u_appid_arb	95.05	87.50	92.68			100.00	100.00

---

Module Instance : tb.dut.u_app_intf.u_appid_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.05	87.50	92.68			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.05	87.50	92.68			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.71	94.57	86.30		46.67	91.01	100.00	u_app_intf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		32	28	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	97	1	1	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	0	0.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         3/3                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T7 T10 T4  | T10 T4 T15  | T10 T4 T15 
86                                  assign idx_tree[Pa]      = offset;
87         0/3     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         3/3                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T7 T10 T4  | T10 T4 T15  | T4 T9 T11 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97         1/1                      assign unused_sigs = gnt_tree[Pa];
           Tests:       T10 T15 T16 
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T7 T10 T4 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T7 T10 T4 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T7 T10 T4 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T7 T10 T4 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T7 T10 T4 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T7 T10 T4 
***repeat 1
105        1/1                      sel = ~req_tree[C0];
           Tests:       T7 T10 T4 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T7 T10 T4 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T7 T10 T4 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T7 T10 T4 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T7 T10 T4 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T7 T10 T4 
***repeat 2
105        1/1                      sel = ~req_tree[C0];
           Tests:       T10 T4 T15 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T10 T4 T15 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T10 T4 T15 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T10 T4 T15 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T10 T4 T15 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T10 T4 T15 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        0/1     ==>        assign unused_data = data_tree[0];
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T4 T9 T11 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T7 T10 T4 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T7 T10 T4 

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	41	38	92.68
Logical	41	38	92.68
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T4
0	1	Covered	T4,T9,T11
1	0	Covered	T7,T10,T4

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T4
0	1	Covered	T4,T9,T11
1	0	Covered	T7,T10,T4

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T4,T15
0	1	Unreachable
1	0	Covered	T10,T4,T15

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T10,T4
1	Covered	T7,T10,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T10,T4
1	Covered	T7,T10,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T10,T4,T15
1	Covered	T10,T4,T15

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T10,T4
1	Covered	T7,T10,T4

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T10,T4
1	Covered	T7,T10,T4

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T10,T4,T15
1	Covered	T10,T4,T15

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T10,T4
1	0	Covered	T4,T9,T11
1	1	Covered	T7,T4,T9

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T10,T4
1	0	Covered	T4,T9,T11
1	1	Covered	T7,T4,T9

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T4,T15
1	0	Not Covered
1	1	Covered	T4,T9,T11

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T10,T4
1	0	Covered	T7,T4,T9
1	1	Covered	T4,T9,T11

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T10,T4
1	0	Covered	T7,T4,T9
1	1	Covered	T4,T9,T11

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T4,T15
1	0	Covered	T4,T9,T11
1	1	Not Covered

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T10,T4
1	1	Covered	T7,T4,T9

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T4
0	Covered	T7,T10,T4

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T4
0	Covered	T7,T10,T4

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T4
0	Covered	T7,T10,T4

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T4
0	Covered	T7,T10,T4

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T10,T4,T15
0	Covered	T10,T4,T15

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T10,T4,T15
0	Covered	T10,T4,T15

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	617143802	616987707	0	0
CheckNGreaterZero_A	666	666	0	0
GntImpliesReady_A	617143802	6743	0	0
GntImpliesValid_A	617143802	6743	0	0
GrantKnown_A	617143802	616987707	0	0
IdxKnown_A	617143802	616987707	0	0
IndexIsCorrect_A	617143802	6743	0	0
NoReadyValidNoGrant_A	617143802	614186530	0	0
Priority_A	617143802	2801177	0	0
ReadyAndValidImplyGrant_A	617143802	6743	0	0
ReqAndReadyImplyGrant_A	617143802	6743	0	0
ReqImpliesValid_A	617143802	2801177	0	0
ValidKnown_A	617143802	616987707	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617143802	616987707	0	0
T1	173403	173352	0	0
T2	91647	91583	0	0
T3	8020	7932	0	0
T7	162918	162822	0	0
T10	4223	4073	0	0
T29	244494	244444	0	0
T30	3874	3787	0	0
T41	688223	688149	0	0
T42	1016	924	0	0
T43	1452	1374	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	666	666	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617143802	6743	0	0
T4	223637	70	0	0
T5	0	146	0	0
T7	162918	20	0	0
T8	0	15	0	0
T9	0	3	0	0
T10	4223	0	0	0
T11	0	31	0	0
T12	0	27	0	0
T13	0	28	0	0
T15	233034	0	0	0
T20	0	1	0	0
T31	0	1	0	0
T42	1016	0	0	0
T43	1452	0	0	0
T44	1325	0	0	0
T45	105552	0	0	0
T46	8951	0	0	0
T47	245430	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617143802	6743	0	0
T4	223637	70	0	0
T5	0	146	0	0
T7	162918	20	0	0
T8	0	15	0	0
T9	0	3	0	0
T10	4223	0	0	0
T11	0	31	0	0
T12	0	27	0	0
T13	0	28	0	0
T15	233034	0	0	0
T20	0	1	0	0
T31	0	1	0	0
T42	1016	0	0	0
T43	1452	0	0	0
T44	1325	0	0	0
T45	105552	0	0	0
T46	8951	0	0	0
T47	245430	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617143802	616987707	0	0
T1	173403	173352	0	0
T2	91647	91583	0	0
T3	8020	7932	0	0
T7	162918	162822	0	0
T10	4223	4073	0	0
T29	244494	244444	0	0
T30	3874	3787	0	0
T41	688223	688149	0	0
T42	1016	924	0	0
T43	1452	1374	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617143802	616987707	0	0
T1	173403	173352	0	0
T2	91647	91583	0	0
T3	8020	7932	0	0
T7	162918	162822	0	0
T10	4223	4073	0	0
T29	244494	244444	0	0
T30	3874	3787	0	0
T41	688223	688149	0	0
T42	1016	924	0	0
T43	1452	1374	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617143802	6743	0	0
T4	223637	70	0	0
T5	0	146	0	0
T7	162918	20	0	0
T8	0	15	0	0
T9	0	3	0	0
T10	4223	0	0	0
T11	0	31	0	0
T12	0	27	0	0
T13	0	28	0	0
T15	233034	0	0	0
T20	0	1	0	0
T31	0	1	0	0
T42	1016	0	0	0
T43	1452	0	0	0
T44	1325	0	0	0
T45	105552	0	0	0
T46	8951	0	0	0
T47	245430	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617143802	614186530	0	0
T1	173403	173352	0	0
T2	91647	91583	0	0
T3	8020	7932	0	0
T7	162918	161371	0	0
T10	4223	1294	0	0
T29	244494	244444	0	0
T30	3874	3787	0	0
T41	688223	688149	0	0
T42	1016	924	0	0
T43	1452	1374	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617143802	2801177	0	0
T4	223637	4145	0	0
T7	162918	1451	0	0
T8	0	881	0	0
T9	0	244	0	0
T10	4223	2779	0	0
T11	0	15989	0	0
T12	0	8961	0	0
T15	233034	202473	0	0
T16	0	377	0	0
T20	0	8	0	0
T42	1016	0	0	0
T43	1452	0	0	0
T44	1325	0	0	0
T45	105552	0	0	0
T46	8951	0	0	0
T47	245430	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617143802	6743	0	0
T4	223637	70	0	0
T5	0	146	0	0
T7	162918	20	0	0
T8	0	15	0	0
T9	0	3	0	0
T10	4223	0	0	0
T11	0	31	0	0
T12	0	27	0	0
T13	0	28	0	0
T15	233034	0	0	0
T20	0	1	0	0
T31	0	1	0	0
T42	1016	0	0	0
T43	1452	0	0	0
T44	1325	0	0	0
T45	105552	0	0	0
T46	8951	0	0	0
T47	245430	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617143802	6743	0	0
T4	223637	70	0	0
T5	0	146	0	0
T7	162918	20	0	0
T8	0	15	0	0
T9	0	3	0	0
T10	4223	0	0	0
T11	0	31	0	0
T12	0	27	0	0
T13	0	28	0	0
T15	233034	0	0	0
T20	0	1	0	0
T31	0	1	0	0
T42	1016	0	0	0
T43	1452	0	0	0
T44	1325	0	0	0
T45	105552	0	0	0
T46	8951	0	0	0
T47	245430	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617143802	2801177	0	0
T4	223637	4145	0	0
T7	162918	1451	0	0
T8	0	881	0	0
T9	0	244	0	0
T10	4223	2779	0	0
T11	0	15989	0	0
T12	0	8961	0	0
T15	233034	202473	0	0
T16	0	377	0	0
T20	0	8	0	0
T42	1016	0	0	0
T43	1452	0	0	0
T44	1325	0	0	0
T45	105552	0	0	0
T46	8951	0	0	0
T47	245430	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617143802	616987707	0	0
T1	173403	173352	0	0
T2	91647	91583	0	0
T3	8020	7932	0	0
T7	162918	162822	0	0
T10	4223	4073	0	0
T29	244494	244444	0	0
T30	3874	3787	0	0
T41	688223	688149	0	0
T42	1016	924	0	0
T43	1452	1374	0	0