Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	617143802	53512	0	0
RunThenComplete_M	617143802	696021	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617143802	53512	0	0
T1	173403	19	0	0
T2	91647	73	0	0
T3	8020	3	0	0
T4	0	34	0	0
T7	162918	20	0	0
T10	4223	0	0	0
T29	244494	127	0	0
T30	3874	3	0	0
T41	688223	145	0	0
T42	1016	0	0	0
T43	1452	0	0	0
T45	0	105	0	0
T46	0	3	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	617143802	696021	0	0
T1	173403	112	0	0
T2	91647	74	0	0
T3	8020	11	0	0
T4	0	146	0	0
T7	162918	60	0	0
T10	4223	0	0	0
T29	244494	319	0	0
T30	3874	11	0	0
T41	688223	146	0	0
T42	1016	0	0	0
T43	1452	0	0	0
T45	0	106	0	0
T46	0	11	0	0