Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	618574867	57927554	0	0
DepthKnown_A	618574867	618371885	0	0
RvalidKnown_A	618574867	618371885	0	0
WreadyKnown_A	618574867	618371885	0	0
gen_passthru_fifo.paramCheckPass	881	881	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618574867	57927554	0	0
T1	173403	12850	0	0
T2	91647	3998	0	0
T3	8020	630	0	0
T7	162918	2353	0	0
T10	4223	123	0	0
T29	244494	11107	0	0
T30	3874	572	0	0
T41	688223	11498	0	0
T42	1016	38	0	0
T43	1452	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618574867	618371885	0	0
T1	173403	173352	0	0
T2	91647	91583	0	0
T3	8020	7932	0	0
T7	162918	162822	0	0
T10	4223	4073	0	0
T29	244494	244444	0	0
T30	3874	3787	0	0
T41	688223	688149	0	0
T42	1016	924	0	0
T43	1452	1374	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618574867	618371885	0	0
T1	173403	173352	0	0
T2	91647	91583	0	0
T3	8020	7932	0	0
T7	162918	162822	0	0
T10	4223	4073	0	0
T29	244494	244444	0	0
T30	3874	3787	0	0
T41	688223	688149	0	0
T42	1016	924	0	0
T43	1452	1374	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618574867	618371885	0	0
T1	173403	173352	0	0
T2	91647	91583	0	0
T3	8020	7932	0	0
T7	162918	162822	0	0
T10	4223	4073	0	0
T29	244494	244444	0	0
T30	3874	3787	0	0
T41	688223	688149	0	0
T42	1016	924	0	0
T43	1452	1374	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	618574867	108449986	0	0
DepthKnown_A	618574867	618371885	0	0
RvalidKnown_A	618574867	618371885	0	0
WreadyKnown_A	618574867	618371885	0	0
gen_passthru_fifo.paramCheckPass	881	881	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618574867	108449986	0	0
T1	173403	12850	0	0
T2	91647	3998	0	0
T3	8020	630	0	0
T7	162918	2353	0	0
T10	4223	123	0	0
T29	244494	11107	0	0
T30	3874	572	0	0
T41	688223	11498	0	0
T42	1016	38	0	0
T43	1452	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618574867	618371885	0	0
T1	173403	173352	0	0
T2	91647	91583	0	0
T3	8020	7932	0	0
T7	162918	162822	0	0
T10	4223	4073	0	0
T29	244494	244444	0	0
T30	3874	3787	0	0
T41	688223	688149	0	0
T42	1016	924	0	0
T43	1452	1374	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618574867	618371885	0	0
T1	173403	173352	0	0
T2	91647	91583	0	0
T3	8020	7932	0	0
T7	162918	162822	0	0
T10	4223	4073	0	0
T29	244494	244444	0	0
T30	3874	3787	0	0
T41	688223	688149	0	0
T42	1016	924	0	0
T43	1452	1374	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618574867	618371885	0	0
T1	173403	173352	0	0
T2	91647	91583	0	0
T3	8020	7932	0	0
T7	162918	162822	0	0
T10	4223	4073	0	0
T29	244494	244444	0	0
T30	3874	3787	0	0
T41	688223	688149	0	0
T42	1016	924	0	0
T43	1452	1374	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0