Unified Coverage Report :: Module :: prim_slicer

Module : prim_slicer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_kmac_core.gen_key_slicer[0].u_key_slicer	100.00	100.00					100.00
tb.dut.u_kmac_core.gen_key_slicer[1].u_key_slicer	100.00	100.00					100.00
tb.dut.u_sha3.u_pad.u_prefix_slicer	100.00	100.00					100.00
tb.dut.u_staterd.gen_slicer[0].u_state_slice	100.00	100.00					100.00
tb.dut.u_staterd.gen_slicer[1].u_state_slice	100.00	100.00					100.00

---

Module Instance : tb.dut.u_kmac_core.gen_key_slicer[0].u_key_slicer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.57	100.00	100.00		100.00	92.86	100.00	u_kmac_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_kmac_core.gen_key_slicer[1].u_key_slicer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.57	100.00	100.00		100.00	92.86	100.00	u_kmac_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sha3.u_pad.u_prefix_slicer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.59	99.41	88.37		94.44	95.70	100.00	u_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_staterd.gen_slicer[0].u_state_slice

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.00	100.00	70.00			100.00		u_staterd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_staterd.gen_slicer[1].u_state_slice

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.00	100.00	70.00			100.00		u_staterd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_slicer

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	25	1	1	100.00
CONT_ASSIGN	27	1	1	100.00

24                      
25         1/1            assign unrolled_data = UnrollW'(data_i);
           Tests:       T1 T2 T3 
26                      
27         1/1            assign data_o = unrolled_data[sel_i*OutW+:OutW];
           Tests:       T1 T2 T3 

---

Assert Coverage for Module : prim_slicer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ValidWidth_A	3330	3330	0	0

ValidWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3330	3330	0	0
T1	5	5	0	0
T2	5	5	0	0
T3	5	5	0	0
T7	5	5	0	0
T10	5	5	0	0
T29	5	5	0	0
T30	5	5	0	0
T41	5	5	0	0
T42	5	5	0	0
T43	5	5	0	0

Line Coverage for Instance : tb.dut.u_kmac_core.gen_key_slicer[0].u_key_slicer

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	25	1	1	100.00
CONT_ASSIGN	27	1	1	100.00

24                      
25         1/1            assign unrolled_data = UnrollW'(data_i);
           Tests:       T1 T2 T3 
26                      
27         1/1            assign data_o = unrolled_data[sel_i*OutW+:OutW];
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_kmac_core.gen_key_slicer[0].u_key_slicer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ValidWidth_A	666	666	0	0

ValidWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	666	666	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0

Line Coverage for Instance : tb.dut.u_kmac_core.gen_key_slicer[1].u_key_slicer

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	25	1	1	100.00
CONT_ASSIGN	27	1	1	100.00

24                      
25         1/1            assign unrolled_data = UnrollW'(data_i);
           Tests:       T1 T2 T3 
26                      
27         1/1            assign data_o = unrolled_data[sel_i*OutW+:OutW];
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_kmac_core.gen_key_slicer[1].u_key_slicer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ValidWidth_A	666	666	0	0

ValidWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	666	666	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0

Line Coverage for Instance : tb.dut.u_sha3.u_pad.u_prefix_slicer

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	25	1	1	100.00
CONT_ASSIGN	27	1	1	100.00

24                      
25         1/1            assign unrolled_data = UnrollW'(data_i);
           Tests:       T1 T2 T3 
26                      
27         1/1            assign data_o = unrolled_data[sel_i*OutW+:OutW];
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_sha3.u_pad.u_prefix_slicer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ValidWidth_A	666	666	0	0

ValidWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	666	666	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0

Line Coverage for Instance : tb.dut.u_staterd.gen_slicer[0].u_state_slice

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	25	1	1	100.00
CONT_ASSIGN	27	1	1	100.00

24                      
25         1/1            assign unrolled_data = UnrollW'(data_i);
           Tests:       T1 T2 T3 
26                      
27         1/1            assign data_o = unrolled_data[sel_i*OutW+:OutW];
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_staterd.gen_slicer[0].u_state_slice

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ValidWidth_A	666	666	0	0

ValidWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	666	666	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0

Line Coverage for Instance : tb.dut.u_staterd.gen_slicer[1].u_state_slice

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	25	1	1	100.00
CONT_ASSIGN	27	1	1	100.00

24                      
25         1/1            assign unrolled_data = UnrollW'(data_i);
           Tests:       T1 T2 T3 
26                      
27         1/1            assign data_o = unrolled_data[sel_i*OutW+:OutW];
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_staterd.gen_slicer[1].u_state_slice

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ValidWidth_A	666	666	0	0

ValidWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	666	666	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0