Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	618574867	10600	0	0
entropy_period_rd_A	618574867	1591	0	0
intr_enable_rd_A	618574867	2403	0	0
prefix_0_rd_A	618574867	1773	0	0
prefix_10_rd_A	618574867	1881	0	0
prefix_1_rd_A	618574867	1687	0	0
prefix_2_rd_A	618574867	1713	0	0
prefix_3_rd_A	618574867	1775	0	0
prefix_4_rd_A	618574867	1612	0	0
prefix_5_rd_A	618574867	1705	0	0
prefix_6_rd_A	618574867	1701	0	0
prefix_7_rd_A	618574867	1720	0	0
prefix_8_rd_A	618574867	1625	0	0
prefix_9_rd_A	618574867	1627	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618574867	10600	0	0
T5	246999	0	0	0
T13	492151	0	0	0
T31	191115	2065	0	0
T32	0	2300	0	0
T33	0	187	0	0
T38	253625	0	0	0
T57	0	1362	0	0
T58	336882	0	0	0
T71	0	1708	0	0
T110	539597	0	0	0
T127	0	3	0	0
T133	0	287	0	0
T134	0	1	0	0
T135	0	145	0	0
T136	0	3	0	0
T137	64880	0	0	0
T138	5107	0	0	0
T139	15815	0	0	0
T140	79467	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618574867	1591	0	0
T98	2422	6	0	0
T101	6837	25	0	0
T126	6022	36	0	0
T127	11624	73	0	0
T134	5077	13	0	0
T136	6337	16	0	0
T155	3771	9	0	0
T156	1662	6	0	0
T157	8703	11	0	0
T158	2363	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618574867	2403	0	0
T98	2422	7	0	0
T101	6837	85	0	0
T127	11624	69	0	0
T130	1513	24	0	0
T134	5077	13	0	0
T136	6337	11	0	0
T155	3771	5	0	0
T156	1662	13	0	0
T157	8703	49	0	0
T159	1046	29	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618574867	1773	0	0
T98	2422	1	0	0
T101	6837	34	0	0
T126	6022	31	0	0
T127	11624	41	0	0
T134	5077	6	0	0
T136	6337	4	0	0
T155	3771	11	0	0
T156	1662	10	0	0
T157	8703	17	0	0
T160	15227	24	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618574867	1881	0	0
T98	2422	8	0	0
T101	6837	31	0	0
T126	6022	24	0	0
T127	11624	38	0	0
T134	5077	7	0	0
T136	6337	10	0	0
T155	3771	11	0	0
T156	1662	1	0	0
T157	8703	14	0	0
T158	2363	5	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618574867	1687	0	0
T98	2422	7	0	0
T101	6837	23	0	0
T126	6022	13	0	0
T127	11624	58	0	0
T134	5077	10	0	0
T136	6337	7	0	0
T155	3771	7	0	0
T156	1662	4	0	0
T157	8703	18	0	0
T158	2363	7	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618574867	1713	0	0
T98	2422	1	0	0
T101	6837	37	0	0
T126	6022	24	0	0
T127	11624	42	0	0
T134	5077	5	0	0
T136	6337	8	0	0
T155	3771	6	0	0
T156	1662	7	0	0
T157	8703	20	0	0
T158	2363	6	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618574867	1775	0	0
T98	2422	1	0	0
T101	6837	27	0	0
T126	6022	35	0	0
T127	11624	36	0	0
T134	5077	9	0	0
T136	6337	14	0	0
T156	1662	8	0	0
T157	8703	14	0	0
T158	2363	9	0	0
T160	15227	31	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618574867	1612	0	0
T98	2422	3	0	0
T101	6837	28	0	0
T126	6022	25	0	0
T127	11624	26	0	0
T134	5077	8	0	0
T136	6337	7	0	0
T156	1662	1	0	0
T157	8703	10	0	0
T158	2363	1	0	0
T160	15227	37	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618574867	1705	0	0
T98	2422	2	0	0
T101	6837	37	0	0
T126	6022	19	0	0
T127	11624	52	0	0
T134	5077	4	0	0
T136	6337	6	0	0
T155	3771	3	0	0
T156	1662	2	0	0
T157	8703	20	0	0
T158	2363	9	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618574867	1701	0	0
T98	2422	6	0	0
T101	6837	30	0	0
T126	6022	23	0	0
T127	11624	59	0	0
T134	5077	1	0	0
T136	6337	14	0	0
T155	3771	8	0	0
T156	1662	5	0	0
T157	8703	14	0	0
T158	2363	1	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618574867	1720	0	0
T98	2422	8	0	0
T101	6837	20	0	0
T126	6022	26	0	0
T127	11624	54	0	0
T134	5077	16	0	0
T136	6337	9	0	0
T155	3771	3	0	0
T156	1662	9	0	0
T157	8703	24	0	0
T158	2363	2	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618574867	1625	0	0
T98	2422	1	0	0
T101	6837	28	0	0
T126	6022	27	0	0
T127	11624	43	0	0
T134	5077	11	0	0
T136	6337	12	0	0
T155	3771	5	0	0
T156	1662	3	0	0
T157	8703	24	0	0
T158	2363	5	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618574867	1627	0	0
T98	2422	1	0	0
T101	6837	29	0	0
T126	6022	18	0	0
T127	11624	47	0	0
T134	5077	11	0	0
T136	6337	2	0	0
T155	3771	13	0	0
T157	8703	5	0	0
T158	2363	3	0	0
T160	15227	47	0	0