Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
169324 |
1 |
|
|
T9 |
21 |
|
T4 |
865 |
|
T5 |
885 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
87058 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
61704 |
1 |
|
|
T9 |
20 |
|
T4 |
852 |
|
T5 |
871 |
seven_bytes |
2945 |
1 |
|
|
T14 |
11 |
|
T15 |
12 |
|
T111 |
79 |
six_bytes |
2902 |
1 |
|
|
T14 |
17 |
|
T15 |
11 |
|
T111 |
74 |
five_bytes |
2945 |
1 |
|
|
T14 |
7 |
|
T15 |
7 |
|
T111 |
73 |
four_bytes |
2979 |
1 |
|
|
T14 |
7 |
|
T15 |
17 |
|
T111 |
70 |
three_bytes |
2921 |
1 |
|
|
T14 |
15 |
|
T15 |
16 |
|
T111 |
84 |
two_bytes |
2935 |
1 |
|
|
T14 |
13 |
|
T15 |
13 |
|
T111 |
81 |
one_byte |
2935 |
1 |
|
|
T14 |
16 |
|
T15 |
15 |
|
T111 |
68 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
166070 |
1 |
|
|
T9 |
19 |
|
T4 |
839 |
|
T5 |
857 |
auto[1] |
3254 |
1 |
|
|
T9 |
2 |
|
T4 |
26 |
|
T5 |
28 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
169324 |
1 |
|
|
T9 |
21 |
|
T4 |
865 |
|
T5 |
885 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
169307 |
1 |
|
|
T9 |
21 |
|
T4 |
865 |
|
T5 |
885 |
auto[1] |
17 |
1 |
|
|
T111 |
1 |
|
T182 |
1 |
|
T183 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1117 |
1 |
|
|
T9 |
1 |
|
T4 |
13 |
|
T5 |
14 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3254 |
1 |
|
|
T9 |
2 |
|
T4 |
26 |
|
T5 |
28 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170820 |
1 |
|
|
T4 |
598 |
|
T10 |
3 |
|
T5 |
949 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
89030 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
60666 |
1 |
|
|
T4 |
589 |
|
T10 |
3 |
|
T5 |
936 |
seven_bytes |
3103 |
1 |
|
|
T14 |
24 |
|
T15 |
7 |
|
T111 |
58 |
six_bytes |
2984 |
1 |
|
|
T14 |
23 |
|
T15 |
15 |
|
T111 |
47 |
five_bytes |
3056 |
1 |
|
|
T14 |
29 |
|
T15 |
7 |
|
T111 |
45 |
four_bytes |
3047 |
1 |
|
|
T14 |
20 |
|
T15 |
11 |
|
T111 |
60 |
three_bytes |
3049 |
1 |
|
|
T14 |
18 |
|
T15 |
10 |
|
T111 |
44 |
two_bytes |
2898 |
1 |
|
|
T14 |
21 |
|
T15 |
10 |
|
T111 |
37 |
one_byte |
2987 |
1 |
|
|
T14 |
21 |
|
T15 |
6 |
|
T111 |
44 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
167532 |
1 |
|
|
T4 |
580 |
|
T10 |
3 |
|
T5 |
923 |
auto[1] |
3288 |
1 |
|
|
T4 |
18 |
|
T5 |
26 |
|
T13 |
4 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170820 |
1 |
|
|
T4 |
598 |
|
T10 |
3 |
|
T5 |
949 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170807 |
1 |
|
|
T4 |
598 |
|
T10 |
3 |
|
T5 |
949 |
auto[1] |
13 |
1 |
|
|
T110 |
1 |
|
T111 |
1 |
|
T79 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1147 |
1 |
|
|
T4 |
9 |
|
T5 |
13 |
|
T13 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3288 |
1 |
|
|
T4 |
18 |
|
T5 |
26 |
|
T13 |
4 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
332740 |
1 |
|
|
T4 |
962 |
|
T12 |
48 |
|
T5 |
1513 |
auto[1] |
407 |
1 |
|
|
T4 |
14 |
|
T5 |
26 |
|
T6 |
1 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
174246 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
117590 |
1 |
|
|
T4 |
962 |
|
T12 |
47 |
|
T5 |
1513 |
seven_bytes |
5820 |
1 |
|
|
T14 |
25 |
|
T15 |
35 |
|
T111 |
108 |
six_bytes |
5990 |
1 |
|
|
T14 |
26 |
|
T15 |
37 |
|
T111 |
113 |
five_bytes |
5911 |
1 |
|
|
T14 |
25 |
|
T15 |
26 |
|
T111 |
105 |
four_bytes |
5922 |
1 |
|
|
T14 |
19 |
|
T15 |
36 |
|
T111 |
101 |
three_bytes |
5866 |
1 |
|
|
T14 |
25 |
|
T15 |
32 |
|
T111 |
116 |
two_bytes |
5841 |
1 |
|
|
T14 |
24 |
|
T15 |
38 |
|
T111 |
100 |
one_byte |
5961 |
1 |
|
|
T14 |
17 |
|
T15 |
43 |
|
T111 |
108 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
326743 |
1 |
|
|
T4 |
948 |
|
T12 |
46 |
|
T5 |
1487 |
auto[1] |
6404 |
1 |
|
|
T4 |
28 |
|
T12 |
2 |
|
T5 |
52 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
333147 |
1 |
|
|
T4 |
976 |
|
T12 |
48 |
|
T5 |
1539 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
333123 |
1 |
|
|
T4 |
976 |
|
T12 |
48 |
|
T5 |
1539 |
auto[1] |
24 |
1 |
|
|
T110 |
1 |
|
T184 |
1 |
|
T185 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2226 |
1 |
|
|
T4 |
14 |
|
T12 |
1 |
|
T5 |
26 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6404 |
1 |
|
|
T4 |
28 |
|
T12 |
2 |
|
T5 |
52 |