Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	50932365	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

48496677

1

T1

18

T2

56

T3

439

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	55161825	1			T1	9		T2	29		T3	399
values[0x0]	21441536	1			T1	13		T2	32		T3	200
values[0x1]	22825681	1			T1	9		T2	31		T3	205

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	39158728	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

60270314

1

T1

21

T2

66

T3

517

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	410243	1			T7	3		T4	10		T12	20
valid_sources[0x01]	320193	1			T11	6		T7	5		T4	9
valid_sources[0x02]	311145	1			T11	6		T7	2		T4	8
valid_sources[0x03]	1069195	1			T11	3		T4	11		T12	24
valid_sources[0x04]	391702	1			T7	10		T4	21		T27	1
valid_sources[0x05]	317594	1			T11	3		T38	1		T7	7
valid_sources[0x06]	316055	1			T11	4		T7	6		T4	10
valid_sources[0x07]	317026	1			T1	31		T11	1		T4	4
valid_sources[0x08]	312747	1			T7	5		T4	6		T27	1
valid_sources[0x09]	320822	1			T4	17		T12	24		T10	1
valid_sources[0x0a]	317220	1			T11	5		T7	3		T4	17
valid_sources[0x0b]	317262	1			T11	4		T7	7		T4	11
valid_sources[0x0c]	317186	1			T11	1		T7	1		T4	6
valid_sources[0x0d]	317378	1			T11	1		T7	18		T4	4
valid_sources[0x0e]	315943	1			T4	5		T8	8		T12	23
valid_sources[0x0f]	320168	1			T11	4		T4	7		T8	8
valid_sources[0x10]	396582	1			T11	8		T7	1		T4	7
valid_sources[0x11]	316174	1			T11	2		T7	4		T4	4
valid_sources[0x12]	316750	1			T11	1		T7	2		T4	5
valid_sources[0x13]	312810	1			T11	12		T7	5		T4	9
valid_sources[0x14]	508078	1			T11	1		T4	4		T27	1
valid_sources[0x15]	450526	1			T11	3		T4	5		T12	28
valid_sources[0x16]	317511	1			T11	2		T7	4		T4	16
valid_sources[0x17]	321806	1			T38	1		T7	5		T9	1
valid_sources[0x18]	316422	1			T11	5		T7	3		T9	2920
valid_sources[0x19]	403844	1			T11	1		T4	15		T27	2
valid_sources[0x1a]	316726	1			T11	2		T4	17		T27	1
valid_sources[0x1b]	320398	1			T7	1		T4	19		T12	31
valid_sources[0x1c]	409746	1			T7	1		T4	3		T12	28
valid_sources[0x1d]	502166	1			T11	1		T38	1		T4	9
valid_sources[0x1e]	419069	1			T11	1		T7	1		T9	1
valid_sources[0x1f]	313211	1			T7	9		T4	14		T12	21
valid_sources[0x20]	316677	1			T4	20		T12	33		T10	1
valid_sources[0x21]	325167	1			T11	4		T7	2		T4	10
valid_sources[0x22]	630533	1			T11	3		T7	15		T4	7
valid_sources[0x23]	319094	1			T11	3		T4	3		T12	28
valid_sources[0x24]	315098	1			T11	8		T7	9		T4	6
valid_sources[0x25]	347552	1			T4	16		T12	28		T19	20
valid_sources[0x26]	317930	1			T11	2		T7	2		T4	9
valid_sources[0x27]	347052	1			T7	20		T4	9		T12	26
valid_sources[0x28]	332163	1			T7	6		T4	11		T12	30
valid_sources[0x29]	316543	1			T11	1		T7	2		T4	5
valid_sources[0x2a]	321535	1			T11	2		T7	1		T4	4
valid_sources[0x2b]	314438	1			T11	5		T7	4		T4	10
valid_sources[0x2c]	317458	1			T4	14		T12	30		T19	58
valid_sources[0x2d]	315249	1			T7	1		T4	8		T27	1
valid_sources[0x2e]	316985	1			T11	5		T7	1		T4	11
valid_sources[0x2f]	317982	1			T11	9		T7	2		T4	12
valid_sources[0x30]	525768	1			T11	3		T38	2		T7	3
valid_sources[0x31]	314558	1			T11	7		T38	1		T7	1
valid_sources[0x32]	450925	1			T11	4		T4	14		T27	2
valid_sources[0x33]	962821	1			T11	2		T4	12		T12	43
valid_sources[0x34]	316099	1			T4	20		T12	30		T10	4
valid_sources[0x35]	318242	1			T11	1		T7	2		T4	22
valid_sources[0x36]	871496	1			T11	2		T7	5		T4	10
valid_sources[0x37]	321335	1			T7	2		T4	15		T12	24
valid_sources[0x38]	314552	1			T7	1		T4	14		T12	35
valid_sources[0x39]	314992	1			T11	8		T38	1		T7	2
valid_sources[0x3a]	310326	1			T11	1		T4	10		T27	1
valid_sources[0x3b]	311826	1			T11	5		T7	13		T4	7
valid_sources[0x3c]	1355197	1			T11	1		T38	1		T7	9
valid_sources[0x3d]	317375	1			T7	4		T4	18		T12	26
valid_sources[0x3e]	319604	1			T7	6		T4	7		T8	2
valid_sources[0x3f]	356233	1			T11	9		T7	8		T9	1
valid_sources[0x40]	743689	1			T11	3		T7	20		T9	1
valid_sources[0x41]	318926	1			T11	1		T4	23		T27	1
valid_sources[0x42]	453120	1			T11	6		T7	6		T4	16
valid_sources[0x43]	315612	1			T11	8		T7	5		T4	13
valid_sources[0x44]	317156	1			T7	1		T4	16		T27	1
valid_sources[0x45]	319158	1			T11	1		T7	4		T4	8
valid_sources[0x46]	321221	1			T11	5		T9	1		T4	10
valid_sources[0x47]	313079	1			T11	2		T7	10		T4	18
valid_sources[0x48]	345218	1			T11	2		T7	9		T4	9
valid_sources[0x49]	458953	1			T11	4		T7	10		T4	11
valid_sources[0x4a]	1188079	1			T11	3		T7	7		T4	15
valid_sources[0x4b]	317581	1			T11	5		T7	1		T4	11
valid_sources[0x4c]	342509	1			T11	1		T4	9		T8	2
valid_sources[0x4d]	321522	1			T7	4		T4	8		T8	1
valid_sources[0x4e]	351259	1			T11	1		T38	1		T7	7
valid_sources[0x4f]	314712	1			T11	6		T7	4		T4	12
valid_sources[0x50]	314331	1			T11	3		T7	4		T4	10
valid_sources[0x51]	313049	1			T7	5		T4	7		T12	29
valid_sources[0x52]	338842	1			T11	5		T4	4		T8	1
valid_sources[0x53]	314475	1			T4	12		T12	31		T19	29
valid_sources[0x54]	327441	1			T11	9		T7	7		T4	5
valid_sources[0x55]	319144	1			T7	6		T4	11		T12	32
valid_sources[0x56]	319452	1			T11	3		T4	6		T12	33
valid_sources[0x57]	317784	1			T7	1		T4	10		T27	1
valid_sources[0x58]	369984	1			T11	4		T7	8		T4	8
valid_sources[0x59]	327557	1			T11	1		T4	9		T12	28
valid_sources[0x5a]	578224	1			T11	1		T7	25		T4	13
valid_sources[0x5b]	320609	1			T11	1		T4	16		T8	11
valid_sources[0x5c]	313250	1			T11	10		T4	6		T8	5
valid_sources[0x5d]	319405	1			T11	1		T38	1		T7	3
valid_sources[0x5e]	316522	1			T4	11		T12	31		T10	1
valid_sources[0x5f]	314163	1			T11	1		T7	1		T4	9
valid_sources[0x60]	336328	1			T7	5		T4	13		T12	22
valid_sources[0x61]	472876	1			T11	2		T7	2		T4	4
valid_sources[0x62]	334916	1			T11	1		T4	6		T12	33
valid_sources[0x63]	317463	1			T11	3		T7	7		T4	15
valid_sources[0x64]	317487	1			T7	20		T4	17		T8	2
valid_sources[0x65]	315634	1			T11	5		T38	1		T7	2
valid_sources[0x66]	318488	1			T11	1		T7	10		T4	3
valid_sources[0x67]	315786	1			T11	6		T7	8		T4	2
valid_sources[0x68]	315814	1			T11	6		T7	10		T4	6
valid_sources[0x69]	946496	1			T11	2		T7	9		T4	10
valid_sources[0x6a]	339391	1			T11	1		T7	3		T4	17
valid_sources[0x6b]	318322	1			T11	7		T7	1		T4	13
valid_sources[0x6c]	314471	1			T7	10		T4	10		T12	29
valid_sources[0x6d]	315549	1			T11	3		T9	1		T4	11
valid_sources[0x6e]	313527	1			T11	2		T7	1		T4	17
valid_sources[0x6f]	1437853	1			T7	3		T4	16		T12	29
valid_sources[0x70]	516051	1			T7	16		T9	1		T4	4
valid_sources[0x71]	324792	1			T11	1		T7	9		T4	5
valid_sources[0x72]	515468	1			T11	4		T4	7		T12	26
valid_sources[0x73]	675014	1			T11	5		T7	7		T9	1
valid_sources[0x74]	321873	1			T7	5		T4	29		T12	35
valid_sources[0x75]	329575	1			T11	10		T7	9		T4	9
valid_sources[0x76]	312960	1			T11	1		T7	1		T4	19
valid_sources[0x77]	360281	1			T38	1		T7	5		T4	8
valid_sources[0x78]	319350	1			T11	1		T38	1		T7	3
valid_sources[0x79]	315856	1			T7	5		T4	18		T27	1
valid_sources[0x7a]	314625	1			T11	2		T7	5		T9	1
valid_sources[0x7b]	319126	1			T11	1		T4	11		T12	29
valid_sources[0x7c]	792715	1			T7	2		T4	14		T8	8
valid_sources[0x7d]	410742	1			T11	3		T7	1		T4	11
valid_sources[0x7e]	318661	1			T11	4		T4	19		T39	520
valid_sources[0x7f]	319981	1			T11	6		T7	3		T4	3
valid_sources[0x80]	311816	1			T11	5		T7	15		T4	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

21232766

1

T1

4

T2

15

T3

163

values[0x0]

all_enables

biggest_size

14343841

1

T1

10

T2

22

T3

143

values[0x1]

all_enables

biggest_size

12920070

1

T1

4

T2

19

T3

133