Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

50984314

1

T1

13

T2

36

T3

365

full_word

48500168

1

T1

18

T2

56

T3

439

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	99484182	1			T1	31		T2	92		T3	804
auto[TlIntgErrCmd]	111	1			T122	6		T123	4		T124	7
auto[TlIntgErrData]	103	1			T122	10		T123	2		T124	5
auto[TlIntgErrBoth]	86	1			T122	4		T123	4		T124	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55174829

1

T1

9

T2

29

T3

399

auto[1]

44309653

1

T1

22

T2

63

T3

405

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	33940893	1			T1	5		T2	14		T3	236
auto[TlIntgErrNone]	partial	auto[1]	17043146	1			T1	8		T2	22		T3	129
auto[TlIntgErrNone]	full_word	auto[0]	21233804	1			T1	4		T2	15		T3	163
auto[TlIntgErrNone]	full_word	auto[1]	27266339	1			T1	14		T2	41		T3	276
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T123	1		T124	3		T188	3
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T122	6		T123	2		T124	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T189	1		T190	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T123	1		T191	1		T186	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T122	4		T123	1		T124	2
auto[TlIntgErrData]	partial	auto[1]	48	1			T122	4		T124	2		T188	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T122	2		T138	2		T192	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T123	1		T124	1		T193	1
auto[TlIntgErrBoth]	partial	auto[0]	29	1			T122	1		T123	2		T124	3
auto[TlIntgErrBoth]	partial	auto[1]	48	1			T122	3		T123	2		T124	5
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T138	1		T194	1		T187	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T191	1		T195	1		T138	1