Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	586252734	9837	0	0
entropy_period_rd_A	586252734	1149	0	0
intr_enable_rd_A	586252734	1937	0	0
prefix_0_rd_A	586252734	1052	0	0
prefix_10_rd_A	586252734	1153	0	0
prefix_1_rd_A	586252734	1124	0	0
prefix_2_rd_A	586252734	1091	0	0
prefix_3_rd_A	586252734	1163	0	0
prefix_4_rd_A	586252734	1035	0	0
prefix_5_rd_A	586252734	1168	0	0
prefix_6_rd_A	586252734	1081	0	0
prefix_7_rd_A	586252734	1056	0	0
prefix_8_rd_A	586252734	1097	0	0
prefix_9_rd_A	586252734	999	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	586252734	9837	0	0
T22	308689	0	0	0
T25	133380	0	0	0
T28	403357	6164	0	0
T78	922966	0	0	0
T116	0	145	0	0
T117	0	4	0	0
T122	0	1	0	0
T123	0	2	0	0
T129	0	264	0	0
T132	0	340	0	0
T133	0	103	0	0
T139	0	3	0	0
T140	0	1	0	0
T141	61075	0	0	0
T142	1391	0	0	0
T143	109894	0	0	0
T144	21174	0	0	0
T145	593215	0	0	0
T146	900436	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	586252734	1149	0	0
T96	4740	14	0	0
T97	7104	46	0	0
T101	11230	35	0	0
T107	9639	43	0	0
T109	9596	26	0	0
T117	8337	10	0	0
T124	25537	72	0	0
T169	4071	7	0	0
T170	4254	1	0	0
T171	1814	12	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	586252734	1937	0	0
T96	4740	5	0	0
T97	7104	57	0	0
T101	11230	59	0	0
T107	9639	26	0	0
T109	9596	25	0	0
T117	8337	29	0	0
T124	25537	154	0	0
T131	1393	15	0	0
T169	4071	16	0	0
T170	4254	16	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	586252734	1052	0	0
T96	4740	7	0	0
T97	7104	25	0	0
T101	11230	21	0	0
T107	9639	21	0	0
T109	9596	27	0	0
T117	8337	16	0	0
T124	25537	70	0	0
T169	4071	12	0	0
T170	4254	6	0	0
T171	1814	1	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	586252734	1153	0	0
T96	4740	12	0	0
T97	7104	29	0	0
T101	11230	31	0	0
T107	9639	18	0	0
T109	9596	14	0	0
T117	8337	12	0	0
T124	25537	87	0	0
T169	4071	12	0	0
T170	4254	6	0	0
T171	1814	9	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	586252734	1124	0	0
T96	4740	4	0	0
T97	7104	32	0	0
T101	11230	42	0	0
T107	9639	22	0	0
T109	9596	32	0	0
T117	8337	13	0	0
T124	25537	54	0	0
T169	4071	4	0	0
T170	4254	3	0	0
T171	1814	4	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	586252734	1091	0	0
T96	4740	10	0	0
T97	7104	19	0	0
T101	11230	18	0	0
T107	9639	20	0	0
T109	9596	43	0	0
T117	8337	20	0	0
T124	25537	82	0	0
T169	4071	10	0	0
T170	4254	1	0	0
T171	1814	4	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	586252734	1163	0	0
T96	4740	9	0	0
T97	7104	29	0	0
T101	11230	41	0	0
T107	9639	36	0	0
T109	9596	30	0	0
T117	8337	10	0	0
T124	25537	82	0	0
T169	4071	3	0	0
T171	1814	7	0	0
T172	2817	10	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	586252734	1035	0	0
T96	4740	6	0	0
T97	7104	41	0	0
T101	11230	33	0	0
T107	9639	27	0	0
T109	9596	7	0	0
T117	8337	17	0	0
T124	25537	96	0	0
T169	4071	6	0	0
T170	4254	2	0	0
T172	2817	13	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	586252734	1168	0	0
T96	4740	9	0	0
T97	7104	34	0	0
T101	11230	36	0	0
T107	9639	33	0	0
T109	9596	43	0	0
T117	8337	28	0	0
T124	25537	86	0	0
T169	4071	4	0	0
T170	4254	5	0	0
T172	2817	13	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	586252734	1081	0	0
T96	4740	5	0	0
T97	7104	26	0	0
T101	11230	26	0	0
T107	9639	32	0	0
T109	9596	17	0	0
T117	8337	19	0	0
T124	25537	72	0	0
T169	4071	17	0	0
T170	4254	7	0	0
T171	1814	8	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	586252734	1056	0	0
T96	4740	5	0	0
T97	7104	18	0	0
T101	11230	26	0	0
T107	9639	9	0	0
T109	9596	29	0	0
T117	8337	17	0	0
T124	25537	84	0	0
T169	4071	10	0	0
T170	4254	6	0	0
T171	1814	9	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	586252734	1097	0	0
T96	4740	7	0	0
T97	7104	30	0	0
T101	11230	33	0	0
T107	9639	20	0	0
T109	9596	30	0	0
T117	8337	21	0	0
T124	25537	77	0	0
T169	4071	6	0	0
T170	4254	4	0	0
T172	2817	8	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	586252734	999	0	0
T96	4740	9	0	0
T97	7104	24	0	0
T101	11230	25	0	0
T107	9639	24	0	0
T109	9596	27	0	0
T117	8337	14	0	0
T124	25537	75	0	0
T169	4071	5	0	0
T170	4254	4	0	0
T171	1814	4	0	0