Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	17235176	1			T1	87		T2	117		T11	767
all_values[1]	17235176	1			T1	87		T2	117		T11	767
all_values[2]	17235176	1			T1	87		T2	117		T11	767

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

517610

1

T1

106

T2

12

T11

30

auto[1]

51187918

1

T1

155

T2

339

T11

2271

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51487881

1

T1

246

T2

336

T11

1965

auto[1]

217647

1

T1

15

T2

15

T11

336

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	170065	1			T1	9		T2	4		T11	17
all_values[0]	auto[0]	auto[1]	1367	1			T1	4		T2	2		T11	4
all_values[0]	auto[1]	auto[0]	16992562	1			T1	73		T2	108		T11	638
all_values[0]	auto[1]	auto[1]	71182	1			T1	1		T2	3		T11	108
all_values[1]	auto[0]	auto[0]	160730	1			T1	82		T2	4		T50	1
all_values[1]	auto[0]	auto[1]	962	1			T1	5		T2	2		T50	2
all_values[1]	auto[1]	auto[0]	17001897	1			T2	108		T11	655		T49	1865
all_values[1]	auto[1]	auto[1]	71587	1			T2	3		T11	112		T49	157
all_values[2]	auto[0]	auto[0]	183445	1			T1	4		T11	7		T49	5
all_values[2]	auto[0]	auto[1]	1041	1			T1	2		T11	2		T49	2
all_values[2]	auto[1]	auto[0]	16979182	1			T1	78		T2	112		T11	648
all_values[2]	auto[1]	auto[1]	71508	1			T1	3		T2	5		T11	110