Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56008 |
1 |
|
|
T1 |
6 |
|
T2 |
2 |
|
T11 |
2 |
auto[1] |
54508 |
1 |
|
|
T2 |
4 |
|
T11 |
136 |
|
T53 |
4 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
27224 |
1 |
|
|
T1 |
3 |
|
T11 |
41 |
|
T49 |
49 |
lower_val |
27352 |
1 |
|
|
T2 |
5 |
|
T11 |
46 |
|
T49 |
58 |
zero_val |
869 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T11 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
41410 |
1 |
|
|
T1 |
2 |
|
T11 |
56 |
|
T49 |
98 |
lower_val |
41686 |
1 |
|
|
T1 |
4 |
|
T11 |
40 |
|
T49 |
112 |
zero_val |
27420 |
1 |
|
|
T2 |
6 |
|
T11 |
42 |
|
T9 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
6755 |
1 |
|
|
T1 |
1 |
|
T49 |
25 |
|
T55 |
1 |
higher_val |
higher_val |
auto[1] |
3436 |
1 |
|
|
T11 |
20 |
|
T4 |
8 |
|
T31 |
3 |
higher_val |
lower_val |
auto[0] |
6754 |
1 |
|
|
T1 |
2 |
|
T49 |
24 |
|
T50 |
26 |
higher_val |
lower_val |
auto[1] |
3493 |
1 |
|
|
T11 |
13 |
|
T4 |
5 |
|
T31 |
1 |
higher_val |
zero_val |
auto[0] |
64 |
1 |
|
|
T9 |
1 |
|
T4 |
1 |
|
T14 |
1 |
higher_val |
zero_val |
auto[1] |
6722 |
1 |
|
|
T11 |
8 |
|
T4 |
9 |
|
T31 |
2 |
lower_val |
higher_val |
auto[0] |
6954 |
1 |
|
|
T49 |
26 |
|
T50 |
48 |
|
T92 |
3 |
lower_val |
higher_val |
auto[1] |
3386 |
1 |
|
|
T11 |
15 |
|
T4 |
6 |
|
T31 |
2 |
lower_val |
lower_val |
auto[0] |
6854 |
1 |
|
|
T49 |
32 |
|
T50 |
42 |
|
T91 |
1 |
lower_val |
lower_val |
auto[1] |
3397 |
1 |
|
|
T11 |
12 |
|
T4 |
3 |
|
T91 |
15 |
lower_val |
zero_val |
auto[0] |
55 |
1 |
|
|
T2 |
1 |
|
T11 |
1 |
|
T31 |
1 |
lower_val |
zero_val |
auto[1] |
6706 |
1 |
|
|
T2 |
4 |
|
T11 |
18 |
|
T4 |
9 |
zero_val |
higher_val |
auto[0] |
252 |
1 |
|
|
T10 |
1 |
|
T55 |
1 |
|
T62 |
1 |
zero_val |
higher_val |
auto[1] |
63 |
1 |
|
|
T35 |
1 |
|
T67 |
2 |
|
T68 |
5 |
zero_val |
lower_val |
auto[0] |
272 |
1 |
|
|
T1 |
1 |
|
T49 |
1 |
|
T53 |
1 |
zero_val |
lower_val |
auto[1] |
63 |
1 |
|
|
T35 |
3 |
|
T197 |
1 |
|
T198 |
1 |
zero_val |
zero_val |
auto[0] |
165 |
1 |
|
|
T2 |
1 |
|
T11 |
1 |
|
T9 |
1 |
zero_val |
zero_val |
auto[1] |
54 |
1 |
|
|
T35 |
1 |
|
T197 |
1 |
|
T199 |
2 |