Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.28	97.89	92.55	99.89	77.46	95.53	98.89	97.73

Total test records in report: 879

T761	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.1670928345	Aug 29 02:59:24 AM UTC 24	Aug 29 02:59:27 AM UTC 24	91725978 ps
T186	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.562391574	Aug 29 02:59:21 AM UTC 24	Aug 29 02:59:27 AM UTC 24	101359091 ps
T762	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.1220605977	Aug 29 02:59:23 AM UTC 24	Aug 29 02:59:27 AM UTC 24	58426655 ps
T763	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.4154078525	Aug 29 02:59:04 AM UTC 24	Aug 29 02:59:28 AM UTC 24	1274015438 ps
T124	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.4268711805	Aug 29 02:59:24 AM UTC 24	Aug 29 02:59:29 AM UTC 24	46148733 ps
T764	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.2537911733	Aug 29 02:59:27 AM UTC 24	Aug 29 02:59:29 AM UTC 24	17616949 ps
T765	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.3848750321	Aug 29 02:59:28 AM UTC 24	Aug 29 02:59:30 AM UTC 24	24491369 ps
T766	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.1805541300	Aug 29 02:59:28 AM UTC 24	Aug 29 02:59:31 AM UTC 24	41824360 ps
T188	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.1522718895	Aug 29 02:59:25 AM UTC 24	Aug 29 02:59:32 AM UTC 24	225933349 ps
T125	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1275014881	Aug 29 02:59:29 AM UTC 24	Aug 29 02:59:32 AM UTC 24	141088557 ps
T767	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.360657982	Aug 29 02:59:28 AM UTC 24	Aug 29 02:59:32 AM UTC 24	903654769 ps
T768	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.92669021	Aug 29 02:59:25 AM UTC 24	Aug 29 02:59:33 AM UTC 24	166766911 ps
T769	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.509235728	Aug 29 02:59:30 AM UTC 24	Aug 29 02:59:34 AM UTC 24	246778501 ps
T178	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.3479768415	Aug 29 02:59:32 AM UTC 24	Aug 29 02:59:34 AM UTC 24	23297704 ps
T770	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.4147985111	Aug 29 02:59:32 AM UTC 24	Aug 29 02:59:35 AM UTC 24	90654608 ps
T771	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.1915373149	Aug 29 02:59:30 AM UTC 24	Aug 29 02:59:35 AM UTC 24	234355730 ps
T187	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.2032838183	Aug 29 02:59:31 AM UTC 24	Aug 29 02:59:35 AM UTC 24	254223023 ps
T772	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2059560634	Aug 29 02:59:32 AM UTC 24	Aug 29 02:59:36 AM UTC 24	151711591 ps
T773	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3181678131	Aug 29 02:59:33 AM UTC 24	Aug 29 02:59:36 AM UTC 24	153204261 ps
T774	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.3297856656	Aug 29 02:58:56 AM UTC 24	Aug 29 02:59:37 AM UTC 24	7601907894 ps
T775	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.2533017860	Aug 29 02:59:34 AM UTC 24	Aug 29 02:59:37 AM UTC 24	45656374 ps
T776	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.1233135076	Aug 29 02:59:36 AM UTC 24	Aug 29 02:59:38 AM UTC 24	20972577 ps
T777	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.1949018928	Aug 29 02:59:37 AM UTC 24	Aug 29 02:59:39 AM UTC 24	36127117 ps
T778	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.2477882418	Aug 29 02:59:36 AM UTC 24	Aug 29 02:59:40 AM UTC 24	106788097 ps
T779	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.2535067173	Aug 29 02:59:34 AM UTC 24	Aug 29 02:59:40 AM UTC 24	249943023 ps
T780	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1952132443	Aug 29 02:59:37 AM UTC 24	Aug 29 02:59:40 AM UTC 24	75670728 ps
T781	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.557610360	Aug 29 02:59:35 AM UTC 24	Aug 29 02:59:41 AM UTC 24	100964243 ps
T782	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.3003757891	Aug 29 02:59:38 AM UTC 24	Aug 29 02:59:41 AM UTC 24	121419126 ps
T783	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.927078631	Aug 29 02:59:37 AM UTC 24	Aug 29 02:59:42 AM UTC 24	173346881 ps
T784	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.4054395807	Aug 29 02:59:38 AM UTC 24	Aug 29 02:59:42 AM UTC 24	86513478 ps
T177	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.1552120095	Aug 29 02:59:41 AM UTC 24	Aug 29 02:59:43 AM UTC 24	16501805 ps
T785	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.3511407068	Aug 29 02:59:41 AM UTC 24	Aug 29 02:59:43 AM UTC 24	50623827 ps
T786	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.629198260	Aug 29 02:59:39 AM UTC 24	Aug 29 02:59:44 AM UTC 24	102125821 ps
T787	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1578898478	Aug 29 02:59:41 AM UTC 24	Aug 29 02:59:45 AM UTC 24	95235722 ps
T788	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1982304353	Aug 29 02:59:42 AM UTC 24	Aug 29 02:59:46 AM UTC 24	64834417 ps
T789	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1402307310	Aug 29 02:59:41 AM UTC 24	Aug 29 02:59:46 AM UTC 24	117339098 ps
T790	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.353641807	Aug 29 02:59:40 AM UTC 24	Aug 29 02:59:46 AM UTC 24	112731886 ps
T791	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.4145496823	Aug 29 02:59:42 AM UTC 24	Aug 29 02:59:46 AM UTC 24	209862181 ps
T792	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.3432453857	Aug 29 02:59:45 AM UTC 24	Aug 29 02:59:47 AM UTC 24	21918551 ps
T793	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.171372241	Aug 29 02:59:45 AM UTC 24	Aug 29 02:59:48 AM UTC 24	36412970 ps
T794	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.2891156593	Aug 29 02:59:45 AM UTC 24	Aug 29 02:59:49 AM UTC 24	202229923 ps
T795	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1228649097	Aug 29 02:59:47 AM UTC 24	Aug 29 02:59:49 AM UTC 24	317356715 ps
T796	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.1913354766	Aug 29 02:59:42 AM UTC 24	Aug 29 02:59:49 AM UTC 24	946447087 ps
T797	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.1072271743	Aug 29 02:59:47 AM UTC 24	Aug 29 02:59:50 AM UTC 24	78439427 ps
T798	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.3747119271	Aug 29 02:59:47 AM UTC 24	Aug 29 02:59:50 AM UTC 24	78497926 ps
T799	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.1752556126	Aug 29 02:59:47 AM UTC 24	Aug 29 02:59:50 AM UTC 24	135339527 ps
T800	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.4219765137	Aug 29 02:59:49 AM UTC 24	Aug 29 02:59:51 AM UTC 24	17637730 ps
T801	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2925503287	Aug 29 02:59:47 AM UTC 24	Aug 29 02:59:52 AM UTC 24	100956569 ps
T802	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.3386284820	Aug 29 02:59:48 AM UTC 24	Aug 29 02:59:52 AM UTC 24	269070912 ps
T803	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.2808145159	Aug 29 02:59:50 AM UTC 24	Aug 29 02:59:53 AM UTC 24	19564012 ps
T804	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3311089141	Aug 29 02:59:50 AM UTC 24	Aug 29 02:59:54 AM UTC 24	186243075 ps
T805	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.3276260348	Aug 29 02:59:51 AM UTC 24	Aug 29 02:59:54 AM UTC 24	59583303 ps
T806	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.514092603	Aug 29 02:59:50 AM UTC 24	Aug 29 02:59:55 AM UTC 24	46380488 ps
T807	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.4003898950	Aug 29 02:59:53 AM UTC 24	Aug 29 02:59:55 AM UTC 24	50941105 ps
T808	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.2852936868	Aug 29 02:59:54 AM UTC 24	Aug 29 02:59:57 AM UTC 24	30062830 ps
T809	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.3422140611	Aug 29 02:59:51 AM UTC 24	Aug 29 02:59:57 AM UTC 24	403923723 ps
T810	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.3763568995	Aug 29 02:59:55 AM UTC 24	Aug 29 02:59:57 AM UTC 24	62070109 ps
T811	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.1227916641	Aug 29 02:59:54 AM UTC 24	Aug 29 02:59:57 AM UTC 24	153187264 ps
T812	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.4135160942	Aug 29 02:59:51 AM UTC 24	Aug 29 02:59:57 AM UTC 24	547102599 ps
T813	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.500227194	Aug 29 02:59:53 AM UTC 24	Aug 29 02:59:58 AM UTC 24	396338738 ps
T814	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.2608866654	Aug 29 02:59:55 AM UTC 24	Aug 29 03:00:00 AM UTC 24	82223719 ps
T815	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.4144728121	Aug 29 02:59:58 AM UTC 24	Aug 29 03:00:01 AM UTC 24	27479288 ps
T816	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.1739767318	Aug 29 02:59:58 AM UTC 24	Aug 29 03:00:01 AM UTC 24	18292812 ps
T817	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.335325235	Aug 29 02:59:56 AM UTC 24	Aug 29 03:00:01 AM UTC 24	332044489 ps
T818	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.2395358949	Aug 29 02:59:56 AM UTC 24	Aug 29 03:00:02 AM UTC 24	118838632 ps
T819	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.2274003464	Aug 29 02:59:57 AM UTC 24	Aug 29 03:00:02 AM UTC 24	105750483 ps
T820	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.4173435155	Aug 29 02:59:58 AM UTC 24	Aug 29 03:00:02 AM UTC 24	44383415 ps
T821	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2185971266	Aug 29 02:59:58 AM UTC 24	Aug 29 03:00:04 AM UTC 24	98422333 ps
T822	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1232027761	Aug 29 03:00:00 AM UTC 24	Aug 29 03:00:06 AM UTC 24	24061084 ps
T823	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.1735346584	Aug 29 03:00:01 AM UTC 24	Aug 29 03:00:07 AM UTC 24	14885295 ps
T824	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.2144921307	Aug 29 03:00:00 AM UTC 24	Aug 29 03:00:07 AM UTC 24	80106192 ps
T825	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.3459531259	Aug 29 03:00:05 AM UTC 24	Aug 29 03:00:08 AM UTC 24	18138713 ps
T826	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.18353901	Aug 29 03:00:05 AM UTC 24	Aug 29 03:00:08 AM UTC 24	90988075 ps
T827	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.4004168569	Aug 29 03:00:05 AM UTC 24	Aug 29 03:00:08 AM UTC 24	26290027 ps
T828	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.3580963457	Aug 29 03:00:00 AM UTC 24	Aug 29 03:00:09 AM UTC 24	1248794143 ps
T829	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.2866549096	Aug 29 03:00:05 AM UTC 24	Aug 29 03:00:09 AM UTC 24	165327686 ps
T830	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.2339186913	Aug 29 03:00:01 AM UTC 24	Aug 29 03:00:10 AM UTC 24	98617041 ps
T831	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.2083131792	Aug 29 03:00:08 AM UTC 24	Aug 29 03:00:10 AM UTC 24	40857527 ps
T832	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1058996707	Aug 29 03:00:09 AM UTC 24	Aug 29 03:00:12 AM UTC 24	88455313 ps
T833	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2105729927	Aug 29 03:00:05 AM UTC 24	Aug 29 03:00:10 AM UTC 24	35420251 ps
T834	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.2349343033	Aug 29 03:00:05 AM UTC 24	Aug 29 03:00:11 AM UTC 24	533183398 ps
T835	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2323260510	Aug 29 03:00:09 AM UTC 24	Aug 29 03:00:12 AM UTC 24	115788236 ps
T836	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1943935130	Aug 29 03:00:09 AM UTC 24	Aug 29 03:00:12 AM UTC 24	132249169 ps
T191	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.3363795066	Aug 29 03:00:08 AM UTC 24	Aug 29 03:00:13 AM UTC 24	275331212 ps
T837	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.1694138143	Aug 29 03:00:11 AM UTC 24	Aug 29 03:00:14 AM UTC 24	51096130 ps
T838	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.1511274044	Aug 29 03:00:11 AM UTC 24	Aug 29 03:00:14 AM UTC 24	51353873 ps
T839	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.599257501	Aug 29 03:00:10 AM UTC 24	Aug 29 03:00:14 AM UTC 24	36525231 ps
T840	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.1783827238	Aug 29 03:00:11 AM UTC 24	Aug 29 03:00:15 AM UTC 24	97156003 ps
T841	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.2224348599	Aug 29 03:00:12 AM UTC 24	Aug 29 03:00:15 AM UTC 24	104954720 ps
T842	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2390735714	Aug 29 03:00:12 AM UTC 24	Aug 29 03:00:15 AM UTC 24	23536273 ps
T843	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2085757551	Aug 29 03:00:12 AM UTC 24	Aug 29 03:00:16 AM UTC 24	91199923 ps
T844	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.1933912834	Aug 29 03:00:10 AM UTC 24	Aug 29 03:00:16 AM UTC 24	254021647 ps
T845	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.773950084	Aug 29 03:00:15 AM UTC 24	Aug 29 03:00:17 AM UTC 24	36854608 ps
T846	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.1577389041	Aug 29 03:00:13 AM UTC 24	Aug 29 03:00:17 AM UTC 24	178337180 ps
T847	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.4004566987	Aug 29 03:00:15 AM UTC 24	Aug 29 03:00:17 AM UTC 24	18904184 ps
T848	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.2653170944	Aug 29 03:00:15 AM UTC 24	Aug 29 03:00:18 AM UTC 24	52619543 ps
T849	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.956884622	Aug 29 03:00:16 AM UTC 24	Aug 29 03:00:18 AM UTC 24	16082512 ps
T192	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.3161619040	Aug 29 03:00:11 AM UTC 24	Aug 29 03:00:19 AM UTC 24	596215700 ps
T850	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.3264486017	Aug 29 03:00:16 AM UTC 24	Aug 29 03:00:19 AM UTC 24	16448446 ps
T851	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2786705575	Aug 29 03:00:16 AM UTC 24	Aug 29 03:00:19 AM UTC 24	48762424 ps
T852	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.2666925063	Aug 29 03:00:17 AM UTC 24	Aug 29 03:00:20 AM UTC 24	20962919 ps
T853	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.1151427591	Aug 29 03:00:17 AM UTC 24	Aug 29 03:00:20 AM UTC 24	40645858 ps
T193	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.2463383248	Aug 29 03:00:14 AM UTC 24	Aug 29 03:00:20 AM UTC 24	100243442 ps
T854	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.55402587	Aug 29 03:00:18 AM UTC 24	Aug 29 03:00:20 AM UTC 24	30795798 ps
T855	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.2519967410	Aug 29 03:00:19 AM UTC 24	Aug 29 03:00:21 AM UTC 24	17919982 ps
T856	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.121375950	Aug 29 03:00:19 AM UTC 24	Aug 29 03:00:21 AM UTC 24	104076720 ps
T857	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.4159894025	Aug 29 03:00:19 AM UTC 24	Aug 29 03:00:21 AM UTC 24	16588649 ps
T858	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.2740670846	Aug 29 03:00:19 AM UTC 24	Aug 29 03:00:22 AM UTC 24	19204187 ps
T859	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.376678957	Aug 29 03:00:19 AM UTC 24	Aug 29 03:00:22 AM UTC 24	19702566 ps
T860	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.2026462067	Aug 29 03:00:21 AM UTC 24	Aug 29 03:00:23 AM UTC 24	17964169 ps
T861	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.2928999522	Aug 29 03:00:21 AM UTC 24	Aug 29 03:00:23 AM UTC 24	14019572 ps
T862	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.2917391287	Aug 29 03:00:21 AM UTC 24	Aug 29 03:00:23 AM UTC 24	37752240 ps
T863	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.2814509115	Aug 29 03:00:21 AM UTC 24	Aug 29 03:00:23 AM UTC 24	19305041 ps
T864	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.2989346007	Aug 29 03:00:22 AM UTC 24	Aug 29 03:00:24 AM UTC 24	20388039 ps
T865	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.3952195095	Aug 29 03:00:22 AM UTC 24	Aug 29 03:00:24 AM UTC 24	116892946 ps
T866	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.193157675	Aug 29 03:00:22 AM UTC 24	Aug 29 03:00:24 AM UTC 24	37468971 ps
T867	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.3043892197	Aug 29 03:00:22 AM UTC 24	Aug 29 03:00:24 AM UTC 24	49448771 ps
T868	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.1744774773	Aug 29 03:00:23 AM UTC 24	Aug 29 03:00:25 AM UTC 24	42495042 ps
T869	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.2727105265	Aug 29 03:00:23 AM UTC 24	Aug 29 03:00:25 AM UTC 24	105310725 ps
T870	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.2601860061	Aug 29 03:00:23 AM UTC 24	Aug 29 03:00:25 AM UTC 24	20254168 ps
T871	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.3896142034	Aug 29 03:00:24 AM UTC 24	Aug 29 03:00:26 AM UTC 24	26165763 ps
T872	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.2438526947	Aug 29 03:00:24 AM UTC 24	Aug 29 03:00:26 AM UTC 24	20656609 ps
T873	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.1483010578	Aug 29 03:00:24 AM UTC 24	Aug 29 03:00:26 AM UTC 24	40857243 ps
T874	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.2531193041	Aug 29 03:00:24 AM UTC 24	Aug 29 03:00:27 AM UTC 24	15606222 ps
T875	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.2886914490	Aug 29 03:00:24 AM UTC 24	Aug 29 03:00:27 AM UTC 24	17140840 ps
T876	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.1918155028	Aug 29 03:00:26 AM UTC 24	Aug 29 03:00:28 AM UTC 24	52155895 ps
T877	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.4130444806	Aug 29 03:00:26 AM UTC 24	Aug 29 03:00:28 AM UTC 24	36032908 ps
T878	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.2465828041	Aug 29 03:00:26 AM UTC 24	Aug 29 03:00:28 AM UTC 24	13391687 ps
T879	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.1674930342	Aug 29 03:00:26 AM UTC 24	Aug 29 03:00:28 AM UTC 24	68007754 ps

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/0.kmac_smoke.2886026046
Short name	T11
Test name
Test status
Simulation time	1654817620 ps
CPU time	26.32 seconds
Started	Aug 29 06:18:15 AM UTC 24
Finished	Aug 29 06:18:43 AM UTC 24
Peak memory	234932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886026046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.2886026046 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/2.kmac_lc_escalation.1141941651
Short name	T12
Test name
Test status
Simulation time	7078141910 ps
CPU time	27.37 seconds
Started	Aug 29 06:18:51 AM UTC 24
Finished	Aug 29 06:19:19 AM UTC 24
Peak memory	256396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141941651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.1141941651 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_refresh.3260073465
Short name	T15
Test name
Test status
Simulation time	4188156519 ps
CPU time	161.3 seconds
Started	Aug 29 06:18:19 AM UTC 24
Finished	Aug 29 06:21:03 AM UTC 24
Peak memory	291060 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260073465 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.3260073465 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_intg_err.4003377254
Short name	T136
Test name
Test status
Simulation time	105136104 ps
CPU time	5.93 seconds
Started	Aug 29 02:58:30 AM UTC 24
Finished	Aug 29 02:58:37 AM UTC 24
Peak memory	225704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003377254 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.4003377254 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/3.kmac_stress_all_with_rand_reset.3054029896
Short name	T35
Test name
Test status
Simulation time	13887376862 ps
CPU time	201.32 seconds
Started	Aug 29 06:19:14 AM UTC 24
Finished	Aug 29 06:22:40 AM UTC 24
Peak memory	295628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3054029896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all_with_r and_reset.3054029896 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/0.kmac_key_error.3077798326
Short name	T3
Test name
Test status
Simulation time	501161434 ps
CPU time	3.08 seconds
Started	Aug 29 06:18:34 AM UTC 24
Finished	Aug 29 06:18:38 AM UTC 24
Peak memory	227496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077798326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.3077798326 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/1.kmac_sec_cm.1152554558
Short name	T43
Test name
Test status
Simulation time	3879756768 ps
CPU time	51.53 seconds
Started	Aug 29 06:18:45 AM UTC 24
Finished	Aug 29 06:19:39 AM UTC 24
Peak memory	286236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152554558 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.1152554558 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_ready_error.3909320003
Short name	T4
Test name
Test status
Simulation time	4241269077 ps
CPU time	14.7 seconds
Started	Aug 29 06:18:42 AM UTC 24
Finished	Aug 29 06:18:58 AM UTC 24
Peak memory	231880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909320003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.3909320003 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_entropy_ready_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/5.kmac_lc_escalation.3499332171
Short name	T46
Test name
Test status
Simulation time	169636995 ps
CPU time	2.36 seconds
Started	Aug 29 06:21:16 AM UTC 24
Finished	Aug 29 06:21:19 AM UTC 24
Peak memory	233872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499332171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.3499332171 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/5.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/1.kmac_error.2835529040
Short name	T18
Test name
Test status
Simulation time	11807137991 ps
CPU time	201.18 seconds
Started	Aug 29 06:18:45 AM UTC 24
Finished	Aug 29 06:22:10 AM UTC 24
Peak memory	379260 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835529040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.2835529040 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.3824324795
Short name	T118
Test name
Test status
Simulation time	356837153 ps
CPU time	3.85 seconds
Started	Aug 29 02:58:24 AM UTC 24
Finished	Aug 29 02:58:29 AM UTC 24
Peak memory	229948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824324795 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors_with_csr_rw.3824 324795 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/13.kmac_lc_escalation.1696195189
Short name	T74
Test name
Test status
Simulation time	35336274 ps
CPU time	2.72 seconds
Started	Aug 29 06:29:31 AM UTC 24
Finished	Aug 29 06:29:35 AM UTC 24
Peak memory	233808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696195189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.1696195189 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/13.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_intr_test.2122441600
Short name	T175
Test name
Test status
Simulation time	48934117 ps
CPU time	1.15 seconds
Started	Aug 29 02:59:03 AM UTC 24
Finished	Aug 29 02:59:05 AM UTC 24
Peak memory	224500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122441600 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.2122441600 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/4.kmac_edn_timeout_error.4080048653
Short name	T99
Test name
Test status
Simulation time	28598878 ps
CPU time	1.52 seconds
Started	Aug 29 06:20:07 AM UTC 24
Finished	Aug 29 06:20:10 AM UTC 24
Peak memory	225088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080048653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.4080048653 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/3.kmac_lc_escalation.2689633780
Short name	T17
Test name
Test status
Simulation time	124513272 ps
CPU time	1.83 seconds
Started	Aug 29 06:19:10 AM UTC 24
Finished	Aug 29 06:19:13 AM UTC 24
Peak memory	231040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689633780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.2689633780 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.2082792318
Short name	T116
Test name
Test status
Simulation time	155442556 ps
CPU time	2.99 seconds
Started	Aug 29 02:58:05 AM UTC 24
Finished	Aug 29 02:58:09 AM UTC 24
Peak memory	229924 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082792318 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors_with_csr_rw.2082 792318 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/28.kmac_lc_escalation.1178931241
Short name	T65
Test name
Test status
Simulation time	1660967538 ps
CPU time	33.82 seconds
Started	Aug 29 06:53:04 AM UTC 24
Finished	Aug 29 06:53:39 AM UTC 24
Peak memory	262352 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178931241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.1178931241 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/28.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_mode_error.900885588
Short name	T51
Test name
Test status
Simulation time	33451665 ps
CPU time	0.81 seconds
Started	Aug 29 06:18:42 AM UTC 24
Finished	Aug 29 06:18:44 AM UTC 24
Peak memory	227440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900885588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.900885588 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/1.kmac_sideload.729793281
Short name	T23
Test name
Test status
Simulation time	3796568177 ps
CPU time	63.74 seconds
Started	Aug 29 06:18:44 AM UTC 24
Finished	Aug 29 06:19:49 AM UTC 24
Peak memory	258292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729793281 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.729793281 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/16.kmac_lc_escalation.129600225
Short name	T42
Test name
Test status
Simulation time	47561106 ps
CPU time	2.23 seconds
Started	Aug 29 06:33:02 AM UTC 24
Finished	Aug 29 06:33:05 AM UTC 24
Peak memory	231796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129600225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.129600225 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/16.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/15.kmac_entropy_refresh.314429259
Short name	T101
Test name
Test status
Simulation time	3723948867 ps
CPU time	120.83 seconds
Started	Aug 29 06:30:24 AM UTC 24
Finished	Aug 29 06:32:27 AM UTC 24
Peak memory	268672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314429259 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.314429259 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/15.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_partial_access.4285018817
Short name	T154
Test name
Test status
Simulation time	44012339 ps
CPU time	1.79 seconds
Started	Aug 29 02:58:08 AM UTC 24
Finished	Aug 29 02:58:11 AM UTC 24
Peak memory	224568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285018817 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial_access.4285018817 +enable_masking =1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/4.kmac_stress_all.3032714005
Short name	T161
Test name
Test status
Simulation time	59089066376 ps
CPU time	722.8 seconds
Started	Aug 29 06:20:17 AM UTC 24
Finished	Aug 29 06:32:31 AM UTC 24
Peak memory	400008 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032714005 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.3032714005 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/18.kmac_lc_escalation.4170114493
Short name	T109
Test name
Test status
Simulation time	54313659 ps
CPU time	2.06 seconds
Started	Aug 29 06:35:51 AM UTC 24
Finished	Aug 29 06:35:54 AM UTC 24
Peak memory	233780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170114493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.4170114493 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/18.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/24.kmac_lc_escalation.1191779316
Short name	T71
Test name
Test status
Simulation time	31471810 ps
CPU time	2.03 seconds
Started	Aug 29 06:46:16 AM UTC 24
Finished	Aug 29 06:46:19 AM UTC 24
Peak memory	231736 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191779316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.1191779316 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/24.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/34.kmac_lc_escalation.3615547098
Short name	T112
Test name
Test status
Simulation time	88552520 ps
CPU time	2.01 seconds
Started	Aug 29 06:59:04 AM UTC 24
Finished	Aug 29 06:59:07 AM UTC 24
Peak memory	233348 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615547098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.3615547098 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/34.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/0.kmac_alert_test.814213052
Short name	T52
Test name
Test status
Simulation time	19136578 ps
CPU time	0.84 seconds
Started	Aug 29 06:18:44 AM UTC 24
Finished	Aug 29 06:18:46 AM UTC 24
Peak memory	226296 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814213052 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.814213052 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_256.3791103526
Short name	T50
Test name
Test status
Simulation time	8128905739 ps
CPU time	41.6 seconds
Started	Aug 29 06:18:15 AM UTC 24
Finished	Aug 29 06:18:58 AM UTC 24
Peak memory	257012 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791103526 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.3791103526 +enab le_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_256/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors.262655873
Short name	T195
Test name
Test status
Simulation time	797084125 ps
CPU time	2.48 seconds
Started	Aug 29 02:59:18 AM UTC 24
Finished	Aug 29 02:59:21 AM UTC 24
Peak memory	225912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262655873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors.262655873 +enable_masking=1 + sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.1552120095
Short name	T177
Test name
Test status
Simulation time	16501805 ps
CPU time	1.18 seconds
Started	Aug 29 02:59:41 AM UTC 24
Finished	Aug 29 02:59:43 AM UTC 24
Peak memory	224496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552120095 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.1552120095 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/11.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/5.kmac_mubi.3948915883
Short name	T82
Test name
Test status
Simulation time	31516558690 ps
CPU time	366.24 seconds
Started	Aug 29 06:21:01 AM UTC 24
Finished	Aug 29 06:27:12 AM UTC 24
Peak memory	522912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948915883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.3948915883 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/5.kmac_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_intg_err.860570460
Short name	T183
Test name
Test status
Simulation time	368550639 ps
CPU time	5.34 seconds
Started	Aug 29 02:58:54 AM UTC 24
Finished	Aug 29 02:59:00 AM UTC 24
Peak memory	225572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860570460 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.860570460 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_128.1328062137
Short name	T204
Test name
Test status
Simulation time	14257527066 ps
CPU time	293.64 seconds
Started	Aug 29 06:18:44 AM UTC 24
Finished	Aug 29 06:23:42 AM UTC 24
Peak memory	284928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328062137 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.1328062137 +e nable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_128/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/5.kmac_error.3723219072
Short name	T20
Test name
Test status
Simulation time	5119003914 ps
CPU time	355.93 seconds
Started	Aug 29 06:21:04 AM UTC 24
Finished	Aug 29 06:27:05 AM UTC 24
Peak memory	377208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723219072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.3723219072 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/5.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.2463383248
Short name	T193
Test name
Test status
Simulation time	100243442 ps
CPU time	5.66 seconds
Started	Aug 29 03:00:14 AM UTC 24
Finished	Aug 29 03:00:20 AM UTC 24
Peak memory	225488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463383248 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.2463383248 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/19.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_ready_error.234905645
Short name	T6
Test name
Test status
Simulation time	4810945819 ps
CPU time	45.36 seconds
Started	Aug 29 06:18:51 AM UTC 24
Finished	Aug 29 06:19:38 AM UTC 24
Peak memory	233996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234905645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_mas ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.234905645 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_entropy_ready_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.2035411410
Short name	T185
Test name
Test status
Simulation time	182841234 ps
CPU time	4.78 seconds
Started	Aug 29 02:59:14 AM UTC 24
Finished	Aug 29 02:59:20 AM UTC 24
Peak memory	225568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035411410 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.2035411410 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/6.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/10.kmac_stress_all.3338777861
Short name	T545
Test name
Test status
Simulation time	61529776975 ps
CPU time	2387.27 seconds
Started	Aug 29 06:26:15 AM UTC 24
Finished	Aug 29 07:06:29 AM UTC 24
Peak memory	1507636 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338777861 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.3338777861 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/10.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/35.kmac_stress_all.1791816841
Short name	T105
Test name
Test status
Simulation time	38905733652 ps
CPU time	1447.92 seconds
Started	Aug 29 07:00:20 AM UTC 24
Finished	Aug 29 07:24:46 AM UTC 24
Peak memory	393912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791816841 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.1791816841 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/35.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/0.kmac_lc_escalation.1732555228
Short name	T9
Test name
Test status
Simulation time	69742577 ps
CPU time	1.18 seconds
Started	Aug 29 06:18:42 AM UTC 24
Finished	Aug 29 06:18:45 AM UTC 24
Peak memory	231304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732555228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.1732555228 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_aliasing.1317853683
Short name	T166
Test name
Test status
Simulation time	268155972 ps
CPU time	8.04 seconds
Started	Aug 29 02:58:18 AM UTC 24
Finished	Aug 29 02:58:27 AM UTC 24
Peak memory	225496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317853683 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.1317853683 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_bit_bash.2684720194
Short name	T722
Test name
Test status
Simulation time	154295047 ps
CPU time	9.85 seconds
Started	Aug 29 02:58:18 AM UTC 24
Finished	Aug 29 02:58:29 AM UTC 24
Peak memory	225476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684720194 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.2684720194 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_hw_reset.1868392529
Short name	T139
Test name
Test status
Simulation time	100541552 ps
CPU time	1.8 seconds
Started	Aug 29 02:58:14 AM UTC 24
Finished	Aug 29 02:58:17 AM UTC 24
Peak memory	224452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868392529 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.1868392529 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.798426735
Short name	T142
Test name
Test status
Simulation time	818134521 ps
CPU time	2.58 seconds
Started	Aug 29 02:58:20 AM UTC 24
Finished	Aug 29 02:58:23 AM UTC 24
Peak memory	231692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=798426735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_r w_with_rand_reset.798426735 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_rw.484524367
Short name	T164
Test name
Test status
Simulation time	53906011 ps
CPU time	1.6 seconds
Started	Aug 29 02:58:17 AM UTC 24
Finished	Aug 29 02:58:19 AM UTC 24
Peak memory	224496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484524367 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.484524367 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_intr_test.3274297460
Short name	T138
Test name
Test status
Simulation time	14594677 ps
CPU time	1.29 seconds
Started	Aug 29 02:58:14 AM UTC 24
Finished	Aug 29 02:58:17 AM UTC 24
Peak memory	224224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274297460 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.3274297460 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_walk.3891265287
Short name	T721
Test name
Test status
Simulation time	14398933 ps
CPU time	1.24 seconds
Started	Aug 29 02:58:05 AM UTC 24
Finished	Aug 29 02:58:07 AM UTC 24
Peak memory	223592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891265287 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.3891265287 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_same_csr_outstanding.1349279020
Short name	T165
Test name
Test status
Simulation time	59461385 ps
CPU time	2.46 seconds
Started	Aug 29 02:58:19 AM UTC 24
Finished	Aug 29 02:58:22 AM UTC 24
Peak memory	225656 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349279020 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_outstanding.1349279020 +enable_mas king=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors.2889652796
Short name	T115
Test name
Test status
Simulation time	31286196 ps
CPU time	1.99 seconds
Started	Aug 29 02:58:00 AM UTC 24
Finished	Aug 29 02:58:03 AM UTC 24
Peak memory	227440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889652796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors.2889652796 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_errors.2427256785
Short name	T141
Test name
Test status
Simulation time	47626517 ps
CPU time	2.46 seconds
Started	Aug 29 02:58:10 AM UTC 24
Finished	Aug 29 02:58:13 AM UTC 24
Peak memory	225760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427256785 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.2427256785 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_intg_err.158069754
Short name	T135
Test name
Test status
Simulation time	182304791 ps
CPU time	3.36 seconds
Started	Aug 29 02:58:12 AM UTC 24
Finished	Aug 29 02:58:17 AM UTC 24
Peak memory	225536 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158069754 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.158069754 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_aliasing.2508728606
Short name	T727
Test name
Test status
Simulation time	589303859 ps
CPU time	6.76 seconds
Started	Aug 29 02:58:35 AM UTC 24
Finished	Aug 29 02:58:42 AM UTC 24
Peak memory	225628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508728606 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.2508728606 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_bit_bash.2190741613
Short name	T169
Test name
Test status
Simulation time	1374095677 ps
CPU time	17.37 seconds
Started	Aug 29 02:58:35 AM UTC 24
Finished	Aug 29 02:58:53 AM UTC 24
Peak memory	225692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190741613 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.2190741613 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_hw_reset.3558001205
Short name	T724
Test name
Test status
Simulation time	15295210 ps
CPU time	1.48 seconds
Started	Aug 29 02:58:31 AM UTC 24
Finished	Aug 29 02:58:34 AM UTC 24
Peak memory	224452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558001205 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.3558001205 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.609130765
Short name	T144
Test name
Test status
Simulation time	461869059 ps
CPU time	2.4 seconds
Started	Aug 29 02:58:39 AM UTC 24
Finished	Aug 29 02:58:42 AM UTC 24
Peak memory	229644 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=609130765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_mem_r w_with_rand_reset.609130765 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_rw.1730674950
Short name	T725
Test name
Test status
Simulation time	114030353 ps
CPU time	1.64 seconds
Started	Aug 29 02:58:34 AM UTC 24
Finished	Aug 29 02:58:36 AM UTC 24
Peak memory	224492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730674950 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.1730674950 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_intr_test.3415593687
Short name	T140
Test name
Test status
Simulation time	47948170 ps
CPU time	1.2 seconds
Started	Aug 29 02:58:30 AM UTC 24
Finished	Aug 29 02:58:33 AM UTC 24
Peak memory	224500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415593687 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.3415593687 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_partial_access.3180758511
Short name	T155
Test name
Test status
Simulation time	54229230 ps
CPU time	1.58 seconds
Started	Aug 29 02:58:28 AM UTC 24
Finished	Aug 29 02:58:31 AM UTC 24
Peak memory	224568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180758511 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial_access.3180758511 +enable_masking =1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_walk.1718899656
Short name	T723
Test name
Test status
Simulation time	13211235 ps
CPU time	1.23 seconds
Started	Aug 29 02:58:27 AM UTC 24
Finished	Aug 29 02:58:29 AM UTC 24
Peak memory	224620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718899656 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.1718899656 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_same_csr_outstanding.3967329294
Short name	T726
Test name
Test status
Simulation time	49997949 ps
CPU time	2.58 seconds
Started	Aug 29 02:58:37 AM UTC 24
Finished	Aug 29 02:58:40 AM UTC 24
Peak memory	225484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967329294 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_outstanding.3967329294 +enable_mas king=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors.2388038450
Short name	T117
Test name
Test status
Simulation time	133897748 ps
CPU time	2.18 seconds
Started	Aug 29 02:58:23 AM UTC 24
Finished	Aug 29 02:58:26 AM UTC 24
Peak memory	225916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388038450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors.2388038450 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_errors.3392667139
Short name	T143
Test name
Test status
Simulation time	68720281 ps
CPU time	3.35 seconds
Started	Aug 29 02:58:29 AM UTC 24
Finished	Aug 29 02:58:34 AM UTC 24
Peak memory	225604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392667139 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.3392667139 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.927078631
Short name	T783
Test name
Test status
Simulation time	173346881 ps
CPU time	3.99 seconds
Started	Aug 29 02:59:37 AM UTC 24
Finished	Aug 29 02:59:42 AM UTC 24
Peak memory	231768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=927078631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_mem_ rw_with_rand_reset.927078631 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.1949018928
Short name	T777
Test name
Test status
Simulation time	36127117 ps
CPU time	1.58 seconds
Started	Aug 29 02:59:37 AM UTC 24
Finished	Aug 29 02:59:39 AM UTC 24
Peak memory	224504 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949018928 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.1949018928 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/10.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.1233135076
Short name	T776
Test name
Test status
Simulation time	20972577 ps
CPU time	1.05 seconds
Started	Aug 29 02:59:36 AM UTC 24
Finished	Aug 29 02:59:38 AM UTC 24
Peak memory	224224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233135076 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.1233135076 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/10.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1952132443
Short name	T780
Test name
Test status
Simulation time	75670728 ps
CPU time	2.43 seconds
Started	Aug 29 02:59:37 AM UTC 24
Finished	Aug 29 02:59:40 AM UTC 24
Peak memory	225484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952132443 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr_outstanding.1952132443 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/10.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.2533017860
Short name	T775
Test name
Test status
Simulation time	45656374 ps
CPU time	1.71 seconds
Started	Aug 29 02:59:34 AM UTC 24
Finished	Aug 29 02:59:37 AM UTC 24
Peak memory	224288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533017860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors.2533017860 +enable_masking= 1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.2535067173
Short name	T779
Test name
Test status
Simulation time	249943023 ps
CPU time	4.47 seconds
Started	Aug 29 02:59:34 AM UTC 24
Finished	Aug 29 02:59:40 AM UTC 24
Peak memory	230076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535067173 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors_with_csr_rw.253 5067173 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.557610360
Short name	T781
Test name
Test status
Simulation time	100964243 ps
CPU time	4.24 seconds
Started	Aug 29 02:59:35 AM UTC 24
Finished	Aug 29 02:59:41 AM UTC 24
Peak memory	225624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557610360 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.557610360 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/10.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.2477882418
Short name	T778
Test name
Test status
Simulation time	106788097 ps
CPU time	3.24 seconds
Started	Aug 29 02:59:36 AM UTC 24
Finished	Aug 29 02:59:40 AM UTC 24
Peak memory	225480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477882418 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.2477882418 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/10.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1578898478
Short name	T787
Test name
Test status
Simulation time	95235722 ps
CPU time	3.16 seconds
Started	Aug 29 02:59:41 AM UTC 24
Finished	Aug 29 02:59:45 AM UTC 24
Peak memory	231704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1578898478 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_mem _rw_with_rand_reset.1578898478 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.3511407068
Short name	T785
Test name
Test status
Simulation time	50623827 ps
CPU time	1.23 seconds
Started	Aug 29 02:59:41 AM UTC 24
Finished	Aug 29 02:59:43 AM UTC 24
Peak memory	224500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511407068 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.3511407068 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/11.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1402307310
Short name	T789
Test name
Test status
Simulation time	117339098 ps
CPU time	3.4 seconds
Started	Aug 29 02:59:41 AM UTC 24
Finished	Aug 29 02:59:46 AM UTC 24
Peak memory	225528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402307310 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr_outstanding.1402307310 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/11.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.3003757891
Short name	T782
Test name
Test status
Simulation time	121419126 ps
CPU time	2.15 seconds
Started	Aug 29 02:59:38 AM UTC 24
Finished	Aug 29 02:59:41 AM UTC 24
Peak memory	227872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003757891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors.3003757891 +enable_masking= 1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.4054395807
Short name	T784
Test name
Test status
Simulation time	86513478 ps
CPU time	2.48 seconds
Started	Aug 29 02:59:38 AM UTC 24
Finished	Aug 29 02:59:42 AM UTC 24
Peak memory	225548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054395807 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors_with_csr_rw.405 4395807 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.629198260
Short name	T786
Test name
Test status
Simulation time	102125821 ps
CPU time	3.55 seconds
Started	Aug 29 02:59:39 AM UTC 24
Finished	Aug 29 02:59:44 AM UTC 24
Peak memory	225624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629198260 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.629198260 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/11.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.353641807
Short name	T790
Test name
Test status
Simulation time	112731886 ps
CPU time	4.6 seconds
Started	Aug 29 02:59:40 AM UTC 24
Finished	Aug 29 02:59:46 AM UTC 24
Peak memory	225552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353641807 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.353641807 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/11.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.3747119271
Short name	T798
Test name
Test status
Simulation time	78497926 ps
CPU time	2.25 seconds
Started	Aug 29 02:59:47 AM UTC 24
Finished	Aug 29 02:59:50 AM UTC 24
Peak memory	231696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3747119271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_mem _rw_with_rand_reset.3747119271 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.171372241
Short name	T793
Test name
Test status
Simulation time	36412970 ps
CPU time	1.84 seconds
Started	Aug 29 02:59:45 AM UTC 24
Finished	Aug 29 02:59:48 AM UTC 24
Peak memory	224556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171372241 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.171372241 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/12.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.3432453857
Short name	T792
Test name
Test status
Simulation time	21918551 ps
CPU time	1.26 seconds
Started	Aug 29 02:59:45 AM UTC 24
Finished	Aug 29 02:59:47 AM UTC 24
Peak memory	224880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432453857 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.3432453857 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/12.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.1072271743
Short name	T797
Test name
Test status
Simulation time	78439427 ps
CPU time	2.12 seconds
Started	Aug 29 02:59:47 AM UTC 24
Finished	Aug 29 02:59:50 AM UTC 24
Peak memory	224388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072271743 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr_outstanding.1072271743 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/12.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1982304353
Short name	T788
Test name
Test status
Simulation time	64834417 ps
CPU time	1.58 seconds
Started	Aug 29 02:59:42 AM UTC 24
Finished	Aug 29 02:59:46 AM UTC 24
Peak memory	224448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982304353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors.1982304353 +enable_masking= 1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.4145496823
Short name	T791
Test name
Test status
Simulation time	209862181 ps
CPU time	2.34 seconds
Started	Aug 29 02:59:42 AM UTC 24
Finished	Aug 29 02:59:46 AM UTC 24
Peak memory	225600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145496823 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors_with_csr_rw.414 5496823 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.1913354766
Short name	T796
Test name
Test status
Simulation time	946447087 ps
CPU time	5.32 seconds
Started	Aug 29 02:59:42 AM UTC 24
Finished	Aug 29 02:59:49 AM UTC 24
Peak memory	225616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913354766 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.1913354766 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/12.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.2891156593
Short name	T794
Test name
Test status
Simulation time	202229923 ps
CPU time	3.29 seconds
Started	Aug 29 02:59:45 AM UTC 24
Finished	Aug 29 02:59:49 AM UTC 24
Peak memory	225548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891156593 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.2891156593 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/12.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3311089141
Short name	T804
Test name
Test status
Simulation time	186243075 ps
CPU time	2.79 seconds
Started	Aug 29 02:59:50 AM UTC 24
Finished	Aug 29 02:59:54 AM UTC 24
Peak memory	227672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3311089141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_mem _rw_with_rand_reset.3311089141 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.2808145159
Short name	T803
Test name
Test status
Simulation time	19564012 ps
CPU time	1.75 seconds
Started	Aug 29 02:59:50 AM UTC 24
Finished	Aug 29 02:59:53 AM UTC 24
Peak memory	224500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808145159 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.2808145159 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/13.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.4219765137
Short name	T800
Test name
Test status
Simulation time	17637730 ps
CPU time	1.14 seconds
Started	Aug 29 02:59:49 AM UTC 24
Finished	Aug 29 02:59:51 AM UTC 24
Peak memory	224448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219765137 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.4219765137 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/13.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.514092603
Short name	T806
Test name
Test status
Simulation time	46380488 ps
CPU time	3.31 seconds
Started	Aug 29 02:59:50 AM UTC 24
Finished	Aug 29 02:59:55 AM UTC 24
Peak memory	225548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514092603 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr_outstanding.514092603 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/13.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1228649097
Short name	T795
Test name
Test status
Simulation time	317356715 ps
CPU time	1.58 seconds
Started	Aug 29 02:59:47 AM UTC 24
Finished	Aug 29 02:59:49 AM UTC 24
Peak memory	226496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228649097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors.1228649097 +enable_masking= 1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2925503287
Short name	T801
Test name
Test status
Simulation time	100956569 ps
CPU time	3.94 seconds
Started	Aug 29 02:59:47 AM UTC 24
Finished	Aug 29 02:59:52 AM UTC 24
Peak memory	225580 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925503287 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors_with_csr_rw.292 5503287 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.1752556126
Short name	T799
Test name
Test status
Simulation time	135339527 ps
CPU time	2.36 seconds
Started	Aug 29 02:59:47 AM UTC 24
Finished	Aug 29 02:59:50 AM UTC 24
Peak memory	225616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752556126 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.1752556126 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/13.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.3386284820
Short name	T802
Test name
Test status
Simulation time	269070912 ps
CPU time	3.09 seconds
Started	Aug 29 02:59:48 AM UTC 24
Finished	Aug 29 02:59:52 AM UTC 24
Peak memory	225544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386284820 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.3386284820 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/13.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.2608866654
Short name	T814
Test name
Test status
Simulation time	82223719 ps
CPU time	3.9 seconds
Started	Aug 29 02:59:55 AM UTC 24
Finished	Aug 29 03:00:00 AM UTC 24
Peak memory	231700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2608866654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_mem _rw_with_rand_reset.2608866654 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.2852936868
Short name	T808
Test name
Test status
Simulation time	30062830 ps
CPU time	1.85 seconds
Started	Aug 29 02:59:54 AM UTC 24
Finished	Aug 29 02:59:57 AM UTC 24
Peak memory	224500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852936868 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.2852936868 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/14.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.4003898950
Short name	T807
Test name
Test status
Simulation time	50941105 ps
CPU time	1.02 seconds
Started	Aug 29 02:59:53 AM UTC 24
Finished	Aug 29 02:59:55 AM UTC 24
Peak memory	224848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003898950 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.4003898950 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/14.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.1227916641
Short name	T811
Test name
Test status
Simulation time	153187264 ps
CPU time	2.52 seconds
Started	Aug 29 02:59:54 AM UTC 24
Finished	Aug 29 02:59:57 AM UTC 24
Peak memory	225552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227916641 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr_outstanding.1227916641 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/14.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.3276260348
Short name	T805
Test name
Test status
Simulation time	59583303 ps
CPU time	1.63 seconds
Started	Aug 29 02:59:51 AM UTC 24
Finished	Aug 29 02:59:54 AM UTC 24
Peak memory	224288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276260348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors.3276260348 +enable_masking= 1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.3422140611
Short name	T809
Test name
Test status
Simulation time	403923723 ps
CPU time	4.47 seconds
Started	Aug 29 02:59:51 AM UTC 24
Finished	Aug 29 02:59:57 AM UTC 24
Peak memory	229948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422140611 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors_with_csr_rw.342 2140611 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.4135160942
Short name	T812
Test name
Test status
Simulation time	547102599 ps
CPU time	4.85 seconds
Started	Aug 29 02:59:51 AM UTC 24
Finished	Aug 29 02:59:57 AM UTC 24
Peak memory	225816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135160942 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.4135160942 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/14.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.500227194
Short name	T813
Test name
Test status
Simulation time	396338738 ps
CPU time	4.52 seconds
Started	Aug 29 02:59:53 AM UTC 24
Finished	Aug 29 02:59:58 AM UTC 24
Peak memory	225556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500227194 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.500227194 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/14.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.4173435155
Short name	T820
Test name
Test status
Simulation time	44383415 ps
CPU time	2.5 seconds
Started	Aug 29 02:59:58 AM UTC 24
Finished	Aug 29 03:00:02 AM UTC 24
Peak memory	229652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4173435155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_mem _rw_with_rand_reset.4173435155 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.1739767318
Short name	T816
Test name
Test status
Simulation time	18292812 ps
CPU time	1.71 seconds
Started	Aug 29 02:59:58 AM UTC 24
Finished	Aug 29 03:00:01 AM UTC 24
Peak memory	224224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739767318 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.1739767318 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/15.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.4144728121
Short name	T815
Test name
Test status
Simulation time	27479288 ps
CPU time	1.19 seconds
Started	Aug 29 02:59:58 AM UTC 24
Finished	Aug 29 03:00:01 AM UTC 24
Peak memory	224496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144728121 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.4144728121 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/15.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2185971266
Short name	T821
Test name
Test status
Simulation time	98422333 ps
CPU time	3.92 seconds
Started	Aug 29 02:59:58 AM UTC 24
Finished	Aug 29 03:00:04 AM UTC 24
Peak memory	225464 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185971266 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr_outstanding.2185971266 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/15.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.3763568995
Short name	T810
Test name
Test status
Simulation time	62070109 ps
CPU time	1.14 seconds
Started	Aug 29 02:59:55 AM UTC 24
Finished	Aug 29 02:59:57 AM UTC 24
Peak memory	224448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763568995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors.3763568995 +enable_masking= 1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.2395358949
Short name	T818
Test name
Test status
Simulation time	118838632 ps
CPU time	4.21 seconds
Started	Aug 29 02:59:56 AM UTC 24
Finished	Aug 29 03:00:02 AM UTC 24
Peak memory	227900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395358949 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors_with_csr_rw.239 5358949 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.335325235
Short name	T817
Test name
Test status
Simulation time	332044489 ps
CPU time	4.17 seconds
Started	Aug 29 02:59:56 AM UTC 24
Finished	Aug 29 03:00:01 AM UTC 24
Peak memory	225560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335325235 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.335325235 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/15.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.2274003464
Short name	T819
Test name
Test status
Simulation time	105750483 ps
CPU time	3.58 seconds
Started	Aug 29 02:59:57 AM UTC 24
Finished	Aug 29 03:00:02 AM UTC 24
Peak memory	225612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274003464 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.2274003464 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/15.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2105729927
Short name	T833
Test name
Test status
Simulation time	35420251 ps
CPU time	3.58 seconds
Started	Aug 29 03:00:05 AM UTC 24
Finished	Aug 29 03:00:10 AM UTC 24
Peak memory	231708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2105729927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_mem _rw_with_rand_reset.2105729927 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.3459531259
Short name	T825
Test name
Test status
Simulation time	18138713 ps
CPU time	1.44 seconds
Started	Aug 29 03:00:05 AM UTC 24
Finished	Aug 29 03:00:08 AM UTC 24
Peak memory	224504 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459531259 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.3459531259 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/16.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.1735346584
Short name	T823
Test name
Test status
Simulation time	14885295 ps
CPU time	1.22 seconds
Started	Aug 29 03:00:01 AM UTC 24
Finished	Aug 29 03:00:07 AM UTC 24
Peak memory	224908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735346584 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.1735346584 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/16.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.18353901
Short name	T826
Test name
Test status
Simulation time	90988075 ps
CPU time	1.77 seconds
Started	Aug 29 03:00:05 AM UTC 24
Finished	Aug 29 03:00:08 AM UTC 24
Peak memory	224228 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18353901 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr_outstanding.18353901 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/16.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1232027761
Short name	T822
Test name
Test status
Simulation time	24061084 ps
CPU time	1.57 seconds
Started	Aug 29 03:00:00 AM UTC 24
Finished	Aug 29 03:00:06 AM UTC 24
Peak memory	224456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232027761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors.1232027761 +enable_masking= 1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.2144921307
Short name	T824
Test name
Test status
Simulation time	80106192 ps
CPU time	2.51 seconds
Started	Aug 29 03:00:00 AM UTC 24
Finished	Aug 29 03:00:07 AM UTC 24
Peak memory	230136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144921307 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors_with_csr_rw.214 4921307 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.3580963457
Short name	T828
Test name
Test status
Simulation time	1248794143 ps
CPU time	4.04 seconds
Started	Aug 29 03:00:00 AM UTC 24
Finished	Aug 29 03:00:09 AM UTC 24
Peak memory	225556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580963457 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.3580963457 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/16.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.2339186913
Short name	T830
Test name
Test status
Simulation time	98617041 ps
CPU time	4.04 seconds
Started	Aug 29 03:00:01 AM UTC 24
Finished	Aug 29 03:00:10 AM UTC 24
Peak memory	225336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339186913 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.2339186913 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/16.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1943935130
Short name	T836
Test name
Test status
Simulation time	132249169 ps
CPU time	2.45 seconds
Started	Aug 29 03:00:09 AM UTC 24
Finished	Aug 29 03:00:12 AM UTC 24
Peak memory	227740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1943935130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_mem _rw_with_rand_reset.1943935130 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.2984570183
Short name	T758
Test name
Test status
Simulation time	36714321 ps
CPU time	1.51 seconds
Started	Aug 29 03:00:08 AM UTC 24
Finished	Aug 29 03:00:10 AM UTC 24
Peak memory	224504 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984570183 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.2984570183 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/17.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.2083131792
Short name	T831
Test name
Test status
Simulation time	40857527 ps
CPU time	1.28 seconds
Started	Aug 29 03:00:08 AM UTC 24
Finished	Aug 29 03:00:10 AM UTC 24
Peak memory	224496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083131792 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.2083131792 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/17.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2323260510
Short name	T835
Test name
Test status
Simulation time	115788236 ps
CPU time	1.94 seconds
Started	Aug 29 03:00:09 AM UTC 24
Finished	Aug 29 03:00:12 AM UTC 24
Peak memory	224556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323260510 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr_outstanding.2323260510 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/17.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.4004168569
Short name	T827
Test name
Test status
Simulation time	26290027 ps
CPU time	1.75 seconds
Started	Aug 29 03:00:05 AM UTC 24
Finished	Aug 29 03:00:08 AM UTC 24
Peak memory	226336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004168569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors.4004168569 +enable_masking= 1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.2349343033
Short name	T834
Test name
Test status
Simulation time	533183398 ps
CPU time	4.84 seconds
Started	Aug 29 03:00:05 AM UTC 24
Finished	Aug 29 03:00:11 AM UTC 24
Peak memory	230160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349343033 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors_with_csr_rw.234 9343033 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.2866549096
Short name	T829
Test name
Test status
Simulation time	165327686 ps
CPU time	2.67 seconds
Started	Aug 29 03:00:05 AM UTC 24
Finished	Aug 29 03:00:09 AM UTC 24
Peak memory	225556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866549096 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.2866549096 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/17.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.3363795066
Short name	T191
Test name
Test status
Simulation time	275331212 ps
CPU time	4.01 seconds
Started	Aug 29 03:00:08 AM UTC 24
Finished	Aug 29 03:00:13 AM UTC 24
Peak memory	225480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363795066 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.3363795066 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/17.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2085757551
Short name	T843
Test name
Test status
Simulation time	91199923 ps
CPU time	2.76 seconds
Started	Aug 29 03:00:12 AM UTC 24
Finished	Aug 29 03:00:16 AM UTC 24
Peak memory	231764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2085757551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_mem _rw_with_rand_reset.2085757551 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.1511274044
Short name	T838
Test name
Test status
Simulation time	51353873 ps
CPU time	1.31 seconds
Started	Aug 29 03:00:11 AM UTC 24
Finished	Aug 29 03:00:14 AM UTC 24
Peak memory	224500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511274044 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.1511274044 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/18.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.1694138143
Short name	T837
Test name
Test status
Simulation time	51096130 ps
CPU time	1.29 seconds
Started	Aug 29 03:00:11 AM UTC 24
Finished	Aug 29 03:00:14 AM UTC 24
Peak memory	224848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694138143 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.1694138143 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/18.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.1783827238
Short name	T840
Test name
Test status
Simulation time	97156003 ps
CPU time	2.42 seconds
Started	Aug 29 03:00:11 AM UTC 24
Finished	Aug 29 03:00:15 AM UTC 24
Peak memory	225656 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783827238 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr_outstanding.1783827238 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/18.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1058996707
Short name	T832
Test name
Test status
Simulation time	88455313 ps
CPU time	2.11 seconds
Started	Aug 29 03:00:09 AM UTC 24
Finished	Aug 29 03:00:12 AM UTC 24
Peak memory	228032 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058996707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors.1058996707 +enable_masking= 1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.599257501
Short name	T839
Test name
Test status
Simulation time	36525231 ps
CPU time	2.47 seconds
Started	Aug 29 03:00:10 AM UTC 24
Finished	Aug 29 03:00:14 AM UTC 24
Peak memory	230140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599257501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors_with_csr_rw.5992 57501 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.1933912834
Short name	T844
Test name
Test status
Simulation time	254021647 ps
CPU time	5.16 seconds
Started	Aug 29 03:00:10 AM UTC 24
Finished	Aug 29 03:00:16 AM UTC 24
Peak memory	225620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933912834 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.1933912834 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/18.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.3161619040
Short name	T192
Test name
Test status
Simulation time	596215700 ps
CPU time	6.25 seconds
Started	Aug 29 03:00:11 AM UTC 24
Finished	Aug 29 03:00:19 AM UTC 24
Peak memory	225568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161619040 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.3161619040 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/18.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2786705575
Short name	T851
Test name
Test status
Simulation time	48762424 ps
CPU time	2.27 seconds
Started	Aug 29 03:00:16 AM UTC 24
Finished	Aug 29 03:00:19 AM UTC 24
Peak memory	229652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2786705575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_mem _rw_with_rand_reset.2786705575 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.4004566987
Short name	T847
Test name
Test status
Simulation time	18904184 ps
CPU time	1.73 seconds
Started	Aug 29 03:00:15 AM UTC 24
Finished	Aug 29 03:00:17 AM UTC 24
Peak memory	224456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004566987 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.4004566987 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/19.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.773950084
Short name	T845
Test name
Test status
Simulation time	36854608 ps
CPU time	1.24 seconds
Started	Aug 29 03:00:15 AM UTC 24
Finished	Aug 29 03:00:17 AM UTC 24
Peak memory	224500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773950084 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.773950084 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/19.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.2653170944
Short name	T848
Test name
Test status
Simulation time	52619543 ps
CPU time	2.05 seconds
Started	Aug 29 03:00:15 AM UTC 24
Finished	Aug 29 03:00:18 AM UTC 24
Peak memory	225492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653170944 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr_outstanding.2653170944 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/19.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.2224348599
Short name	T841
Test name
Test status
Simulation time	104954720 ps
CPU time	1.76 seconds
Started	Aug 29 03:00:12 AM UTC 24
Finished	Aug 29 03:00:15 AM UTC 24
Peak memory	226496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224348599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors.2224348599 +enable_masking= 1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2390735714
Short name	T842
Test name
Test status
Simulation time	23536273 ps
CPU time	1.95 seconds
Started	Aug 29 03:00:12 AM UTC 24
Finished	Aug 29 03:00:15 AM UTC 24
Peak memory	224436 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390735714 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors_with_csr_rw.239 0735714 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.1577389041
Short name	T846
Test name
Test status
Simulation time	178337180 ps
CPU time	2.95 seconds
Started	Aug 29 03:00:13 AM UTC 24
Finished	Aug 29 03:00:17 AM UTC 24
Peak memory	225596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577389041 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.1577389041 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/19.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_aliasing.2079723370
Short name	T170
Test name
Test status
Simulation time	235731848 ps
CPU time	5 seconds
Started	Aug 29 02:58:48 AM UTC 24
Finished	Aug 29 02:58:53 AM UTC 24
Peak memory	225496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079723370 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.2079723370 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.1603878869
Short name	T733
Test name
Test status
Simulation time	2906864900 ps
CPU time	10.83 seconds
Started	Aug 29 02:58:47 AM UTC 24
Finished	Aug 29 02:58:59 AM UTC 24
Peak memory	225528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603878869 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.1603878869 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_hw_reset.3954500768
Short name	T167
Test name
Test status
Simulation time	242852769 ps
CPU time	1.59 seconds
Started	Aug 29 02:58:46 AM UTC 24
Finished	Aug 29 02:58:49 AM UTC 24
Peak memory	224496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954500768 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.3954500768 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.4272250328
Short name	T152
Test name
Test status
Simulation time	53332348 ps
CPU time	2.94 seconds
Started	Aug 29 02:58:50 AM UTC 24
Finished	Aug 29 02:58:54 AM UTC 24
Peak memory	231832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4272250328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_mem_ rw_with_rand_reset.4272250328 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_rw.3694920582
Short name	T729
Test name
Test status
Simulation time	38966455 ps
CPU time	1.48 seconds
Started	Aug 29 02:58:47 AM UTC 24
Finished	Aug 29 02:58:50 AM UTC 24
Peak memory	224216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694920582 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.3694920582 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_intr_test.2112683952
Short name	T171
Test name
Test status
Simulation time	52701883 ps
CPU time	1.26 seconds
Started	Aug 29 02:58:45 AM UTC 24
Finished	Aug 29 02:58:47 AM UTC 24
Peak memory	224224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112683952 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.2112683952 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_partial_access.2977589075
Short name	T156
Test name
Test status
Simulation time	31264975 ps
CPU time	1.87 seconds
Started	Aug 29 02:58:43 AM UTC 24
Finished	Aug 29 02:58:46 AM UTC 24
Peak memory	224568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977589075 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial_access.2977589075 +enable_masking =1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_walk.645117174
Short name	T728
Test name
Test status
Simulation time	20605916 ps
CPU time	1.24 seconds
Started	Aug 29 02:58:43 AM UTC 24
Finished	Aug 29 02:58:45 AM UTC 24
Peak memory	224220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645117174 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.645117174 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_same_csr_outstanding.4141601263
Short name	T168
Test name
Test status
Simulation time	66456833 ps
CPU time	2.52 seconds
Started	Aug 29 02:58:49 AM UTC 24
Finished	Aug 29 02:58:52 AM UTC 24
Peak memory	225544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141601263 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_outstanding.4141601263 +enable_mas king=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors.2593358624
Short name	T121
Test name
Test status
Simulation time	63196099 ps
CPU time	1.56 seconds
Started	Aug 29 02:58:41 AM UTC 24
Finished	Aug 29 02:58:43 AM UTC 24
Peak memory	224448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593358624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors.2593358624 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.3711649181
Short name	T119
Test name
Test status
Simulation time	158984072 ps
CPU time	2.75 seconds
Started	Aug 29 02:58:42 AM UTC 24
Finished	Aug 29 02:58:46 AM UTC 24
Peak memory	230200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711649181 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors_with_csr_rw.3711 649181 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_errors.2797910667
Short name	T145
Test name
Test status
Simulation time	95351566 ps
CPU time	3.79 seconds
Started	Aug 29 02:58:45 AM UTC 24
Finished	Aug 29 02:58:50 AM UTC 24
Peak memory	225628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797910667 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.2797910667 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_intg_err.296950246
Short name	T137
Test name
Test status
Simulation time	123327485 ps
CPU time	4.91 seconds
Started	Aug 29 02:58:45 AM UTC 24
Finished	Aug 29 02:58:51 AM UTC 24
Peak memory	225496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296950246 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.296950246 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.956884622
Short name	T849
Test name
Test status
Simulation time	16082512 ps
CPU time	1.13 seconds
Started	Aug 29 03:00:16 AM UTC 24
Finished	Aug 29 03:00:18 AM UTC 24
Peak memory	224284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956884622 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.956884622 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/20.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.3264486017
Short name	T850
Test name
Test status
Simulation time	16448446 ps
CPU time	1.32 seconds
Started	Aug 29 03:00:16 AM UTC 24
Finished	Aug 29 03:00:19 AM UTC 24
Peak memory	224704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264486017 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.3264486017 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/21.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.1151427591
Short name	T853
Test name
Test status
Simulation time	40645858 ps
CPU time	1.24 seconds
Started	Aug 29 03:00:17 AM UTC 24
Finished	Aug 29 03:00:20 AM UTC 24
Peak memory	224448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151427591 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.1151427591 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/22.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.2666925063
Short name	T852
Test name
Test status
Simulation time	20962919 ps
CPU time	1 seconds
Started	Aug 29 03:00:17 AM UTC 24
Finished	Aug 29 03:00:20 AM UTC 24
Peak memory	224616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666925063 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.2666925063 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/23.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.55402587
Short name	T854
Test name
Test status
Simulation time	30795798 ps
CPU time	1.2 seconds
Started	Aug 29 03:00:18 AM UTC 24
Finished	Aug 29 03:00:20 AM UTC 24
Peak memory	224644 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55402587 -assert nopostproc +UVM_TESTNAME=kmac_ base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/k mac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.55402587 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/24.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.2519967410
Short name	T855
Test name
Test status
Simulation time	17919982 ps
CPU time	1.15 seconds
Started	Aug 29 03:00:19 AM UTC 24
Finished	Aug 29 03:00:21 AM UTC 24
Peak memory	224496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519967410 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.2519967410 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/25.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.121375950
Short name	T856
Test name
Test status
Simulation time	104076720 ps
CPU time	1.19 seconds
Started	Aug 29 03:00:19 AM UTC 24
Finished	Aug 29 03:00:21 AM UTC 24
Peak memory	224452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121375950 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.121375950 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/26.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.4159894025
Short name	T857
Test name
Test status
Simulation time	16588649 ps
CPU time	1.16 seconds
Started	Aug 29 03:00:19 AM UTC 24
Finished	Aug 29 03:00:21 AM UTC 24
Peak memory	224448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159894025 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.4159894025 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/27.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.2740670846
Short name	T858
Test name
Test status
Simulation time	19204187 ps
CPU time	1.34 seconds
Started	Aug 29 03:00:19 AM UTC 24
Finished	Aug 29 03:00:22 AM UTC 24
Peak memory	224556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740670846 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.2740670846 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/28.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.376678957
Short name	T859
Test name
Test status
Simulation time	19702566 ps
CPU time	1.27 seconds
Started	Aug 29 03:00:19 AM UTC 24
Finished	Aug 29 03:00:22 AM UTC 24
Peak memory	224620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376678957 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.376678957 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/29.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.345574725
Short name	T741
Test name
Test status
Simulation time	471069658 ps
CPU time	6.49 seconds
Started	Aug 29 02:58:57 AM UTC 24
Finished	Aug 29 02:59:05 AM UTC 24
Peak memory	225596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345574725 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.345574725 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.3297856656
Short name	T774
Test name
Test status
Simulation time	7601907894 ps
CPU time	39.17 seconds
Started	Aug 29 02:58:56 AM UTC 24
Finished	Aug 29 02:59:37 AM UTC 24
Peak memory	225616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297856656 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.3297856656 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_hw_reset.1326395805
Short name	T731
Test name
Test status
Simulation time	104760348 ps
CPU time	1.9 seconds
Started	Aug 29 02:58:54 AM UTC 24
Finished	Aug 29 02:58:57 AM UTC 24
Peak memory	224500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326395805 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.1326395805 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.2722703523
Short name	T738
Test name
Test status
Simulation time	269628673 ps
CPU time	3.89 seconds
Started	Aug 29 02:58:58 AM UTC 24
Finished	Aug 29 02:59:02 AM UTC 24
Peak memory	231768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2722703523 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_mem_ rw_with_rand_reset.2722703523 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_rw.4044161031
Short name	T732
Test name
Test status
Simulation time	63406339 ps
CPU time	1.6 seconds
Started	Aug 29 02:58:55 AM UTC 24
Finished	Aug 29 02:58:58 AM UTC 24
Peak memory	224500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044161031 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.4044161031 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_intr_test.3001615435
Short name	T173
Test name
Test status
Simulation time	72857031 ps
CPU time	1.08 seconds
Started	Aug 29 02:58:54 AM UTC 24
Finished	Aug 29 02:58:56 AM UTC 24
Peak memory	224500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001615435 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.3001615435 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_partial_access.10375084
Short name	T157
Test name
Test status
Simulation time	68136471 ps
CPU time	2.3 seconds
Started	Aug 29 02:58:53 AM UTC 24
Finished	Aug 29 02:58:56 AM UTC 24
Peak memory	225556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10375084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial_access.10375084 +enable_masking=1 + sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_walk.3426579784
Short name	T730
Test name
Test status
Simulation time	30758978 ps
CPU time	1.18 seconds
Started	Aug 29 02:58:52 AM UTC 24
Finished	Aug 29 02:58:54 AM UTC 24
Peak memory	224620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426579784 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.3426579784 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_same_csr_outstanding.1039219719
Short name	T737
Test name
Test status
Simulation time	37657480 ps
CPU time	3.47 seconds
Started	Aug 29 02:58:57 AM UTC 24
Finished	Aug 29 02:59:02 AM UTC 24
Peak memory	225496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039219719 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_outstanding.1039219719 +enable_mas king=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors.1503315183
Short name	T194
Test name
Test status
Simulation time	30430450 ps
CPU time	1.79 seconds
Started	Aug 29 02:58:51 AM UTC 24
Finished	Aug 29 02:58:54 AM UTC 24
Peak memory	224284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503315183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors.1503315183 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.3819348911
Short name	T122
Test name
Test status
Simulation time	130006009 ps
CPU time	3.25 seconds
Started	Aug 29 02:58:51 AM UTC 24
Finished	Aug 29 02:58:55 AM UTC 24
Peak memory	230024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819348911 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors_with_csr_rw.3819 348911 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_errors.1031777236
Short name	T153
Test name
Test status
Simulation time	195460221 ps
CPU time	2.65 seconds
Started	Aug 29 02:58:54 AM UTC 24
Finished	Aug 29 02:58:58 AM UTC 24
Peak memory	225604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031777236 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.1031777236 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.2917391287
Short name	T862
Test name
Test status
Simulation time	37752240 ps
CPU time	1.19 seconds
Started	Aug 29 03:00:21 AM UTC 24
Finished	Aug 29 03:00:23 AM UTC 24
Peak memory	225144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917391287 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.2917391287 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/30.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.2814509115
Short name	T863
Test name
Test status
Simulation time	19305041 ps
CPU time	1.3 seconds
Started	Aug 29 03:00:21 AM UTC 24
Finished	Aug 29 03:00:23 AM UTC 24
Peak memory	224496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814509115 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.2814509115 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/31.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.2026462067
Short name	T860
Test name
Test status
Simulation time	17964169 ps
CPU time	1.07 seconds
Started	Aug 29 03:00:21 AM UTC 24
Finished	Aug 29 03:00:23 AM UTC 24
Peak memory	224848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026462067 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.2026462067 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/32.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.2928999522
Short name	T861
Test name
Test status
Simulation time	14019572 ps
CPU time	1.08 seconds
Started	Aug 29 03:00:21 AM UTC 24
Finished	Aug 29 03:00:23 AM UTC 24
Peak memory	225000 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928999522 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.2928999522 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/33.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.2989346007
Short name	T864
Test name
Test status
Simulation time	20388039 ps
CPU time	1.13 seconds
Started	Aug 29 03:00:22 AM UTC 24
Finished	Aug 29 03:00:24 AM UTC 24
Peak memory	224280 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989346007 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.2989346007 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/34.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.3952195095
Short name	T865
Test name
Test status
Simulation time	116892946 ps
CPU time	1.24 seconds
Started	Aug 29 03:00:22 AM UTC 24
Finished	Aug 29 03:00:24 AM UTC 24
Peak memory	224500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952195095 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.3952195095 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/35.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.193157675
Short name	T866
Test name
Test status
Simulation time	37468971 ps
CPU time	1.3 seconds
Started	Aug 29 03:00:22 AM UTC 24
Finished	Aug 29 03:00:24 AM UTC 24
Peak memory	224852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193157675 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.193157675 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/36.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.3043892197
Short name	T867
Test name
Test status
Simulation time	49448771 ps
CPU time	1.31 seconds
Started	Aug 29 03:00:22 AM UTC 24
Finished	Aug 29 03:00:24 AM UTC 24
Peak memory	224616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043892197 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.3043892197 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/37.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.2727105265
Short name	T869
Test name
Test status
Simulation time	105310725 ps
CPU time	1.29 seconds
Started	Aug 29 03:00:23 AM UTC 24
Finished	Aug 29 03:00:25 AM UTC 24
Peak memory	224456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727105265 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.2727105265 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/38.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.1744774773
Short name	T868
Test name
Test status
Simulation time	42495042 ps
CPU time	1.1 seconds
Started	Aug 29 03:00:23 AM UTC 24
Finished	Aug 29 03:00:25 AM UTC 24
Peak memory	224496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744774773 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.1744774773 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/39.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.1963569281
Short name	T747
Test name
Test status
Simulation time	392884357 ps
CPU time	6.34 seconds
Started	Aug 29 02:59:04 AM UTC 24
Finished	Aug 29 02:59:12 AM UTC 24
Peak memory	225492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963569281 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.1963569281 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.4154078525
Short name	T763
Test name
Test status
Simulation time	1274015438 ps
CPU time	22.32 seconds
Started	Aug 29 02:59:04 AM UTC 24
Finished	Aug 29 02:59:28 AM UTC 24
Peak memory	225540 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154078525 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.4154078525 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_hw_reset.4132358248
Short name	T742
Test name
Test status
Simulation time	32137498 ps
CPU time	1.74 seconds
Started	Aug 29 02:59:03 AM UTC 24
Finished	Aug 29 02:59:06 AM UTC 24
Peak memory	224496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132358248 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.4132358248 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.837035149
Short name	T746
Test name
Test status
Simulation time	288955702 ps
CPU time	3.81 seconds
Started	Aug 29 02:59:06 AM UTC 24
Finished	Aug 29 02:59:10 AM UTC 24
Peak memory	231700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=837035149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_mem_r w_with_rand_reset.837035149 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_rw.971069112
Short name	T744
Test name
Test status
Simulation time	149426764 ps
CPU time	1.8 seconds
Started	Aug 29 02:59:04 AM UTC 24
Finished	Aug 29 02:59:07 AM UTC 24
Peak memory	224556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971069112 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.971069112 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_partial_access.4025759974
Short name	T739
Test name
Test status
Simulation time	29284991 ps
CPU time	1.97 seconds
Started	Aug 29 02:59:01 AM UTC 24
Finished	Aug 29 02:59:04 AM UTC 24
Peak memory	224276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025759974 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial_access.4025759974 +enable_masking =1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_mem_partial_access/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_walk.1594563511
Short name	T736
Test name
Test status
Simulation time	12334426 ps
CPU time	1.13 seconds
Started	Aug 29 02:59:00 AM UTC 24
Finished	Aug 29 02:59:02 AM UTC 24
Peak memory	224452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594563511 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.1594563511 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_mem_walk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_same_csr_outstanding.3252323648
Short name	T745
Test name
Test status
Simulation time	95732103 ps
CPU time	2.41 seconds
Started	Aug 29 02:59:06 AM UTC 24
Finished	Aug 29 02:59:09 AM UTC 24
Peak memory	225680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252323648 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_outstanding.3252323648 +enable_mas king=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors.3665979673
Short name	T735
Test name
Test status
Simulation time	30370291 ps
CPU time	1.45 seconds
Started	Aug 29 02:58:59 AM UTC 24
Finished	Aug 29 02:59:01 AM UTC 24
Peak memory	224444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665979673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors.3665979673 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2982546307
Short name	T740
Test name
Test status
Simulation time	110923153 ps
CPU time	4.35 seconds
Started	Aug 29 02:58:59 AM UTC 24
Finished	Aug 29 02:59:04 AM UTC 24
Peak memory	229940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982546307 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors_with_csr_rw.2982 546307 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_errors.3977222849
Short name	T743
Test name
Test status
Simulation time	120743252 ps
CPU time	3.49 seconds
Started	Aug 29 02:59:02 AM UTC 24
Finished	Aug 29 02:59:06 AM UTC 24
Peak memory	225560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977222849 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.3977222849 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_intg_err.1596464583
Short name	T184
Test name
Test status
Simulation time	451618235 ps
CPU time	7.01 seconds
Started	Aug 29 02:59:03 AM UTC 24
Finished	Aug 29 02:59:11 AM UTC 24
Peak memory	225460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596464583 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.1596464583 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.2601860061
Short name	T870
Test name
Test status
Simulation time	20254168 ps
CPU time	1.32 seconds
Started	Aug 29 03:00:23 AM UTC 24
Finished	Aug 29 03:00:25 AM UTC 24
Peak memory	224496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601860061 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.2601860061 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/40.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.2531193041
Short name	T874
Test name
Test status
Simulation time	15606222 ps
CPU time	1.32 seconds
Started	Aug 29 03:00:24 AM UTC 24
Finished	Aug 29 03:00:27 AM UTC 24
Peak memory	224616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531193041 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.2531193041 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/41.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.1483010578
Short name	T873
Test name
Test status
Simulation time	40857243 ps
CPU time	1.26 seconds
Started	Aug 29 03:00:24 AM UTC 24
Finished	Aug 29 03:00:26 AM UTC 24
Peak memory	223128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483010578 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.1483010578 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/42.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.2438526947
Short name	T872
Test name
Test status
Simulation time	20656609 ps
CPU time	1.16 seconds
Started	Aug 29 03:00:24 AM UTC 24
Finished	Aug 29 03:00:26 AM UTC 24
Peak memory	224496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438526947 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.2438526947 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/43.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.3896142034
Short name	T871
Test name
Test status
Simulation time	26165763 ps
CPU time	1.03 seconds
Started	Aug 29 03:00:24 AM UTC 24
Finished	Aug 29 03:00:26 AM UTC 24
Peak memory	224496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896142034 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.3896142034 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/44.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.2886914490
Short name	T875
Test name
Test status
Simulation time	17140840 ps
CPU time	1.31 seconds
Started	Aug 29 03:00:24 AM UTC 24
Finished	Aug 29 03:00:27 AM UTC 24
Peak memory	224584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886914490 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.2886914490 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/45.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.1918155028
Short name	T876
Test name
Test status
Simulation time	52155895 ps
CPU time	1.1 seconds
Started	Aug 29 03:00:26 AM UTC 24
Finished	Aug 29 03:00:28 AM UTC 24
Peak memory	225024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918155028 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.1918155028 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/46.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.4130444806
Short name	T877
Test name
Test status
Simulation time	36032908 ps
CPU time	1.18 seconds
Started	Aug 29 03:00:26 AM UTC 24
Finished	Aug 29 03:00:28 AM UTC 24
Peak memory	224496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130444806 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.4130444806 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/47.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.2465828041
Short name	T878
Test name
Test status
Simulation time	13391687 ps
CPU time	1.26 seconds
Started	Aug 29 03:00:26 AM UTC 24
Finished	Aug 29 03:00:28 AM UTC 24
Peak memory	224908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465828041 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.2465828041 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/48.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.1674930342
Short name	T879
Test name
Test status
Simulation time	68007754 ps
CPU time	1.26 seconds
Started	Aug 29 03:00:26 AM UTC 24
Finished	Aug 29 03:00:28 AM UTC 24
Peak memory	224616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674930342 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.1674930342 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/49.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.434677623
Short name	T752
Test name
Test status
Simulation time	36469043 ps
CPU time	3.94 seconds
Started	Aug 29 02:59:12 AM UTC 24
Finished	Aug 29 02:59:17 AM UTC 24
Peak memory	231700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=434677623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_mem_r w_with_rand_reset.434677623 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_rw.1917667088
Short name	T749
Test name
Test status
Simulation time	144238251 ps
CPU time	1.68 seconds
Started	Aug 29 02:59:11 AM UTC 24
Finished	Aug 29 02:59:14 AM UTC 24
Peak memory	224556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917667088 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.1917667088 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/5.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_intr_test.1215096603
Short name	T176
Test name
Test status
Simulation time	24851856 ps
CPU time	1.12 seconds
Started	Aug 29 02:59:10 AM UTC 24
Finished	Aug 29 02:59:12 AM UTC 24
Peak memory	224620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215096603 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.1215096603 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/5.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_same_csr_outstanding.1564833197
Short name	T750
Test name
Test status
Simulation time	24580601 ps
CPU time	2.3 seconds
Started	Aug 29 02:59:11 AM UTC 24
Finished	Aug 29 02:59:15 AM UTC 24
Peak memory	225616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564833197 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_outstanding.1564833197 +enable_mas king=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/5.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors.499209495
Short name	T123
Test name
Test status
Simulation time	36476585 ps
CPU time	1.83 seconds
Started	Aug 29 02:59:07 AM UTC 24
Finished	Aug 29 02:59:09 AM UTC 24
Peak memory	224556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499209495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors.499209495 +enable_masking=1 + sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2431194572
Short name	T134
Test name
Test status
Simulation time	63961388 ps
CPU time	2.77 seconds
Started	Aug 29 02:59:07 AM UTC 24
Finished	Aug 29 02:59:11 AM UTC 24
Peak memory	225596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431194572 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors_with_csr_rw.2431 194572 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.2882607776
Short name	T748
Test name
Test status
Simulation time	279545734 ps
CPU time	3.2 seconds
Started	Aug 29 02:59:08 AM UTC 24
Finished	Aug 29 02:59:12 AM UTC 24
Peak memory	225564 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882607776 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.2882607776 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/5.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.1265614113
Short name	T190
Test name
Test status
Simulation time	100145869 ps
CPU time	3.38 seconds
Started	Aug 29 02:59:10 AM UTC 24
Finished	Aug 29 02:59:14 AM UTC 24
Peak memory	225480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265614113 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.1265614113 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/5.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2091591298
Short name	T756
Test name
Test status
Simulation time	278393032 ps
CPU time	3.66 seconds
Started	Aug 29 02:59:18 AM UTC 24
Finished	Aug 29 02:59:22 AM UTC 24
Peak memory	231704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2091591298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_mem_ rw_with_rand_reset.2091591298 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_rw.2952393722
Short name	T753
Test name
Test status
Simulation time	274194838 ps
CPU time	1.7 seconds
Started	Aug 29 02:59:16 AM UTC 24
Finished	Aug 29 02:59:18 AM UTC 24
Peak memory	224492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952393722 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.2952393722 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/6.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_intr_test.2622157465
Short name	T174
Test name
Test status
Simulation time	16746133 ps
CPU time	0.96 seconds
Started	Aug 29 02:59:15 AM UTC 24
Finished	Aug 29 02:59:17 AM UTC 24
Peak memory	224560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622157465 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.2622157465 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/6.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.480582884
Short name	T754
Test name
Test status
Simulation time	133294262 ps
CPU time	2.3 seconds
Started	Aug 29 02:59:17 AM UTC 24
Finished	Aug 29 02:59:20 AM UTC 24
Peak memory	225548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480582884 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_outstanding.480582884 +enable_maski ng=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/6.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3376707339
Short name	T734
Test name
Test status
Simulation time	62516619 ps
CPU time	1.94 seconds
Started	Aug 29 02:59:13 AM UTC 24
Finished	Aug 29 02:59:16 AM UTC 24
Peak memory	226492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376707339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors.3376707339 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.17213923
Short name	T751
Test name
Test status
Simulation time	33974607 ps
CPU time	2.07 seconds
Started	Aug 29 02:59:13 AM UTC 24
Finished	Aug 29 02:59:16 AM UTC 24
Peak memory	229936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17213923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors_with_csr_rw.172139 23 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_errors.2019907932
Short name	T755
Test name
Test status
Simulation time	422824347 ps
CPU time	6.24 seconds
Started	Aug 29 02:59:13 AM UTC 24
Finished	Aug 29 02:59:21 AM UTC 24
Peak memory	225624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019907932 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.2019907932 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/6.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.1220605977
Short name	T762
Test name
Test status
Simulation time	58426655 ps
CPU time	2.85 seconds
Started	Aug 29 02:59:23 AM UTC 24
Finished	Aug 29 02:59:27 AM UTC 24
Peak memory	229848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1220605977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_mem_ rw_with_rand_reset.1220605977 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.1532846813
Short name	T757
Test name
Test status
Simulation time	22319131 ps
CPU time	1.3 seconds
Started	Aug 29 02:59:21 AM UTC 24
Finished	Aug 29 02:59:23 AM UTC 24
Peak memory	224284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532846813 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.1532846813 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/7.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_intr_test.97979400
Short name	T179
Test name
Test status
Simulation time	21416064 ps
CPU time	1.1 seconds
Started	Aug 29 02:59:21 AM UTC 24
Finished	Aug 29 02:59:23 AM UTC 24
Peak memory	224616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97979400 -assert nopostproc +UVM_TESTNAME=kmac_ base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/k mac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.97979400 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/7.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.2865957654
Short name	T760
Test name
Test status
Simulation time	34279918 ps
CPU time	2.72 seconds
Started	Aug 29 02:59:22 AM UTC 24
Finished	Aug 29 02:59:26 AM UTC 24
Peak memory	225664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865957654 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_outstanding.2865957654 +enable_mas king=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/7.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.2153300973
Short name	T120
Test name
Test status
Simulation time	646167634 ps
CPU time	4.21 seconds
Started	Aug 29 02:59:19 AM UTC 24
Finished	Aug 29 02:59:24 AM UTC 24
Peak memory	230032 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153300973 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors_with_csr_rw.2153 300973 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.2523031007
Short name	T759
Test name
Test status
Simulation time	485792612 ps
CPU time	5.13 seconds
Started	Aug 29 02:59:19 AM UTC 24
Finished	Aug 29 02:59:25 AM UTC 24
Peak memory	225696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523031007 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.2523031007 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/7.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.562391574
Short name	T186
Test name
Test status
Simulation time	101359091 ps
CPU time	5.08 seconds
Started	Aug 29 02:59:21 AM UTC 24
Finished	Aug 29 02:59:27 AM UTC 24
Peak memory	225488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562391574 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.562391574 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/7.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.1805541300
Short name	T766
Test name
Test status
Simulation time	41824360 ps
CPU time	2.49 seconds
Started	Aug 29 02:59:28 AM UTC 24
Finished	Aug 29 02:59:31 AM UTC 24
Peak memory	227604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1805541300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_mem_ rw_with_rand_reset.1805541300 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.3848750321
Short name	T765
Test name
Test status
Simulation time	24491369 ps
CPU time	1.61 seconds
Started	Aug 29 02:59:28 AM UTC 24
Finished	Aug 29 02:59:30 AM UTC 24
Peak memory	224492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848750321 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.3848750321 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/8.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.2537911733
Short name	T764
Test name
Test status
Simulation time	17616949 ps
CPU time	1.35 seconds
Started	Aug 29 02:59:27 AM UTC 24
Finished	Aug 29 02:59:29 AM UTC 24
Peak memory	224648 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537911733 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.2537911733 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/8.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.360657982
Short name	T767
Test name
Test status
Simulation time	903654769 ps
CPU time	3.51 seconds
Started	Aug 29 02:59:28 AM UTC 24
Finished	Aug 29 02:59:32 AM UTC 24
Peak memory	225552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360657982 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_outstanding.360657982 +enable_maski ng=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/8.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.1670928345
Short name	T761
Test name
Test status
Simulation time	91725978 ps
CPU time	1.51 seconds
Started	Aug 29 02:59:24 AM UTC 24
Finished	Aug 29 02:59:27 AM UTC 24
Peak memory	226332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670928345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors.1670928345 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.4268711805
Short name	T124
Test name
Test status
Simulation time	46148733 ps
CPU time	3.45 seconds
Started	Aug 29 02:59:24 AM UTC 24
Finished	Aug 29 02:59:29 AM UTC 24
Peak memory	230004 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268711805 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors_with_csr_rw.4268 711805 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.92669021
Short name	T768
Test name
Test status
Simulation time	166766911 ps
CPU time	6.81 seconds
Started	Aug 29 02:59:25 AM UTC 24
Finished	Aug 29 02:59:33 AM UTC 24
Peak memory	225252 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92669021 -assert nopostproc +UVM_TESTNAME=kmac_ base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/k mac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.92669021 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/8.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.1522718895
Short name	T188
Test name
Test status
Simulation time	225933349 ps
CPU time	5.2 seconds
Started	Aug 29 02:59:25 AM UTC 24
Finished	Aug 29 02:59:32 AM UTC 24
Peak memory	225556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522718895 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.1522718895 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/8.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3181678131
Short name	T773
Test name
Test status
Simulation time	153204261 ps
CPU time	2.12 seconds
Started	Aug 29 02:59:33 AM UTC 24
Finished	Aug 29 02:59:36 AM UTC 24
Peak memory	227612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3181678131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_mem_ rw_with_rand_reset.3181678131 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.4147985111
Short name	T770
Test name
Test status
Simulation time	90654608 ps
CPU time	1.63 seconds
Started	Aug 29 02:59:32 AM UTC 24
Finished	Aug 29 02:59:35 AM UTC 24
Peak memory	224492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147985111 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.4147985111 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/9.kmac_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.3479768415
Short name	T178
Test name
Test status
Simulation time	23297704 ps
CPU time	1.24 seconds
Started	Aug 29 02:59:32 AM UTC 24
Finished	Aug 29 02:59:34 AM UTC 24
Peak memory	224620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479768415 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.3479768415 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/9.kmac_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2059560634
Short name	T772
Test name
Test status
Simulation time	151711591 ps
CPU time	2.42 seconds
Started	Aug 29 02:59:32 AM UTC 24
Finished	Aug 29 02:59:36 AM UTC 24
Peak memory	225680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059560634 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_outstanding.2059560634 +enable_mas king=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/9.kmac_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1275014881
Short name	T125
Test name
Test status
Simulation time	141088557 ps
CPU time	1.92 seconds
Started	Aug 29 02:59:29 AM UTC 24
Finished	Aug 29 02:59:32 AM UTC 24
Peak memory	224444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275014881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors.1275014881 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.1915373149
Short name	T771
Test name
Test status
Simulation time	234355730 ps
CPU time	3.99 seconds
Started	Aug 29 02:59:30 AM UTC 24
Finished	Aug 29 02:59:35 AM UTC 24
Peak memory	230000 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915373149 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors_with_csr_rw.1915 373149 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.509235728
Short name	T769
Test name
Test status
Simulation time	246778501 ps
CPU time	3.02 seconds
Started	Aug 29 02:59:30 AM UTC 24
Finished	Aug 29 02:59:34 AM UTC 24
Peak memory	225600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509235728 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.509235728 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/9.kmac_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.2032838183
Short name	T187
Test name
Test status
Simulation time	254223023 ps
CPU time	3.5 seconds
Started	Aug 29 02:59:31 AM UTC 24
Finished	Aug 29 02:59:35 AM UTC 24
Peak memory	225684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032838183 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.2032838183 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/9.kmac_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/0.kmac_app.3857445947
Short name	T14
Test name
Test status
Simulation time	1668518177 ps
CPU time	121.58 seconds
Started	Aug 29 06:18:17 AM UTC 24
Finished	Aug 29 06:20:21 AM UTC 24
Peak memory	270560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857445947 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.3857445947 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/0.kmac_app_with_partial_data.4036494224
Short name	T247
Test name
Test status
Simulation time	20483370259 ps
CPU time	490.63 seconds
Started	Aug 29 06:18:18 AM UTC 24
Finished	Aug 29 06:26:36 AM UTC 24
Peak memory	584024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036494224 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.4036494224 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_app_with_partial_data/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/0.kmac_burst_write.147128622
Short name	T341
Test name
Test status
Simulation time	64577561874 ps
CPU time	1169.88 seconds
Started	Aug 29 06:18:15 AM UTC 24
Finished	Aug 29 06:37:59 AM UTC 24
Peak memory	268540 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147128622 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.147128622 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/0.kmac_edn_timeout_error.688269359
Short name	T22
Test name
Test status
Simulation time	1474185994 ps
CPU time	34.87 seconds
Started	Aug 29 06:18:39 AM UTC 24
Finished	Aug 29 06:19:16 AM UTC 24
Peak memory	245688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688269359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.688269359 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/0.kmac_long_msg_and_output.4129436187
Short name	T218
Test name
Test status
Simulation time	22801498789 ps
CPU time	315.12 seconds
Started	Aug 29 06:18:15 AM UTC 24
Finished	Aug 29 06:23:35 AM UTC 24
Peak memory	387036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129436187 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_and_output.4129436187 +enable_masking =1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/0.kmac_mubi.2280511225
Short name	T80
Test name
Test status
Simulation time	68007403470 ps
CPU time	361.67 seconds
Started	Aug 29 06:18:20 AM UTC 24
Finished	Aug 29 06:24:27 AM UTC 24
Peak memory	488064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280511225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.2280511225 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/0.kmac_sec_cm.1399031373
Short name	T48
Test name
Test status
Simulation time	65259353894 ps
CPU time	98.85 seconds
Started	Aug 29 06:18:44 AM UTC 24
Finished	Aug 29 06:20:25 AM UTC 24
Peak memory	292348 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399031373 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.1399031373 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/0.kmac_sideload.1197835921
Short name	T30
Test name
Test status
Simulation time	16153086564 ps
CPU time	367.39 seconds
Started	Aug 29 06:18:15 AM UTC 24
Finished	Aug 29 06:24:28 AM UTC 24
Peak memory	345848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197835921 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.1197835921 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/0.kmac_stress_all.4147309541
Short name	T390
Test name
Test status
Simulation time	17691487752 ps
CPU time	1655.2 seconds
Started	Aug 29 06:18:44 AM UTC 24
Finished	Aug 29 06:46:39 AM UTC 24
Peak memory	580052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147309541 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.4147309541 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac.101062981
Short name	T1
Test name
Test status
Simulation time	59263678 ps
CPU time	2.03 seconds
Started	Aug 29 06:18:15 AM UTC 24
Finished	Aug 29 06:18:18 AM UTC 24
Peak memory	234336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101062981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vector s_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac.101062981 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac_xof.250551968
Short name	T2
Test name
Test status
Simulation time	238202493 ps
CPU time	2.48 seconds
Started	Aug 29 06:18:16 AM UTC 24
Finished	Aug 29 06:18:20 AM UTC 24
Peak memory	235676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250551968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vector s_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.250551968 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac_xof/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_224.2120549463
Short name	T451
Test name
Test status
Simulation time	18686368663 ps
CPU time	2201.06 seconds
Started	Aug 29 06:18:15 AM UTC 24
Finished	Aug 29 06:55:22 AM UTC 24
Peak memory	1180924 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120549463 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.2120549463 +enab le_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_224/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_384.1215757889
Short name	T49
Test name
Test status
Simulation time	2472924992 ps
CPU time	26.97 seconds
Started	Aug 29 06:18:15 AM UTC 24
Finished	Aug 29 06:18:43 AM UTC 24
Peak memory	235312 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215757889 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.1215757889 +enab le_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_384/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_512.554826509
Short name	T375
Test name
Test status
Simulation time	367857491807 ps
CPU time	1552.42 seconds
Started	Aug 29 06:18:15 AM UTC 24
Finished	Aug 29 06:44:26 AM UTC 24
Peak memory	1748020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554826509 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.554826509 +enable _masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_512/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_128.4137955171
Short name	T201
Test name
Test status
Simulation time	5063937784 ps
CPU time	192.86 seconds
Started	Aug 29 06:18:15 AM UTC 24
Finished	Aug 29 06:21:31 AM UTC 24
Peak memory	290252 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137955171 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.4137955171 +e nable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_128/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_256.3157121007
Short name	T495
Test name
Test status
Simulation time	231757246456 ps
CPU time	2454.5 seconds
Started	Aug 29 06:18:15 AM UTC 24
Finished	Aug 29 06:59:37 AM UTC 24
Peak memory	2993508 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157121007 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.3157121007 +e nable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_256/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/1.kmac_alert_test.2036387744
Short name	T54
Test name
Test status
Simulation time	93707640 ps
CPU time	0.94 seconds
Started	Aug 29 06:18:46 AM UTC 24
Finished	Aug 29 06:18:48 AM UTC 24
Peak memory	226168 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036387744 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.2036387744 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/1.kmac_app.3855622274
Short name	T36
Test name
Test status
Simulation time	21124948633 ps
CPU time	162.61 seconds
Started	Aug 29 06:18:45 AM UTC 24
Finished	Aug 29 06:21:30 AM UTC 24
Peak memory	352556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855622274 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.3855622274 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/1.kmac_app_with_partial_data.2332703313
Short name	T199
Test name
Test status
Simulation time	20339958240 ps
CPU time	471.03 seconds
Started	Aug 29 06:18:45 AM UTC 24
Finished	Aug 29 06:26:43 AM UTC 24
Peak memory	534960 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332703313 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.2332703313 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_app_with_partial_data/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/1.kmac_burst_write.3390804285
Short name	T58
Test name
Test status
Simulation time	5368172547 ps
CPU time	56.9 seconds
Started	Aug 29 06:18:44 AM UTC 24
Finished	Aug 29 06:19:42 AM UTC 24
Peak memory	233984 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390804285 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.3390804285 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/1.kmac_edn_timeout_error.2210575179
Short name	T60
Test name
Test status
Simulation time	885057882 ps
CPU time	12.68 seconds
Started	Aug 29 06:18:45 AM UTC 24
Finished	Aug 29 06:18:59 AM UTC 24
Peak memory	231560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210575179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.2210575179 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_mode_error.657534277
Short name	T32
Test name
Test status
Simulation time	3867566380 ps
CPU time	49.37 seconds
Started	Aug 29 06:18:45 AM UTC 24
Finished	Aug 29 06:19:36 AM UTC 24
Peak memory	235628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657534277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.657534277 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_ready_error.3189106303
Short name	T209
Test name
Test status
Simulation time	6859469900 ps
CPU time	97.12 seconds
Started	Aug 29 06:18:45 AM UTC 24
Finished	Aug 29 06:20:25 AM UTC 24
Peak memory	234052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189106303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.3189106303 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_entropy_ready_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_refresh.1987604820
Short name	T13
Test name
Test status
Simulation time	2010945193 ps
CPU time	37.81 seconds
Started	Aug 29 06:18:45 AM UTC 24
Finished	Aug 29 06:19:24 AM UTC 24
Peak memory	241980 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987604820 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.1987604820 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/1.kmac_key_error.1737378225
Short name	T7
Test name
Test status
Simulation time	4061284194 ps
CPU time	8.59 seconds
Started	Aug 29 06:18:45 AM UTC 24
Finished	Aug 29 06:18:55 AM UTC 24
Peak memory	229636 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737378225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.1737378225 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/1.kmac_lc_escalation.3284035007
Short name	T10
Test name
Test status
Simulation time	58844616 ps
CPU time	1.88 seconds
Started	Aug 29 06:18:45 AM UTC 24
Finished	Aug 29 06:18:48 AM UTC 24
Peak memory	231304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284035007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.3284035007 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/1.kmac_long_msg_and_output.307610450
Short name	T200
Test name
Test status
Simulation time	13947374708 ps
CPU time	133.87 seconds
Started	Aug 29 06:18:44 AM UTC 24
Finished	Aug 29 06:21:00 AM UTC 24
Peak memory	395556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307610450 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_and_output.307610450 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/1.kmac_mubi.3825341699
Short name	T79
Test name
Test status
Simulation time	28829882204 ps
CPU time	325.9 seconds
Started	Aug 29 06:18:45 AM UTC 24
Finished	Aug 29 06:24:16 AM UTC 24
Peak memory	336520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825341699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.3825341699 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/1.kmac_smoke.2977111703
Short name	T94
Test name
Test status
Simulation time	3555743410 ps
CPU time	26.38 seconds
Started	Aug 29 06:18:44 AM UTC 24
Finished	Aug 29 06:19:12 AM UTC 24
Peak memory	235816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977111703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.2977111703 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/1.kmac_stress_all.3854307283
Short name	T606
Test name
Test status
Simulation time	408851541439 ps
CPU time	3278.55 seconds
Started	Aug 29 06:18:45 AM UTC 24
Finished	Aug 29 07:14:00 AM UTC 24
Peak memory	1618420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854307283 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.3854307283 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac.744489755
Short name	T53
Test name
Test status
Simulation time	173676950 ps
CPU time	2.14 seconds
Started	Aug 29 06:18:45 AM UTC 24
Finished	Aug 29 06:18:48 AM UTC 24
Peak memory	229776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744489755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vector s_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac.744489755 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_test_vectors_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac_xof.692020221
Short name	T55
Test name
Test status
Simulation time	82221922 ps
CPU time	2.69 seconds
Started	Aug 29 06:18:45 AM UTC 24
Finished	Aug 29 06:18:49 AM UTC 24
Peak memory	229772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692020221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vector s_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.692020221 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_test_vectors_kmac_xof/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_224.2361167743
Short name	T189
Test name
Test status
Simulation time	3647755437 ps
CPU time	45.45 seconds
Started	Aug 29 06:18:44 AM UTC 24
Finished	Aug 29 06:19:31 AM UTC 24
Peak memory	235372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361167743 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.2361167743 +enab le_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_224/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_256.2420845780
Short name	T453
Test name
Test status
Simulation time	17796488915 ps
CPU time	2180.17 seconds
Started	Aug 29 06:18:44 AM UTC 24
Finished	Aug 29 06:55:30 AM UTC 24
Peak memory	1140704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420845780 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.2420845780 +enab le_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_256/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_384.2453092782
Short name	T396
Test name
Test status
Simulation time	50982172495 ps
CPU time	1673.36 seconds
Started	Aug 29 06:18:44 AM UTC 24
Finished	Aug 29 06:46:57 AM UTC 24
Peak memory	925852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453092782 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.2453092782 +enab le_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_384/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_512.603116576
Short name	T91
Test name
Test status
Simulation time	1013400030 ps
CPU time	19.46 seconds
Started	Aug 29 06:18:44 AM UTC 24
Finished	Aug 29 06:19:05 AM UTC 24
Peak memory	233860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603116576 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.603116576 +enable _masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_512/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_256.3138271615
Short name	T433
Test name
Test status
Simulation time	70733885870 ps
CPU time	2060.71 seconds
Started	Aug 29 06:18:44 AM UTC 24
Finished	Aug 29 06:53:30 AM UTC 24
Peak memory	1126484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138271615 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.3138271615 +e nable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_256/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/10.kmac_alert_test.3789960003
Short name	T245
Test name
Test status
Simulation time	48582180 ps
CPU time	1.19 seconds
Started	Aug 29 06:26:15 AM UTC 24
Finished	Aug 29 06:26:18 AM UTC 24
Peak memory	226292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789960003 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.3789960003 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/10.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/10.kmac_app.30044361
Short name	T274
Test name
Test status
Simulation time	14840490271 ps
CPU time	232.68 seconds
Started	Aug 29 06:25:56 AM UTC 24
Finished	Aug 29 06:29:53 AM UTC 24
Peak memory	305408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30044361 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.30044361 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/10.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/10.kmac_burst_write.2873003840
Short name	T386
Test name
Test status
Simulation time	34938817708 ps
CPU time	1189.99 seconds
Started	Aug 29 06:25:38 AM UTC 24
Finished	Aug 29 06:45:42 AM UTC 24
Peak memory	264496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873003840 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.2873003840 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/10.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/10.kmac_edn_timeout_error.1441552788
Short name	T240
Test name
Test status
Simulation time	187788652 ps
CPU time	1.74 seconds
Started	Aug 29 06:26:08 AM UTC 24
Finished	Aug 29 06:26:11 AM UTC 24
Peak memory	227448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441552788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.1441552788 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/10.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/10.kmac_entropy_mode_error.1186951397
Short name	T242
Test name
Test status
Simulation time	196922971 ps
CPU time	1.9 seconds
Started	Aug 29 06:26:11 AM UTC 24
Finished	Aug 29 06:26:14 AM UTC 24
Peak memory	227512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186951397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.1186951397 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/10.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/10.kmac_entropy_refresh.3415383251
Short name	T261
Test name
Test status
Simulation time	29042605324 ps
CPU time	144.5 seconds
Started	Aug 29 06:25:58 AM UTC 24
Finished	Aug 29 06:28:25 AM UTC 24
Peak memory	295152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415383251 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.3415383251 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/10.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/10.kmac_error.3076342247
Short name	T38
Test name
Test status
Simulation time	4507937927 ps
CPU time	82.45 seconds
Started	Aug 29 06:26:05 AM UTC 24
Finished	Aug 29 06:27:29 AM UTC 24
Peak memory	268616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076342247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.3076342247 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/10.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/10.kmac_key_error.1954163374
Short name	T241
Test name
Test status
Simulation time	184365857 ps
CPU time	3.31 seconds
Started	Aug 29 06:26:07 AM UTC 24
Finished	Aug 29 06:26:11 AM UTC 24
Peak memory	227576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954163374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.1954163374 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/10.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/10.kmac_lc_escalation.1934460811
Short name	T113
Test name
Test status
Simulation time	62411748 ps
CPU time	2.33 seconds
Started	Aug 29 06:26:12 AM UTC 24
Finished	Aug 29 06:26:16 AM UTC 24
Peak memory	233800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934460811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.1934460811 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/10.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/10.kmac_long_msg_and_output.2848830068
Short name	T648
Test name
Test status
Simulation time	159057381023 ps
CPU time	3209.79 seconds
Started	Aug 29 06:25:21 AM UTC 24
Finished	Aug 29 07:19:27 AM UTC 24
Peak memory	3399988 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848830068 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_and_output.2848830068 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/10.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/10.kmac_sideload.1520921654
Short name	T255
Test name
Test status
Simulation time	2204062576 ps
CPU time	155.93 seconds
Started	Aug 29 06:25:32 AM UTC 24
Finished	Aug 29 06:28:10 AM UTC 24
Peak memory	295220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520921654 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.1520921654 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/10.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/10.kmac_smoke.353304028
Short name	T239
Test name
Test status
Simulation time	1437847157 ps
CPU time	40.5 seconds
Started	Aug 29 06:25:21 AM UTC 24
Finished	Aug 29 06:26:04 AM UTC 24
Peak memory	235704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353304028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.353304028 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/10.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/11.kmac_alert_test.4045093785
Short name	T252
Test name
Test status
Simulation time	97182553 ps
CPU time	1.41 seconds
Started	Aug 29 06:27:13 AM UTC 24
Finished	Aug 29 06:27:16 AM UTC 24
Peak memory	224972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045093785 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.4045093785 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/11.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/11.kmac_app.493840585
Short name	T263
Test name
Test status
Simulation time	2122524507 ps
CPU time	113.33 seconds
Started	Aug 29 06:26:37 AM UTC 24
Finished	Aug 29 06:28:32 AM UTC 24
Peak memory	262396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493840585 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.493840585 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/11.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/11.kmac_burst_write.2182031328
Short name	T162
Test name
Test status
Simulation time	129273238727 ps
CPU time	505.12 seconds
Started	Aug 29 06:26:32 AM UTC 24
Finished	Aug 29 06:35:04 AM UTC 24
Peak memory	252148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182031328 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.2182031328 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/11.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/11.kmac_edn_timeout_error.2111468070
Short name	T250
Test name
Test status
Simulation time	89846528 ps
CPU time	1.66 seconds
Started	Aug 29 06:27:07 AM UTC 24
Finished	Aug 29 06:27:10 AM UTC 24
Peak memory	227432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111468070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.2111468070 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/11.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/11.kmac_entropy_mode_error.462184630
Short name	T253
Test name
Test status
Simulation time	1504156417 ps
CPU time	28.93 seconds
Started	Aug 29 06:27:10 AM UTC 24
Finished	Aug 29 06:27:41 AM UTC 24
Peak memory	235636 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462184630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.462184630 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/11.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/11.kmac_entropy_refresh.3020636981
Short name	T97
Test name
Test status
Simulation time	3577652900 ps
CPU time	47.47 seconds
Started	Aug 29 06:26:44 AM UTC 24
Finished	Aug 29 06:27:33 AM UTC 24
Peak memory	252272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020636981 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.3020636981 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/11.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/11.kmac_error.266162077
Short name	T269
Test name
Test status
Simulation time	17786933108 ps
CPU time	165.78 seconds
Started	Aug 29 06:26:44 AM UTC 24
Finished	Aug 29 06:29:33 AM UTC 24
Peak memory	350460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266162077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.266162077 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/11.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/11.kmac_key_error.988043540
Short name	T249
Test name
Test status
Simulation time	140356965 ps
CPU time	1.98 seconds
Started	Aug 29 06:27:06 AM UTC 24
Finished	Aug 29 06:27:09 AM UTC 24
Peak memory	227512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988043540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.988043540 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/11.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/11.kmac_lc_escalation.2447179480
Short name	T41
Test name
Test status
Simulation time	123280800 ps
CPU time	1.93 seconds
Started	Aug 29 06:27:10 AM UTC 24
Finished	Aug 29 06:27:14 AM UTC 24
Peak memory	231304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447179480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.2447179480 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/11.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/11.kmac_long_msg_and_output.510398612
Short name	T437
Test name
Test status
Simulation time	71683429679 ps
CPU time	1640.64 seconds
Started	Aug 29 06:26:19 AM UTC 24
Finished	Aug 29 06:53:58 AM UTC 24
Peak memory	1026320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510398612 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_and_output.510398612 +enable_masking= 1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/11.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/11.kmac_sideload.2787550320
Short name	T292
Test name
Test status
Simulation time	33563812599 ps
CPU time	341.78 seconds
Started	Aug 29 06:26:19 AM UTC 24
Finished	Aug 29 06:32:05 AM UTC 24
Peak memory	346420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787550320 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.2787550320 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/11.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/11.kmac_smoke.2965438130
Short name	T248
Test name
Test status
Simulation time	1350368242 ps
CPU time	48.41 seconds
Started	Aug 29 06:26:16 AM UTC 24
Finished	Aug 29 06:27:06 AM UTC 24
Peak memory	235708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965438130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.2965438130 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/11.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/11.kmac_stress_all.1529319000
Short name	T445
Test name
Test status
Simulation time	19144825481 ps
CPU time	1634.99 seconds
Started	Aug 29 06:27:12 AM UTC 24
Finished	Aug 29 06:54:47 AM UTC 24
Peak memory	664168 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529319000 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.1529319000 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/11.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/12.kmac_alert_test.2936718315
Short name	T260
Test name
Test status
Simulation time	40238676 ps
CPU time	1.23 seconds
Started	Aug 29 06:28:15 AM UTC 24
Finished	Aug 29 06:28:17 AM UTC 24
Peak memory	226292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936718315 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.2936718315 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/12.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/12.kmac_app.330525436
Short name	T276
Test name
Test status
Simulation time	3509334293 ps
CPU time	136.59 seconds
Started	Aug 29 06:27:42 AM UTC 24
Finished	Aug 29 06:30:01 AM UTC 24
Peak memory	307516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330525436 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.330525436 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/12.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/12.kmac_burst_write.4196209803
Short name	T415
Test name
Test status
Simulation time	124255043928 ps
CPU time	1409.72 seconds
Started	Aug 29 06:27:34 AM UTC 24
Finished	Aug 29 06:51:20 AM UTC 24
Peak memory	268592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196209803 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.4196209803 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/12.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/12.kmac_edn_timeout_error.2757093850
Short name	T256
Test name
Test status
Simulation time	17344508 ps
CPU time	1.45 seconds
Started	Aug 29 06:28:06 AM UTC 24
Finished	Aug 29 06:28:09 AM UTC 24
Peak memory	227372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757093850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.2757093850 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/12.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/12.kmac_entropy_mode_error.3483776826
Short name	T257
Test name
Test status
Simulation time	156054144 ps
CPU time	1.42 seconds
Started	Aug 29 06:28:09 AM UTC 24
Finished	Aug 29 06:28:12 AM UTC 24
Peak memory	224364 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483776826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.3483776826 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/12.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/12.kmac_entropy_refresh.3824524610
Short name	T265
Test name
Test status
Simulation time	3303104694 ps
CPU time	87.37 seconds
Started	Aug 29 06:27:49 AM UTC 24
Finished	Aug 29 06:29:18 AM UTC 24
Peak memory	282932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824524610 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.3824524610 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/12.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/12.kmac_error.2406399368
Short name	T285
Test name
Test status
Simulation time	4632793010 ps
CPU time	148.24 seconds
Started	Aug 29 06:27:52 AM UTC 24
Finished	Aug 29 06:30:24 AM UTC 24
Peak memory	356676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406399368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.2406399368 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/12.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/12.kmac_key_error.1609110804
Short name	T258
Test name
Test status
Simulation time	1582731802 ps
CPU time	18.76 seconds
Started	Aug 29 06:27:54 AM UTC 24
Finished	Aug 29 06:28:14 AM UTC 24
Peak memory	229560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609110804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.1609110804 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/12.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/12.kmac_lc_escalation.3687882236
Short name	T259
Test name
Test status
Simulation time	120131958 ps
CPU time	2.07 seconds
Started	Aug 29 06:28:11 AM UTC 24
Finished	Aug 29 06:28:15 AM UTC 24
Peak memory	231760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687882236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.3687882236 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/12.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/12.kmac_long_msg_and_output.2760993584
Short name	T668
Test name
Test status
Simulation time	29515208602 ps
CPU time	3279.62 seconds
Started	Aug 29 06:27:17 AM UTC 24
Finished	Aug 29 07:22:33 AM UTC 24
Peak memory	1866016 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760993584 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_and_output.2760993584 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/12.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/12.kmac_sideload.1195993433
Short name	T307
Test name
Test status
Simulation time	64585437508 ps
CPU time	415.86 seconds
Started	Aug 29 06:27:31 AM UTC 24
Finished	Aug 29 06:34:33 AM UTC 24
Peak memory	526576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195993433 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.1195993433 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/12.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/12.kmac_smoke.2618587768
Short name	T197
Test name
Test status
Simulation time	9914520275 ps
CPU time	49.75 seconds
Started	Aug 29 06:27:15 AM UTC 24
Finished	Aug 29 06:28:06 AM UTC 24
Peak memory	235776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618587768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.2618587768 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/12.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/12.kmac_stress_all.3614653212
Short name	T378
Test name
Test status
Simulation time	12790961999 ps
CPU time	991.01 seconds
Started	Aug 29 06:28:13 AM UTC 24
Finished	Aug 29 06:44:55 AM UTC 24
Peak memory	535184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614653212 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.3614653212 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/12.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/13.kmac_alert_test.3712996532
Short name	T271
Test name
Test status
Simulation time	24898571 ps
CPU time	1.36 seconds
Started	Aug 29 06:29:34 AM UTC 24
Finished	Aug 29 06:29:36 AM UTC 24
Peak memory	226292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712996532 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.3712996532 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/13.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/13.kmac_app.2238164188
Short name	T295
Test name
Test status
Simulation time	16805996666 ps
CPU time	244.09 seconds
Started	Aug 29 06:28:33 AM UTC 24
Finished	Aug 29 06:32:41 AM UTC 24
Peak memory	395508 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238164188 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.2238164188 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/13.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/13.kmac_burst_write.955178908
Short name	T329
Test name
Test status
Simulation time	22879241780 ps
CPU time	474.52 seconds
Started	Aug 29 06:28:28 AM UTC 24
Finished	Aug 29 06:36:29 AM UTC 24
Peak memory	241964 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955178908 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.955178908 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/13.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/13.kmac_edn_timeout_error.78217405
Short name	T275
Test name
Test status
Simulation time	1025755063 ps
CPU time	38.86 seconds
Started	Aug 29 06:29:19 AM UTC 24
Finished	Aug 29 06:30:00 AM UTC 24
Peak memory	235496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78217405 -assert nopostproc +UVM_TESTNAME=kmac_base_test + UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/k mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.78217405 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/13.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/13.kmac_entropy_mode_error.1705374098
Short name	T270
Test name
Test status
Simulation time	15786121 ps
CPU time	1.29 seconds
Started	Aug 29 06:29:30 AM UTC 24
Finished	Aug 29 06:29:33 AM UTC 24
Peak memory	224784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705374098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.1705374098 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/13.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/13.kmac_entropy_refresh.352390348
Short name	T264
Test name
Test status
Simulation time	1236511560 ps
CPU time	7.6 seconds
Started	Aug 29 06:28:45 AM UTC 24
Finished	Aug 29 06:28:54 AM UTC 24
Peak memory	231928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352390348 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.352390348 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/13.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/13.kmac_error.1932112126
Short name	T198
Test name
Test status
Simulation time	5443364975 ps
CPU time	139.29 seconds
Started	Aug 29 06:28:54 AM UTC 24
Finished	Aug 29 06:31:16 AM UTC 24
Peak memory	348412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932112126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.1932112126 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/13.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/13.kmac_key_error.3794621531
Short name	T266
Test name
Test status
Simulation time	8875179354 ps
CPU time	22.39 seconds
Started	Aug 29 06:29:06 AM UTC 24
Finished	Aug 29 06:29:30 AM UTC 24
Peak memory	229664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794621531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.3794621531 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/13.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/13.kmac_long_msg_and_output.3071715716
Short name	T552
Test name
Test status
Simulation time	249205623244 ps
CPU time	2290.5 seconds
Started	Aug 29 06:28:18 AM UTC 24
Finished	Aug 29 07:06:55 AM UTC 24
Peak memory	2455848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071715716 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_and_output.3071715716 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/13.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/13.kmac_sideload.1832016363
Short name	T322
Test name
Test status
Simulation time	24141789881 ps
CPU time	439.08 seconds
Started	Aug 29 06:28:26 AM UTC 24
Finished	Aug 29 06:35:51 AM UTC 24
Peak memory	540912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832016363 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.1832016363 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/13.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/13.kmac_smoke.3404328900
Short name	T268
Test name
Test status
Simulation time	16835943013 ps
CPU time	74.22 seconds
Started	Aug 29 06:28:16 AM UTC 24
Finished	Aug 29 06:29:32 AM UTC 24
Peak memory	235884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404328900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.3404328900 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/13.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/13.kmac_stress_all.2184410018
Short name	T428
Test name
Test status
Simulation time	121342527381 ps
CPU time	1385.81 seconds
Started	Aug 29 06:29:33 AM UTC 24
Finished	Aug 29 06:52:55 AM UTC 24
Peak memory	985788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184410018 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.2184410018 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/13.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/14.kmac_alert_test.3526496335
Short name	T282
Test name
Test status
Simulation time	181113125 ps
CPU time	1.31 seconds
Started	Aug 29 06:30:15 AM UTC 24
Finished	Aug 29 06:30:17 AM UTC 24
Peak memory	225812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526496335 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.3526496335 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/14.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/14.kmac_app.4220250500
Short name	T309
Test name
Test status
Simulation time	121131941569 ps
CPU time	291.17 seconds
Started	Aug 29 06:29:42 AM UTC 24
Finished	Aug 29 06:34:38 AM UTC 24
Peak memory	446768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220250500 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.4220250500 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/14.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/14.kmac_burst_write.1981050182
Short name	T160
Test name
Test status
Simulation time	6620351100 ps
CPU time	154.52 seconds
Started	Aug 29 06:29:38 AM UTC 24
Finished	Aug 29 06:32:15 AM UTC 24
Peak memory	235824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981050182 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.1981050182 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/14.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/14.kmac_edn_timeout_error.1670933971
Short name	T277
Test name
Test status
Simulation time	77761553 ps
CPU time	1.46 seconds
Started	Aug 29 06:30:02 AM UTC 24
Finished	Aug 29 06:30:05 AM UTC 24
Peak memory	227432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670933971 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.1670933971 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/14.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/14.kmac_entropy_mode_error.3005130805
Short name	T278
Test name
Test status
Simulation time	40265970 ps
CPU time	1.61 seconds
Started	Aug 29 06:30:05 AM UTC 24
Finished	Aug 29 06:30:08 AM UTC 24
Peak memory	227452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005130805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.3005130805 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/14.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/14.kmac_entropy_refresh.2690482083
Short name	T343
Test name
Test status
Simulation time	7929689329 ps
CPU time	495.36 seconds
Started	Aug 29 06:29:43 AM UTC 24
Finished	Aug 29 06:38:06 AM UTC 24
Peak memory	356628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690482083 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.2690482083 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/14.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/14.kmac_error.1348722171
Short name	T288
Test name
Test status
Simulation time	1150557072 ps
CPU time	111.4 seconds
Started	Aug 29 06:29:53 AM UTC 24
Finished	Aug 29 06:31:47 AM UTC 24
Peak memory	268480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348722171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.1348722171 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/14.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/14.kmac_key_error.3639885467
Short name	T281
Test name
Test status
Simulation time	923219061 ps
CPU time	12.48 seconds
Started	Aug 29 06:30:00 AM UTC 24
Finished	Aug 29 06:30:14 AM UTC 24
Peak memory	227508 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639885467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.3639885467 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/14.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/14.kmac_lc_escalation.2389603371
Short name	T279
Test name
Test status
Simulation time	40338557 ps
CPU time	2.25 seconds
Started	Aug 29 06:30:09 AM UTC 24
Finished	Aug 29 06:30:13 AM UTC 24
Peak memory	233804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389603371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.2389603371 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/14.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/14.kmac_long_msg_and_output.2037509035
Short name	T682
Test name
Test status
Simulation time	65079380957 ps
CPU time	3438.39 seconds
Started	Aug 29 06:29:36 AM UTC 24
Finished	Aug 29 07:27:35 AM UTC 24
Peak memory	1806632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037509035 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_and_output.2037509035 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/14.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/14.kmac_sideload.1496388197
Short name	T302
Test name
Test status
Simulation time	31132196351 ps
CPU time	211.49 seconds
Started	Aug 29 06:29:37 AM UTC 24
Finished	Aug 29 06:33:12 AM UTC 24
Peak memory	393464 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496388197 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.1496388197 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/14.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/14.kmac_smoke.3039909277
Short name	T273
Test name
Test status
Simulation time	860416880 ps
CPU time	7.57 seconds
Started	Aug 29 06:29:34 AM UTC 24
Finished	Aug 29 06:29:42 AM UTC 24
Peak memory	235460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039909277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.3039909277 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/14.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/14.kmac_stress_all.1678567139
Short name	T387
Test name
Test status
Simulation time	298595843892 ps
CPU time	926.53 seconds
Started	Aug 29 06:30:14 AM UTC 24
Finished	Aug 29 06:45:52 AM UTC 24
Peak memory	1214756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678567139 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.1678567139 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/14.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/15.kmac_alert_test.2844157794
Short name	T291
Test name
Test status
Simulation time	13947672 ps
CPU time	1.25 seconds
Started	Aug 29 06:31:55 AM UTC 24
Finished	Aug 29 06:31:57 AM UTC 24
Peak memory	226292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844157794 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.2844157794 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/15.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/15.kmac_app.1866323411
Short name	T315
Test name
Test status
Simulation time	8355616975 ps
CPU time	261.82 seconds
Started	Aug 29 06:30:23 AM UTC 24
Finished	Aug 29 06:34:49 AM UTC 24
Peak memory	409932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866323411 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.1866323411 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/15.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/15.kmac_burst_write.1567706887
Short name	T407
Test name
Test status
Simulation time	73655169415 ps
CPU time	1127.89 seconds
Started	Aug 29 06:30:19 AM UTC 24
Finished	Aug 29 06:49:21 AM UTC 24
Peak memory	262380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567706887 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.1567706887 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/15.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/15.kmac_edn_timeout_error.157133647
Short name	T290
Test name
Test status
Simulation time	1536682516 ps
CPU time	13.17 seconds
Started	Aug 29 06:31:40 AM UTC 24
Finished	Aug 29 06:31:54 AM UTC 24
Peak memory	235504 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157133647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.157133647 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/15.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/15.kmac_entropy_mode_error.2500831353
Short name	T289
Test name
Test status
Simulation time	49612572 ps
CPU time	1.55 seconds
Started	Aug 29 06:31:48 AM UTC 24
Finished	Aug 29 06:31:50 AM UTC 24
Peak memory	224784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500831353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.2500831353 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/15.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/15.kmac_error.2583339250
Short name	T296
Test name
Test status
Simulation time	5182426681 ps
CPU time	95.63 seconds
Started	Aug 29 06:31:17 AM UTC 24
Finished	Aug 29 06:32:55 AM UTC 24
Peak memory	295224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583339250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.2583339250 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/15.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/15.kmac_key_error.3865575700
Short name	T287
Test name
Test status
Simulation time	1047489782 ps
CPU time	4.85 seconds
Started	Aug 29 06:31:33 AM UTC 24
Finished	Aug 29 06:31:38 AM UTC 24
Peak memory	227512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865575700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.3865575700 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/15.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/15.kmac_lc_escalation.139499181
Short name	T69
Test name
Test status
Simulation time	88475390 ps
CPU time	2.12 seconds
Started	Aug 29 06:31:51 AM UTC 24
Finished	Aug 29 06:31:54 AM UTC 24
Peak memory	231732 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139499181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.139499181 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/15.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/15.kmac_long_msg_and_output.3385199695
Short name	T293
Test name
Test status
Simulation time	2429904946 ps
CPU time	118.42 seconds
Started	Aug 29 06:30:15 AM UTC 24
Finished	Aug 29 06:32:16 AM UTC 24
Peak memory	327884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385199695 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_and_output.3385199695 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/15.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/15.kmac_sideload.1005428723
Short name	T301
Test name
Test status
Simulation time	3891874051 ps
CPU time	170.09 seconds
Started	Aug 29 06:30:18 AM UTC 24
Finished	Aug 29 06:33:11 AM UTC 24
Peak memory	282932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005428723 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.1005428723 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/15.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/15.kmac_smoke.4021579480
Short name	T286
Test name
Test status
Simulation time	2883011543 ps
CPU time	74.62 seconds
Started	Aug 29 06:30:15 AM UTC 24
Finished	Aug 29 06:31:32 AM UTC 24
Peak memory	235776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021579480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.4021579480 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/15.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/15.kmac_stress_all.4200559986
Short name	T425
Test name
Test status
Simulation time	38508315239 ps
CPU time	1212.54 seconds
Started	Aug 29 06:31:55 AM UTC 24
Finished	Aug 29 06:52:21 AM UTC 24
Peak memory	1409332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200559986 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.4200559986 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/15.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/16.kmac_alert_test.164837043
Short name	T300
Test name
Test status
Simulation time	108220176 ps
CPU time	1.02 seconds
Started	Aug 29 06:33:06 AM UTC 24
Finished	Aug 29 06:33:08 AM UTC 24
Peak memory	227556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164837043 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.164837043 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/16.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/16.kmac_app.2092312563
Short name	T303
Test name
Test status
Simulation time	1949618383 ps
CPU time	72.23 seconds
Started	Aug 29 06:32:28 AM UTC 24
Finished	Aug 29 06:33:42 AM UTC 24
Peak memory	250100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092312563 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.2092312563 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/16.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/16.kmac_burst_write.569033064
Short name	T395
Test name
Test status
Simulation time	7734804107 ps
CPU time	866.34 seconds
Started	Aug 29 06:32:17 AM UTC 24
Finished	Aug 29 06:46:55 AM UTC 24
Peak memory	248044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569033064 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.569033064 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/16.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/16.kmac_edn_timeout_error.2834073643
Short name	T297
Test name
Test status
Simulation time	89163155 ps
CPU time	1.54 seconds
Started	Aug 29 06:32:56 AM UTC 24
Finished	Aug 29 06:32:58 AM UTC 24
Peak memory	227372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834073643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.2834073643 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/16.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/16.kmac_entropy_mode_error.2523367919
Short name	T298
Test name
Test status
Simulation time	76584709 ps
CPU time	1.57 seconds
Started	Aug 29 06:32:59 AM UTC 24
Finished	Aug 29 06:33:01 AM UTC 24
Peak memory	227452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523367919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.2523367919 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/16.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/16.kmac_entropy_refresh.1400972483
Short name	T308
Test name
Test status
Simulation time	3593793079 ps
CPU time	120.54 seconds
Started	Aug 29 06:32:32 AM UTC 24
Finished	Aug 29 06:34:35 AM UTC 24
Peak memory	291144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400972483 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.1400972483 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/16.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/16.kmac_error.724905335
Short name	T342
Test name
Test status
Simulation time	21930720750 ps
CPU time	320.6 seconds
Started	Aug 29 06:32:39 AM UTC 24
Finished	Aug 29 06:38:04 AM UTC 24
Peak memory	450816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724905335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.724905335 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/16.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/16.kmac_key_error.2281041238
Short name	T299
Test name
Test status
Simulation time	7471961687 ps
CPU time	22.24 seconds
Started	Aug 29 06:32:42 AM UTC 24
Finished	Aug 29 06:33:05 AM UTC 24
Peak memory	229604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281041238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.2281041238 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/16.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/16.kmac_long_msg_and_output.3531901391
Short name	T456
Test name
Test status
Simulation time	131955818949 ps
CPU time	1395.13 seconds
Started	Aug 29 06:32:06 AM UTC 24
Finished	Aug 29 06:55:38 AM UTC 24
Peak memory	1665328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531901391 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_and_output.3531901391 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/16.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/16.kmac_sideload.3735357788
Short name	T310
Test name
Test status
Simulation time	12796844497 ps
CPU time	139.45 seconds
Started	Aug 29 06:32:16 AM UTC 24
Finished	Aug 29 06:34:38 AM UTC 24
Peak memory	327928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735357788 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.3735357788 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/16.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/16.kmac_smoke.558788146
Short name	T294
Test name
Test status
Simulation time	1154862556 ps
CPU time	37.73 seconds
Started	Aug 29 06:31:58 AM UTC 24
Finished	Aug 29 06:32:37 AM UTC 24
Peak memory	235836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558788146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.558788146 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/16.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/16.kmac_stress_all.1116185851
Short name	T353
Test name
Test status
Simulation time	14268666596 ps
CPU time	403.87 seconds
Started	Aug 29 06:33:06 AM UTC 24
Finished	Aug 29 06:39:55 AM UTC 24
Peak memory	283264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116185851 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.1116185851 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/16.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/17.kmac_alert_test.4142058953
Short name	T314
Test name
Test status
Simulation time	13828733 ps
CPU time	1.25 seconds
Started	Aug 29 06:34:43 AM UTC 24
Finished	Aug 29 06:34:46 AM UTC 24
Peak memory	226640 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142058953 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.4142058953 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/17.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/17.kmac_app.600121765
Short name	T364
Test name
Test status
Simulation time	77633514196 ps
CPU time	518.27 seconds
Started	Aug 29 06:33:56 AM UTC 24
Finished	Aug 29 06:42:42 AM UTC 24
Peak memory	479540 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600121765 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.600121765 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/17.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/17.kmac_burst_write.4073285024
Short name	T408
Test name
Test status
Simulation time	23038375376 ps
CPU time	943.63 seconds
Started	Aug 29 06:33:43 AM UTC 24
Finished	Aug 29 06:49:39 AM UTC 24
Peak memory	258348 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073285024 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.4073285024 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/17.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/17.kmac_edn_timeout_error.1945035427
Short name	T318
Test name
Test status
Simulation time	1071192327 ps
CPU time	29.81 seconds
Started	Aug 29 06:34:36 AM UTC 24
Finished	Aug 29 06:35:07 AM UTC 24
Peak memory	233668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945035427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.1945035427 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/17.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/17.kmac_entropy_mode_error.1505063279
Short name	T311
Test name
Test status
Simulation time	83350470 ps
CPU time	1.57 seconds
Started	Aug 29 06:34:38 AM UTC 24
Finished	Aug 29 06:34:40 AM UTC 24
Peak memory	224424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505063279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.1505063279 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/17.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/17.kmac_entropy_refresh.4003302372
Short name	T346
Test name
Test status
Simulation time	30135723271 ps
CPU time	247.66 seconds
Started	Aug 29 06:34:23 AM UTC 24
Finished	Aug 29 06:38:35 AM UTC 24
Peak memory	340248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003302372 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.4003302372 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/17.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/17.kmac_error.1659385448
Short name	T324
Test name
Test status
Simulation time	2139799588 ps
CPU time	78.51 seconds
Started	Aug 29 06:34:34 AM UTC 24
Finished	Aug 29 06:35:54 AM UTC 24
Peak memory	295228 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659385448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.1659385448 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/17.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/17.kmac_key_error.952972540
Short name	T313
Test name
Test status
Simulation time	1808473406 ps
CPU time	7.3 seconds
Started	Aug 29 06:34:34 AM UTC 24
Finished	Aug 29 06:34:42 AM UTC 24
Peak memory	229572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952972540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.952972540 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/17.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/17.kmac_lc_escalation.3614130947
Short name	T312
Test name
Test status
Simulation time	120597619 ps
CPU time	1.94 seconds
Started	Aug 29 06:34:39 AM UTC 24
Finished	Aug 29 06:34:42 AM UTC 24
Peak memory	231304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614130947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.3614130947 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/17.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/17.kmac_long_msg_and_output.2811834091
Short name	T357
Test name
Test status
Simulation time	10942876321 ps
CPU time	468.39 seconds
Started	Aug 29 06:33:12 AM UTC 24
Finished	Aug 29 06:41:07 AM UTC 24
Peak memory	657648 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811834091 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_and_output.2811834091 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/17.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/17.kmac_sideload.2165934325
Short name	T305
Test name
Test status
Simulation time	14863763497 ps
CPU time	67.72 seconds
Started	Aug 29 06:33:12 AM UTC 24
Finished	Aug 29 06:34:22 AM UTC 24
Peak memory	268600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165934325 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.2165934325 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/17.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/17.kmac_smoke.2063971784
Short name	T306
Test name
Test status
Simulation time	2694608232 ps
CPU time	81.43 seconds
Started	Aug 29 06:33:09 AM UTC 24
Finished	Aug 29 06:34:32 AM UTC 24
Peak memory	234128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063971784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.2063971784 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/17.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/17.kmac_stress_all.2673140684
Short name	T344
Test name
Test status
Simulation time	4073067233 ps
CPU time	215.43 seconds
Started	Aug 29 06:34:41 AM UTC 24
Finished	Aug 29 06:38:20 AM UTC 24
Peak memory	301360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673140684 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.2673140684 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/17.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/18.kmac_alert_test.1035766238
Short name	T325
Test name
Test status
Simulation time	30773573 ps
CPU time	1.21 seconds
Started	Aug 29 06:35:54 AM UTC 24
Finished	Aug 29 06:35:57 AM UTC 24
Peak memory	226292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035766238 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.1035766238 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/18.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/18.kmac_app.779943738
Short name	T331
Test name
Test status
Simulation time	1313825726 ps
CPU time	88.62 seconds
Started	Aug 29 06:35:05 AM UTC 24
Finished	Aug 29 06:36:35 AM UTC 24
Peak memory	262368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779943738 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.779943738 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/18.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/18.kmac_burst_write.2750565852
Short name	T391
Test name
Test status
Simulation time	10640856511 ps
CPU time	692.17 seconds
Started	Aug 29 06:34:59 AM UTC 24
Finished	Aug 29 06:46:41 AM UTC 24
Peak memory	252276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750565852 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.2750565852 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/18.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/18.kmac_edn_timeout_error.833907227
Short name	T330
Test name
Test status
Simulation time	1657731186 ps
CPU time	42.47 seconds
Started	Aug 29 06:35:48 AM UTC 24
Finished	Aug 29 06:36:32 AM UTC 24
Peak memory	235168 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833907227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.833907227 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/18.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/18.kmac_entropy_mode_error.2222585284
Short name	T321
Test name
Test status
Simulation time	23065330 ps
CPU time	1.46 seconds
Started	Aug 29 06:35:48 AM UTC 24
Finished	Aug 29 06:35:50 AM UTC 24
Peak memory	224424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222585284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.2222585284 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/18.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/18.kmac_entropy_refresh.4035657666
Short name	T340
Test name
Test status
Simulation time	4922257825 ps
CPU time	161.66 seconds
Started	Aug 29 06:35:05 AM UTC 24
Finished	Aug 29 06:37:49 AM UTC 24
Peak memory	280884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035657666 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.4035657666 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/18.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/18.kmac_error.3117566504
Short name	T328
Test name
Test status
Simulation time	2210706227 ps
CPU time	76.21 seconds
Started	Aug 29 06:35:08 AM UTC 24
Finished	Aug 29 06:36:26 AM UTC 24
Peak memory	278780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117566504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.3117566504 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/18.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/18.kmac_key_error.2393538477
Short name	T320
Test name
Test status
Simulation time	1426944265 ps
CPU time	17.51 seconds
Started	Aug 29 06:35:29 AM UTC 24
Finished	Aug 29 06:35:48 AM UTC 24
Peak memory	227512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393538477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.2393538477 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/18.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/18.kmac_long_msg_and_output.905964866
Short name	T504
Test name
Test status
Simulation time	180326536450 ps
CPU time	1520.45 seconds
Started	Aug 29 06:34:46 AM UTC 24
Finished	Aug 29 07:00:24 AM UTC 24
Peak memory	1827116 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905964866 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_and_output.905964866 +enable_masking= 1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/18.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/18.kmac_sideload.4089815869
Short name	T317
Test name
Test status
Simulation time	496091961 ps
CPU time	12.85 seconds
Started	Aug 29 06:34:49 AM UTC 24
Finished	Aug 29 06:35:04 AM UTC 24
Peak memory	235052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089815869 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.4089815869 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/18.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/18.kmac_smoke.3728574392
Short name	T319
Test name
Test status
Simulation time	1253090977 ps
CPU time	43.38 seconds
Started	Aug 29 06:34:43 AM UTC 24
Finished	Aug 29 06:35:28 AM UTC 24
Peak memory	235720 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728574392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.3728574392 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/18.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/18.kmac_stress_all.3289970616
Short name	T360
Test name
Test status
Simulation time	11332959570 ps
CPU time	331.04 seconds
Started	Aug 29 06:35:52 AM UTC 24
Finished	Aug 29 06:41:28 AM UTC 24
Peak memory	375228 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289970616 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.3289970616 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/18.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/19.kmac_alert_test.1559108087
Short name	T336
Test name
Test status
Simulation time	16410434 ps
CPU time	1.3 seconds
Started	Aug 29 06:36:53 AM UTC 24
Finished	Aug 29 06:36:56 AM UTC 24
Peak memory	224492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559108087 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.1559108087 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/19.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/19.kmac_app.1941745950
Short name	T355
Test name
Test status
Simulation time	114788496415 ps
CPU time	266.65 seconds
Started	Aug 29 06:36:10 AM UTC 24
Finished	Aug 29 06:40:40 AM UTC 24
Peak memory	450864 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941745950 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.1941745950 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/19.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/19.kmac_burst_write.1879686369
Short name	T455
Test name
Test status
Simulation time	46740615821 ps
CPU time	1152.59 seconds
Started	Aug 29 06:36:06 AM UTC 24
Finished	Aug 29 06:55:32 AM UTC 24
Peak memory	262440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879686369 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.1879686369 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/19.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/19.kmac_edn_timeout_error.3077503691
Short name	T332
Test name
Test status
Simulation time	144503949 ps
CPU time	1.47 seconds
Started	Aug 29 06:36:36 AM UTC 24
Finished	Aug 29 06:36:39 AM UTC 24
Peak memory	227452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077503691 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.3077503691 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/19.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/19.kmac_entropy_mode_error.884278913
Short name	T333
Test name
Test status
Simulation time	13905544 ps
CPU time	1.35 seconds
Started	Aug 29 06:36:40 AM UTC 24
Finished	Aug 29 06:36:42 AM UTC 24
Peak memory	225276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884278913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.884278913 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/19.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/19.kmac_entropy_refresh.708666288
Short name	T354
Test name
Test status
Simulation time	4144898429 ps
CPU time	231.75 seconds
Started	Aug 29 06:36:27 AM UTC 24
Finished	Aug 29 06:40:23 AM UTC 24
Peak memory	291140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708666288 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.708666288 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/19.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/19.kmac_error.4030492027
Short name	T338
Test name
Test status
Simulation time	1525922261 ps
CPU time	74.66 seconds
Started	Aug 29 06:36:30 AM UTC 24
Finished	Aug 29 06:37:47 AM UTC 24
Peak memory	262336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030492027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.4030492027 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/19.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/19.kmac_key_error.2819436959
Short name	T335
Test name
Test status
Simulation time	3734683290 ps
CPU time	18.23 seconds
Started	Aug 29 06:36:33 AM UTC 24
Finished	Aug 29 06:36:53 AM UTC 24
Peak memory	229812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819436959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.2819436959 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/19.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/19.kmac_lc_escalation.4269352820
Short name	T334
Test name
Test status
Simulation time	40752031 ps
CPU time	2.18 seconds
Started	Aug 29 06:36:43 AM UTC 24
Finished	Aug 29 06:36:46 AM UTC 24
Peak memory	231788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269352820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.4269352820 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/19.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/19.kmac_long_msg_and_output.1777822715
Short name	T393
Test name
Test status
Simulation time	5088956707 ps
CPU time	639.16 seconds
Started	Aug 29 06:35:55 AM UTC 24
Finished	Aug 29 06:46:43 AM UTC 24
Peak memory	518444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777822715 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_and_output.1777822715 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/19.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/19.kmac_sideload.568815568
Short name	T326
Test name
Test status
Simulation time	468623691 ps
CPU time	6.22 seconds
Started	Aug 29 06:35:58 AM UTC 24
Finished	Aug 29 06:36:05 AM UTC 24
Peak memory	235720 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568815568 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.568815568 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/19.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/19.kmac_smoke.181235541
Short name	T337
Test name
Test status
Simulation time	39755198598 ps
CPU time	70.62 seconds
Started	Aug 29 06:35:55 AM UTC 24
Finished	Aug 29 06:37:08 AM UTC 24
Peak memory	235824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181235541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.181235541 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/19.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/19.kmac_stress_all.690452935
Short name	T483
Test name
Test status
Simulation time	57084622007 ps
CPU time	1288.25 seconds
Started	Aug 29 06:36:47 AM UTC 24
Finished	Aug 29 06:58:31 AM UTC 24
Peak memory	567992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690452935 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.690452935 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/19.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/2.kmac_alert_test.1901688339
Short name	T127
Test name
Test status
Simulation time	23617889 ps
CPU time	1.35 seconds
Started	Aug 29 06:18:52 AM UTC 24
Finished	Aug 29 06:18:54 AM UTC 24
Peak memory	226696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901688339 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.1901688339 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/2.kmac_app.3004587607
Short name	T182
Test name
Test status
Simulation time	14089741771 ps
CPU time	218.04 seconds
Started	Aug 29 06:18:50 AM UTC 24
Finished	Aug 29 06:22:32 AM UTC 24
Peak memory	350516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004587607 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.3004587607 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/2.kmac_app_with_partial_data.3242982597
Short name	T149
Test name
Test status
Simulation time	12146322791 ps
CPU time	246.16 seconds
Started	Aug 29 06:18:50 AM UTC 24
Finished	Aug 29 06:23:00 AM UTC 24
Peak memory	430312 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242982597 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.3242982597 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_app_with_partial_data/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/2.kmac_burst_write.567353018
Short name	T367
Test name
Test status
Simulation time	102418999176 ps
CPU time	1439.96 seconds
Started	Aug 29 06:18:49 AM UTC 24
Finished	Aug 29 06:43:06 AM UTC 24
Peak memory	268556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567353018 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.567353018 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/2.kmac_edn_timeout_error.3395455019
Short name	T21
Test name
Test status
Simulation time	195442585 ps
CPU time	13.01 seconds
Started	Aug 29 06:18:50 AM UTC 24
Finished	Aug 29 06:19:05 AM UTC 24
Peak memory	235476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395455019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.3395455019 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_mode_error.2811776222
Short name	T61
Test name
Test status
Simulation time	49167170 ps
CPU time	1.74 seconds
Started	Aug 29 06:18:50 AM UTC 24
Finished	Aug 29 06:18:53 AM UTC 24
Peak memory	227452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811776222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.2811776222 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_refresh.429998337
Short name	T96
Test name
Test status
Simulation time	61935118499 ps
CPU time	336.36 seconds
Started	Aug 29 06:18:50 AM UTC 24
Finished	Aug 29 06:24:31 AM UTC 24
Peak memory	469276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429998337 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.429998337 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/2.kmac_error.1228984314
Short name	T25
Test name
Test status
Simulation time	7588447460 ps
CPU time	169.21 seconds
Started	Aug 29 06:18:50 AM UTC 24
Finished	Aug 29 06:21:43 AM UTC 24
Peak memory	301372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228984314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.1228984314 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/2.kmac_key_error.4079210464
Short name	T8
Test name
Test status
Simulation time	1075584253 ps
CPU time	4.79 seconds
Started	Aug 29 06:18:50 AM UTC 24
Finished	Aug 29 06:18:56 AM UTC 24
Peak memory	227560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079210464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.4079210464 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/2.kmac_long_msg_and_output.184643841
Short name	T569
Test name
Test status
Simulation time	268841982513 ps
CPU time	2970.84 seconds
Started	Aug 29 06:18:48 AM UTC 24
Finished	Aug 29 07:08:51 AM UTC 24
Peak memory	2990424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184643841 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and_output.184643841 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/2.kmac_mubi.2318088623
Short name	T81
Test name
Test status
Simulation time	49461983889 ps
CPU time	430.6 seconds
Started	Aug 29 06:18:50 AM UTC 24
Finished	Aug 29 06:26:07 AM UTC 24
Peak memory	522884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318088623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.2318088623 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/2.kmac_sec_cm.3134870064
Short name	T44
Test name
Test status
Simulation time	17644381468 ps
CPU time	82.78 seconds
Started	Aug 29 06:18:52 AM UTC 24
Finished	Aug 29 06:20:17 AM UTC 24
Peak memory	294460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134870064 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.3134870064 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/2.kmac_sideload.2192070505
Short name	T237
Test name
Test status
Simulation time	21972073236 ps
CPU time	420.66 seconds
Started	Aug 29 06:18:49 AM UTC 24
Finished	Aug 29 06:25:55 AM UTC 24
Peak memory	385384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192070505 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.2192070505 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/2.kmac_smoke.966145751
Short name	T130
Test name
Test status
Simulation time	5450579289 ps
CPU time	56.49 seconds
Started	Aug 29 06:18:46 AM UTC 24
Finished	Aug 29 06:19:45 AM UTC 24
Peak memory	235840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966145751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.966145751 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/2.kmac_stress_all.2618228099
Short name	T158
Test name
Test status
Simulation time	6089361330 ps
CPU time	318.15 seconds
Started	Aug 29 06:18:51 AM UTC 24
Finished	Aug 29 06:24:13 AM UTC 24
Peak memory	252156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618228099 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.2618228099 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac.1298438274
Short name	T62
Test name
Test status
Simulation time	264152230 ps
CPU time	3.39 seconds
Started	Aug 29 06:18:50 AM UTC 24
Finished	Aug 29 06:18:55 AM UTC 24
Peak memory	229828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298438274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac.1298438274 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_test_vectors_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac_xof.2945930307
Short name	T63
Test name
Test status
Simulation time	597856268 ps
CPU time	4.23 seconds
Started	Aug 29 06:18:50 AM UTC 24
Finished	Aug 29 06:18:55 AM UTC 24
Peak memory	235716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945930307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.2945930307 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_test_vectors_kmac_xof/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_224.3495248034
Short name	T516
Test name
Test status
Simulation time	323455289254 ps
CPU time	2595.96 seconds
Started	Aug 29 06:18:49 AM UTC 24
Finished	Aug 29 07:02:33 AM UTC 24
Peak memory	3168468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495248034 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.3495248034 +enab le_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_224/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_256.992808788
Short name	T64
Test name
Test status
Simulation time	22362440100 ps
CPU time	42.3 seconds
Started	Aug 29 06:18:49 AM UTC 24
Finished	Aug 29 06:19:33 AM UTC 24
Peak memory	256192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992808788 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.992808788 +enable _masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_256/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_384.1914508614
Short name	T363
Test name
Test status
Simulation time	98038602482 ps
CPU time	1415.15 seconds
Started	Aug 29 06:18:49 AM UTC 24
Finished	Aug 29 06:42:40 AM UTC 24
Peak memory	944272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914508614 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.1914508614 +enab le_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_384/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_512.4109835736
Short name	T114
Test name
Test status
Simulation time	3856073789 ps
CPU time	25.82 seconds
Started	Aug 29 06:18:49 AM UTC 24
Finished	Aug 29 06:19:16 AM UTC 24
Peak memory	233868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109835736 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.4109835736 +enab le_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_512/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_128.1816545213
Short name	T147
Test name
Test status
Simulation time	38304311026 ps
CPU time	244.53 seconds
Started	Aug 29 06:18:49 AM UTC 24
Finished	Aug 29 06:22:57 AM UTC 24
Peak memory	444664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816545213 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.1816545213 +e nable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_128/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_256.2917046547
Short name	T449
Test name
Test status
Simulation time	75066212973 ps
CPU time	2159.88 seconds
Started	Aug 29 06:18:49 AM UTC 24
Finished	Aug 29 06:55:15 AM UTC 24
Peak memory	1142944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917046547 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.2917046547 +e nable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_256/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/20.kmac_alert_test.2334402507
Short name	T349
Test name
Test status
Simulation time	171734511 ps
CPU time	1.46 seconds
Started	Aug 29 06:38:37 AM UTC 24
Finished	Aug 29 06:38:40 AM UTC 24
Peak memory	226052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334402507 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.2334402507 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/20.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/20.kmac_app.637569778
Short name	T365
Test name
Test status
Simulation time	19003881205 ps
CPU time	278.91 seconds
Started	Aug 29 06:38:00 AM UTC 24
Finished	Aug 29 06:42:43 AM UTC 24
Peak memory	305460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637569778 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.637569778 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/20.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/20.kmac_burst_write.2332787190
Short name	T522
Test name
Test status
Simulation time	29553439246 ps
CPU time	1538.08 seconds
Started	Aug 29 06:37:51 AM UTC 24
Finished	Aug 29 07:03:47 AM UTC 24
Peak memory	270576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332787190 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.2332787190 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/20.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/20.kmac_entropy_refresh.3460424243
Short name	T368
Test name
Test status
Simulation time	6718963020 ps
CPU time	297.06 seconds
Started	Aug 29 06:38:05 AM UTC 24
Finished	Aug 29 06:43:07 AM UTC 24
Peak memory	303408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460424243 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.3460424243 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/20.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/20.kmac_error.1479883229
Short name	T345
Test name
Test status
Simulation time	646193829 ps
CPU time	23.58 seconds
Started	Aug 29 06:38:07 AM UTC 24
Finished	Aug 29 06:38:32 AM UTC 24
Peak memory	252276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479883229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.1479883229 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/20.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/20.kmac_key_error.3225817573
Short name	T348
Test name
Test status
Simulation time	1267676582 ps
CPU time	17.18 seconds
Started	Aug 29 06:38:21 AM UTC 24
Finished	Aug 29 06:38:40 AM UTC 24
Peak memory	229624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225817573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.3225817573 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/20.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/20.kmac_lc_escalation.904780704
Short name	T347
Test name
Test status
Simulation time	39198582 ps
CPU time	2.13 seconds
Started	Aug 29 06:38:33 AM UTC 24
Finished	Aug 29 06:38:36 AM UTC 24
Peak memory	231820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904780704 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.904780704 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/20.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/20.kmac_long_msg_and_output.2804597407
Short name	T693
Test name
Test status
Simulation time	137335618215 ps
CPU time	3331.41 seconds
Started	Aug 29 06:37:08 AM UTC 24
Finished	Aug 29 07:33:18 AM UTC 24
Peak memory	3254480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804597407 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_and_output.2804597407 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/20.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/20.kmac_sideload.1426485809
Short name	T383
Test name
Test status
Simulation time	11726698188 ps
CPU time	448.39 seconds
Started	Aug 29 06:37:48 AM UTC 24
Finished	Aug 29 06:45:22 AM UTC 24
Peak memory	387372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426485809 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.1426485809 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/20.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/20.kmac_smoke.1921604489
Short name	T350
Test name
Test status
Simulation time	7282177710 ps
CPU time	102.25 seconds
Started	Aug 29 06:36:56 AM UTC 24
Finished	Aug 29 06:38:41 AM UTC 24
Peak memory	234080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921604489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.1921604489 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/20.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/20.kmac_stress_all.2021046718
Short name	T385
Test name
Test status
Simulation time	24080670366 ps
CPU time	411.66 seconds
Started	Aug 29 06:38:35 AM UTC 24
Finished	Aug 29 06:45:33 AM UTC 24
Peak memory	301760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021046718 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.2021046718 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/20.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/21.kmac_alert_test.1093503608
Short name	T359
Test name
Test status
Simulation time	49634720 ps
CPU time	1.22 seconds
Started	Aug 29 06:41:12 AM UTC 24
Finished	Aug 29 06:41:14 AM UTC 24
Peak memory	226292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093503608 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.1093503608 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/21.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/21.kmac_app.3018935747
Short name	T374
Test name
Test status
Simulation time	6735740010 ps
CPU time	304.99 seconds
Started	Aug 29 06:39:16 AM UTC 24
Finished	Aug 29 06:44:25 AM UTC 24
Peak memory	315696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018935747 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.3018935747 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/21.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/21.kmac_burst_write.3758503197
Short name	T372
Test name
Test status
Simulation time	5386848956 ps
CPU time	304.37 seconds
Started	Aug 29 06:38:47 AM UTC 24
Finished	Aug 29 06:43:56 AM UTC 24
Peak memory	241880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758503197 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.3758503197 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/21.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/21.kmac_entropy_refresh.1312710571
Short name	T397
Test name
Test status
Simulation time	6242187461 ps
CPU time	415.77 seconds
Started	Aug 29 06:39:56 AM UTC 24
Finished	Aug 29 06:46:58 AM UTC 24
Peak memory	342328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312710571 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.1312710571 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/21.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/21.kmac_error.2749623228
Short name	T373
Test name
Test status
Simulation time	19826021767 ps
CPU time	229.09 seconds
Started	Aug 29 06:40:23 AM UTC 24
Finished	Aug 29 06:44:16 AM UTC 24
Peak memory	356668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749623228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.2749623228 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/21.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/21.kmac_key_error.795861409
Short name	T356
Test name
Test status
Simulation time	17969255858 ps
CPU time	23.55 seconds
Started	Aug 29 06:40:41 AM UTC 24
Finished	Aug 29 06:41:06 AM UTC 24
Peak memory	229636 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795861409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.795861409 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/21.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/21.kmac_lc_escalation.2401781630
Short name	T358
Test name
Test status
Simulation time	170110756 ps
CPU time	2.12 seconds
Started	Aug 29 06:41:07 AM UTC 24
Finished	Aug 29 06:41:11 AM UTC 24
Peak memory	231756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401781630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.2401781630 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/21.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/21.kmac_long_msg_and_output.2861499619
Short name	T716
Test name
Test status
Simulation time	243089826315 ps
CPU time	5399.86 seconds
Started	Aug 29 06:38:40 AM UTC 24
Finished	Aug 29 08:09:42 AM UTC 24
Peak memory	4522332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861499619 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_and_output.2861499619 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/21.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/21.kmac_sideload.487809706
Short name	T376
Test name
Test status
Simulation time	4262141734 ps
CPU time	355.61 seconds
Started	Aug 29 06:38:42 AM UTC 24
Finished	Aug 29 06:44:42 AM UTC 24
Peak memory	342320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487809706 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.487809706 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/21.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/21.kmac_smoke.3965497760
Short name	T351
Test name
Test status
Simulation time	91668057 ps
CPU time	4.49 seconds
Started	Aug 29 06:38:40 AM UTC 24
Finished	Aug 29 06:38:46 AM UTC 24
Peak memory	231812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965497760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.3965497760 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/21.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/21.kmac_stress_all.3037936633
Short name	T614
Test name
Test status
Simulation time	60865127655 ps
CPU time	1991.12 seconds
Started	Aug 29 06:41:09 AM UTC 24
Finished	Aug 29 07:14:43 AM UTC 24
Peak memory	1458916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037936633 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.3037936633 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/21.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/22.kmac_alert_test.3864459815
Short name	T370
Test name
Test status
Simulation time	50072849 ps
CPU time	1.24 seconds
Started	Aug 29 06:43:11 AM UTC 24
Finished	Aug 29 06:43:13 AM UTC 24
Peak memory	224612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864459815 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.3864459815 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/22.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/22.kmac_app.3536436190
Short name	T394
Test name
Test status
Simulation time	8128687912 ps
CPU time	244.59 seconds
Started	Aug 29 06:42:41 AM UTC 24
Finished	Aug 29 06:46:50 AM UTC 24
Peak memory	295220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536436190 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.3536436190 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/22.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/22.kmac_burst_write.2311244587
Short name	T444
Test name
Test status
Simulation time	54256563151 ps
CPU time	731.58 seconds
Started	Aug 29 06:42:22 AM UTC 24
Finished	Aug 29 06:54:43 AM UTC 24
Peak memory	245996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311244587 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.2311244587 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/22.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/22.kmac_entropy_refresh.4173879678
Short name	T366
Test name
Test status
Simulation time	3399360599 ps
CPU time	20.53 seconds
Started	Aug 29 06:42:43 AM UTC 24
Finished	Aug 29 06:43:05 AM UTC 24
Peak memory	248328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173879678 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.4173879678 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/22.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/22.kmac_error.2325916447
Short name	T409
Test name
Test status
Simulation time	43516976004 ps
CPU time	423.07 seconds
Started	Aug 29 06:42:44 AM UTC 24
Finished	Aug 29 06:49:53 AM UTC 24
Peak memory	479548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325916447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.2325916447 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/22.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/22.kmac_key_error.1364662445
Short name	T371
Test name
Test status
Simulation time	1177812019 ps
CPU time	14.91 seconds
Started	Aug 29 06:43:07 AM UTC 24
Finished	Aug 29 06:43:23 AM UTC 24
Peak memory	229556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364662445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.1364662445 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/22.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/22.kmac_lc_escalation.3293558961
Short name	T369
Test name
Test status
Simulation time	73965830 ps
CPU time	1.82 seconds
Started	Aug 29 06:43:07 AM UTC 24
Finished	Aug 29 06:43:10 AM UTC 24
Peak memory	231308 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293558961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.3293558961 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/22.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/22.kmac_long_msg_and_output.1367188061
Short name	T695
Test name
Test status
Simulation time	324309230497 ps
CPU time	3173.72 seconds
Started	Aug 29 06:41:29 AM UTC 24
Finished	Aug 29 07:35:00 AM UTC 24
Peak memory	3219760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367188061 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_and_output.1367188061 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/22.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/22.kmac_sideload.2180607178
Short name	T406
Test name
Test status
Simulation time	24647052929 ps
CPU time	402.85 seconds
Started	Aug 29 06:42:20 AM UTC 24
Finished	Aug 29 06:49:08 AM UTC 24
Peak memory	545016 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180607178 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.2180607178 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/22.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/22.kmac_smoke.1953973141
Short name	T362
Test name
Test status
Simulation time	14629003541 ps
CPU time	65.03 seconds
Started	Aug 29 06:41:15 AM UTC 24
Finished	Aug 29 06:42:21 AM UTC 24
Peak memory	235808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953973141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.1953973141 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/22.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/22.kmac_stress_all.3224056594
Short name	T607
Test name
Test status
Simulation time	35877119573 ps
CPU time	1845.9 seconds
Started	Aug 29 06:43:08 AM UTC 24
Finished	Aug 29 07:14:16 AM UTC 24
Peak memory	629112 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224056594 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.3224056594 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/22.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/23.kmac_alert_test.3725987785
Short name	T382
Test name
Test status
Simulation time	17587949 ps
CPU time	1.23 seconds
Started	Aug 29 06:45:12 AM UTC 24
Finished	Aug 29 06:45:14 AM UTC 24
Peak memory	226172 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725987785 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.3725987785 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/23.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/23.kmac_app.2823619109
Short name	T380
Test name
Test status
Simulation time	1134320996 ps
CPU time	42.71 seconds
Started	Aug 29 06:44:26 AM UTC 24
Finished	Aug 29 06:45:11 AM UTC 24
Peak memory	252196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823619109 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.2823619109 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/23.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/23.kmac_burst_write.1604958930
Short name	T514
Test name
Test status
Simulation time	9955618352 ps
CPU time	1053.76 seconds
Started	Aug 29 06:44:17 AM UTC 24
Finished	Aug 29 07:02:03 AM UTC 24
Peak memory	252204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604958930 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.1604958930 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/23.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/23.kmac_entropy_refresh.1920550531
Short name	T404
Test name
Test status
Simulation time	6206941379 ps
CPU time	232.49 seconds
Started	Aug 29 06:44:26 AM UTC 24
Finished	Aug 29 06:48:22 AM UTC 24
Peak memory	289164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920550531 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.1920550531 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/23.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/23.kmac_error.692337121
Short name	T434
Test name
Test status
Simulation time	24045399518 ps
CPU time	539.35 seconds
Started	Aug 29 06:44:43 AM UTC 24
Finished	Aug 29 06:53:50 AM UTC 24
Peak memory	385380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692337121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.692337121 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/23.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/23.kmac_key_error.2446418034
Short name	T381
Test name
Test status
Simulation time	10605885702 ps
CPU time	19.06 seconds
Started	Aug 29 06:44:53 AM UTC 24
Finished	Aug 29 06:45:13 AM UTC 24
Peak memory	229684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446418034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.2446418034 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/23.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/23.kmac_lc_escalation.2976204448
Short name	T379
Test name
Test status
Simulation time	177431259 ps
CPU time	2.5 seconds
Started	Aug 29 06:44:56 AM UTC 24
Finished	Aug 29 06:44:59 AM UTC 24
Peak memory	234548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976204448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.2976204448 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/23.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/23.kmac_long_msg_and_output.978565991
Short name	T414
Test name
Test status
Simulation time	41968200386 ps
CPU time	463.23 seconds
Started	Aug 29 06:43:24 AM UTC 24
Finished	Aug 29 06:51:14 AM UTC 24
Peak memory	708916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978565991 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_and_output.978565991 +enable_masking= 1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/23.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/23.kmac_sideload.1018289212
Short name	T339
Test name
Test status
Simulation time	23194245405 ps
CPU time	460.44 seconds
Started	Aug 29 06:43:56 AM UTC 24
Finished	Aug 29 06:51:43 AM UTC 24
Peak memory	372980 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018289212 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.1018289212 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/23.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/23.kmac_smoke.145362189
Short name	T377
Test name
Test status
Simulation time	3889443014 ps
CPU time	95.71 seconds
Started	Aug 29 06:43:14 AM UTC 24
Finished	Aug 29 06:44:52 AM UTC 24
Peak memory	235772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145362189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.145362189 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/23.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/23.kmac_stress_all.3881221669
Short name	T562
Test name
Test status
Simulation time	136601460231 ps
CPU time	1350.65 seconds
Started	Aug 29 06:45:00 AM UTC 24
Finished	Aug 29 07:07:47 AM UTC 24
Peak memory	1098444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881221669 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.3881221669 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/23.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/24.kmac_alert_test.2606725660
Short name	T392
Test name
Test status
Simulation time	13789392 ps
CPU time	1.26 seconds
Started	Aug 29 06:46:40 AM UTC 24
Finished	Aug 29 06:46:43 AM UTC 24
Peak memory	226292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606725660 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.2606725660 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/24.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/24.kmac_app.2255928945
Short name	T399
Test name
Test status
Simulation time	1383383892 ps
CPU time	118.58 seconds
Started	Aug 29 06:45:34 AM UTC 24
Finished	Aug 29 06:47:36 AM UTC 24
Peak memory	258296 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255928945 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.2255928945 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/24.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/24.kmac_burst_write.1901491494
Short name	T477
Test name
Test status
Simulation time	6980261256 ps
CPU time	746.88 seconds
Started	Aug 29 06:45:29 AM UTC 24
Finished	Aug 29 06:58:06 AM UTC 24
Peak memory	245976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901491494 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.1901491494 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/24.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/24.kmac_entropy_refresh.1571870810
Short name	T424
Test name
Test status
Simulation time	13869654354 ps
CPU time	390.78 seconds
Started	Aug 29 06:45:44 AM UTC 24
Finished	Aug 29 06:52:20 AM UTC 24
Peak memory	346360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571870810 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.1571870810 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/24.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/24.kmac_error.2872379005
Short name	T436
Test name
Test status
Simulation time	13106747433 ps
CPU time	477.14 seconds
Started	Aug 29 06:45:53 AM UTC 24
Finished	Aug 29 06:53:56 AM UTC 24
Peak memory	518532 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872379005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.2872379005 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/24.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/24.kmac_key_error.2767593
Short name	T389
Test name
Test status
Simulation time	2192141105 ps
CPU time	8.96 seconds
Started	Aug 29 06:46:05 AM UTC 24
Finished	Aug 29 06:46:15 AM UTC 24
Peak memory	227628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE Q=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.2767593 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/24.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/24.kmac_long_msg_and_output.3918684144
Short name	T703
Test name
Test status
Simulation time	55546187188 ps
CPU time	3579.93 seconds
Started	Aug 29 06:45:15 AM UTC 24
Finished	Aug 29 07:45:36 AM UTC 24
Peak memory	1839348 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918684144 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_and_output.3918684144 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/24.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/24.kmac_sideload.2364695186
Short name	T435
Test name
Test status
Simulation time	5663715131 ps
CPU time	504.1 seconds
Started	Aug 29 06:45:23 AM UTC 24
Finished	Aug 29 06:53:54 AM UTC 24
Peak memory	375140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364695186 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.2364695186 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/24.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/24.kmac_smoke.3883686908
Short name	T388
Test name
Test status
Simulation time	1882170923 ps
CPU time	48.63 seconds
Started	Aug 29 06:45:14 AM UTC 24
Finished	Aug 29 06:46:04 AM UTC 24
Peak memory	235688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883686908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.3883686908 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/24.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/24.kmac_stress_all.2736844003
Short name	T537
Test name
Test status
Simulation time	23526656508 ps
CPU time	1132.59 seconds
Started	Aug 29 06:46:20 AM UTC 24
Finished	Aug 29 07:05:27 AM UTC 24
Peak memory	846076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736844003 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.2736844003 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/24.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/25.kmac_alert_test.330581706
Short name	T401
Test name
Test status
Simulation time	18485037 ps
CPU time	1.26 seconds
Started	Aug 29 06:47:41 AM UTC 24
Finished	Aug 29 06:47:43 AM UTC 24
Peak memory	227556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330581706 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.330581706 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/25.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/25.kmac_app.733913983
Short name	T418
Test name
Test status
Simulation time	8271274783 ps
CPU time	283.6 seconds
Started	Aug 29 06:46:56 AM UTC 24
Finished	Aug 29 06:51:45 AM UTC 24
Peak memory	409856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733913983 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.733913983 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/25.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/25.kmac_burst_write.3625681561
Short name	T450
Test name
Test status
Simulation time	11693986338 ps
CPU time	499.02 seconds
Started	Aug 29 06:46:50 AM UTC 24
Finished	Aug 29 06:55:16 AM UTC 24
Peak memory	244008 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625681561 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.3625681561 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/25.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/25.kmac_entropy_refresh.2289356951
Short name	T440
Test name
Test status
Simulation time	20808498239 ps
CPU time	434.46 seconds
Started	Aug 29 06:46:59 AM UTC 24
Finished	Aug 29 06:54:19 AM UTC 24
Peak memory	459000 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289356951 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.2289356951 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/25.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/25.kmac_error.3935356103
Short name	T467
Test name
Test status
Simulation time	18844143705 ps
CPU time	613.25 seconds
Started	Aug 29 06:46:59 AM UTC 24
Finished	Aug 29 06:57:20 AM UTC 24
Peak memory	661768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935356103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.3935356103 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/25.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/25.kmac_key_error.921612613
Short name	T400
Test name
Test status
Simulation time	4587905341 ps
CPU time	16.47 seconds
Started	Aug 29 06:47:21 AM UTC 24
Finished	Aug 29 06:47:38 AM UTC 24
Peak memory	227776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921612613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.921612613 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/25.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/25.kmac_lc_escalation.1832053544
Short name	T72
Test name
Test status
Simulation time	58478970 ps
CPU time	2.66 seconds
Started	Aug 29 06:47:37 AM UTC 24
Finished	Aug 29 06:47:41 AM UTC 24
Peak memory	234588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832053544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.1832053544 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/25.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/25.kmac_long_msg_and_output.3598529499
Short name	T474
Test name
Test status
Simulation time	77123941505 ps
CPU time	652.61 seconds
Started	Aug 29 06:46:43 AM UTC 24
Finished	Aug 29 06:57:44 AM UTC 24
Peak memory	946392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598529499 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_and_output.3598529499 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/25.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/25.kmac_sideload.2715224688
Short name	T430
Test name
Test status
Simulation time	30651193011 ps
CPU time	373.95 seconds
Started	Aug 29 06:46:44 AM UTC 24
Finished	Aug 29 06:53:04 AM UTC 24
Peak memory	327900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715224688 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.2715224688 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/25.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/25.kmac_smoke.1434809243
Short name	T398
Test name
Test status
Simulation time	2993564769 ps
CPU time	36.69 seconds
Started	Aug 29 06:46:42 AM UTC 24
Finished	Aug 29 06:47:20 AM UTC 24
Peak memory	235828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434809243 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.1434809243 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/25.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/25.kmac_stress_all.347230450
Short name	T402
Test name
Test status
Simulation time	160336716 ps
CPU time	4.9 seconds
Started	Aug 29 06:47:39 AM UTC 24
Finished	Aug 29 06:47:45 AM UTC 24
Peak memory	229776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347230450 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.347230450 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/25.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/26.kmac_alert_test.4123983143
Short name	T411
Test name
Test status
Simulation time	39381577 ps
CPU time	1.22 seconds
Started	Aug 29 06:49:57 AM UTC 24
Finished	Aug 29 06:49:59 AM UTC 24
Peak memory	226052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123983143 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.4123983143 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/26.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/26.kmac_app.2535719563
Short name	T420
Test name
Test status
Simulation time	11191246603 ps
CPU time	183.94 seconds
Started	Aug 29 06:48:48 AM UTC 24
Finished	Aug 29 06:51:55 AM UTC 24
Peak memory	330096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535719563 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.2535719563 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/26.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/26.kmac_burst_write.120795603
Short name	T480
Test name
Test status
Simulation time	20702403397 ps
CPU time	591.9 seconds
Started	Aug 29 06:48:23 AM UTC 24
Finished	Aug 29 06:58:23 AM UTC 24
Peak memory	243952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120795603 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.120795603 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/26.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/26.kmac_entropy_refresh.734347893
Short name	T412
Test name
Test status
Simulation time	3080216628 ps
CPU time	68.96 seconds
Started	Aug 29 06:49:09 AM UTC 24
Finished	Aug 29 06:50:19 AM UTC 24
Peak memory	252220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734347893 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.734347893 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/26.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/26.kmac_error.2380462557
Short name	T448
Test name
Test status
Simulation time	8772832968 ps
CPU time	339.56 seconds
Started	Aug 29 06:49:22 AM UTC 24
Finished	Aug 29 06:55:07 AM UTC 24
Peak memory	336260 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380462557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.2380462557 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/26.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/26.kmac_key_error.3137397996
Short name	T410
Test name
Test status
Simulation time	5367104957 ps
CPU time	14.36 seconds
Started	Aug 29 06:49:40 AM UTC 24
Finished	Aug 29 06:49:55 AM UTC 24
Peak memory	227616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137397996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.3137397996 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/26.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/26.kmac_lc_escalation.2356029311
Short name	T110
Test name
Test status
Simulation time	38865475 ps
CPU time	1.89 seconds
Started	Aug 29 06:49:53 AM UTC 24
Finished	Aug 29 06:49:56 AM UTC 24
Peak memory	231340 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356029311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.2356029311 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/26.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/26.kmac_long_msg_and_output.1850706698
Short name	T510
Test name
Test status
Simulation time	41238216252 ps
CPU time	827.7 seconds
Started	Aug 29 06:47:46 AM UTC 24
Finished	Aug 29 07:01:44 AM UTC 24
Peak memory	614732 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850706698 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_and_output.1850706698 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/26.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/26.kmac_sideload.1631937476
Short name	T431
Test name
Test status
Simulation time	41012542251 ps
CPU time	300.17 seconds
Started	Aug 29 06:47:59 AM UTC 24
Finished	Aug 29 06:53:04 AM UTC 24
Peak memory	432444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631937476 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.1631937476 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/26.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/26.kmac_smoke.932247636
Short name	T405
Test name
Test status
Simulation time	7738573162 ps
CPU time	61.1 seconds
Started	Aug 29 06:47:44 AM UTC 24
Finished	Aug 29 06:48:47 AM UTC 24
Peak memory	235768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932247636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.932247636 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/26.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/26.kmac_stress_all.3296841904
Short name	T690
Test name
Test status
Simulation time	212054216635 ps
CPU time	2450.64 seconds
Started	Aug 29 06:49:56 AM UTC 24
Finished	Aug 29 07:31:15 AM UTC 24
Peak memory	1333896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296841904 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.3296841904 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/26.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/27.kmac_alert_test.3815491422
Short name	T422
Test name
Test status
Simulation time	55503042 ps
CPU time	1.28 seconds
Started	Aug 29 06:51:56 AM UTC 24
Finished	Aug 29 06:51:59 AM UTC 24
Peak memory	224492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815491422 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.3815491422 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/27.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/27.kmac_app.1749417714
Short name	T416
Test name
Test status
Simulation time	438223735 ps
CPU time	14.21 seconds
Started	Aug 29 06:51:21 AM UTC 24
Finished	Aug 29 06:51:36 AM UTC 24
Peak memory	244236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749417714 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.1749417714 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/27.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/27.kmac_burst_write.2244080391
Short name	T490
Test name
Test status
Simulation time	9412619128 ps
CPU time	462.76 seconds
Started	Aug 29 06:51:15 AM UTC 24
Finished	Aug 29 06:59:03 AM UTC 24
Peak memory	252180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244080391 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.2244080391 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/27.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/27.kmac_entropy_refresh.3712058606
Short name	T478
Test name
Test status
Simulation time	6827814426 ps
CPU time	389.82 seconds
Started	Aug 29 06:51:37 AM UTC 24
Finished	Aug 29 06:58:12 AM UTC 24
Peak memory	342332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712058606 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.3712058606 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/27.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/27.kmac_error.725242622
Short name	T426
Test name
Test status
Simulation time	1118689532 ps
CPU time	46.48 seconds
Started	Aug 29 06:51:39 AM UTC 24
Finished	Aug 29 06:52:27 AM UTC 24
Peak memory	264464 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725242622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.725242622 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/27.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/27.kmac_key_error.2430649262
Short name	T421
Test name
Test status
Simulation time	766329059 ps
CPU time	9.99 seconds
Started	Aug 29 06:51:44 AM UTC 24
Finished	Aug 29 06:51:55 AM UTC 24
Peak memory	227616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430649262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.2430649262 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/27.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/27.kmac_lc_escalation.4191550897
Short name	T419
Test name
Test status
Simulation time	22163015 ps
CPU time	2.22 seconds
Started	Aug 29 06:51:45 AM UTC 24
Finished	Aug 29 06:51:48 AM UTC 24
Peak memory	231760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191550897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.4191550897 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/27.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/27.kmac_long_msg_and_output.2464191536
Short name	T468
Test name
Test status
Simulation time	4426284430 ps
CPU time	417.17 seconds
Started	Aug 29 06:50:20 AM UTC 24
Finished	Aug 29 06:57:23 AM UTC 24
Peak memory	434384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464191536 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_and_output.2464191536 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/27.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/27.kmac_sideload.1757924366
Short name	T459
Test name
Test status
Simulation time	25740344693 ps
CPU time	318.18 seconds
Started	Aug 29 06:50:36 AM UTC 24
Finished	Aug 29 06:55:59 AM UTC 24
Peak memory	411892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757924366 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.1757924366 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/27.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/27.kmac_smoke.2071658877
Short name	T417
Test name
Test status
Simulation time	8265010807 ps
CPU time	95.81 seconds
Started	Aug 29 06:50:00 AM UTC 24
Finished	Aug 29 06:51:38 AM UTC 24
Peak memory	235748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071658877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.2071658877 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/27.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/27.kmac_stress_all.1231064677
Short name	T694
Test name
Test status
Simulation time	50016050232 ps
CPU time	2502.09 seconds
Started	Aug 29 06:51:49 AM UTC 24
Finished	Aug 29 07:34:02 AM UTC 24
Peak memory	1313476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231064677 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.1231064677 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/27.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/28.kmac_alert_test.2399639387
Short name	T432
Test name
Test status
Simulation time	17119279 ps
CPU time	1.27 seconds
Started	Aug 29 06:53:04 AM UTC 24
Finished	Aug 29 06:53:07 AM UTC 24
Peak memory	226052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399639387 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.2399639387 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/28.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/28.kmac_app.3789211930
Short name	T466
Test name
Test status
Simulation time	29687905312 ps
CPU time	288 seconds
Started	Aug 29 06:52:23 AM UTC 24
Finished	Aug 29 06:57:15 AM UTC 24
Peak memory	395532 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789211930 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.3789211930 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/28.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/28.kmac_burst_write.3201804996
Short name	T439
Test name
Test status
Simulation time	8322264551 ps
CPU time	112.57 seconds
Started	Aug 29 06:52:21 AM UTC 24
Finished	Aug 29 06:54:16 AM UTC 24
Peak memory	235800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201804996 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.3201804996 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/28.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/28.kmac_entropy_refresh.3554704482
Short name	T487
Test name
Test status
Simulation time	9382302307 ps
CPU time	365.79 seconds
Started	Aug 29 06:52:28 AM UTC 24
Finished	Aug 29 06:58:39 AM UTC 24
Peak memory	332028 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554704482 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.3554704482 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/28.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/28.kmac_error.1740931069
Short name	T458
Test name
Test status
Simulation time	9108566827 ps
CPU time	198.25 seconds
Started	Aug 29 06:52:36 AM UTC 24
Finished	Aug 29 06:55:57 AM UTC 24
Peak memory	301376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740931069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.1740931069 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/28.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/28.kmac_key_error.1988733356
Short name	T429
Test name
Test status
Simulation time	443911290 ps
CPU time	5.95 seconds
Started	Aug 29 06:52:56 AM UTC 24
Finished	Aug 29 06:53:03 AM UTC 24
Peak memory	227576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988733356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.1988733356 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/28.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/28.kmac_long_msg_and_output.2869116352
Short name	T705
Test name
Test status
Simulation time	85485730126 ps
CPU time	3278.69 seconds
Started	Aug 29 06:51:59 AM UTC 24
Finished	Aug 29 07:47:19 AM UTC 24
Peak memory	3295544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869116352 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_and_output.2869116352 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/28.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/28.kmac_sideload.402512104
Short name	T457
Test name
Test status
Simulation time	13699474320 ps
CPU time	206.5 seconds
Started	Aug 29 06:52:14 AM UTC 24
Finished	Aug 29 06:55:44 AM UTC 24
Peak memory	418100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402512104 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.402512104 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/28.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/28.kmac_smoke.62823257
Short name	T423
Test name
Test status
Simulation time	631027694 ps
CPU time	15.47 seconds
Started	Aug 29 06:51:56 AM UTC 24
Finished	Aug 29 06:52:13 AM UTC 24
Peak memory	235780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62823257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.62823257 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/28.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/28.kmac_stress_all.1194128197
Short name	T106
Test name
Test status
Simulation time	7695562865 ps
CPU time	299.25 seconds
Started	Aug 29 06:53:04 AM UTC 24
Finished	Aug 29 06:58:08 AM UTC 24
Peak memory	310024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194128197 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.1194128197 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/28.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/29.kmac_alert_test.4192425198
Short name	T442
Test name
Test status
Simulation time	29399629 ps
CPU time	1.2 seconds
Started	Aug 29 06:54:20 AM UTC 24
Finished	Aug 29 06:54:23 AM UTC 24
Peak memory	224972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192425198 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.4192425198 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/29.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/29.kmac_app.1272515944
Short name	T471
Test name
Test status
Simulation time	10051019740 ps
CPU time	210.39 seconds
Started	Aug 29 06:53:55 AM UTC 24
Finished	Aug 29 06:57:29 AM UTC 24
Peak memory	385268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272515944 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.1272515944 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/29.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/29.kmac_burst_write.3140224800
Short name	T577
Test name
Test status
Simulation time	68514104299 ps
CPU time	974.01 seconds
Started	Aug 29 06:53:51 AM UTC 24
Finished	Aug 29 07:10:18 AM UTC 24
Peak memory	256300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140224800 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.3140224800 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/29.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/29.kmac_entropy_refresh.317945834
Short name	T464
Test name
Test status
Simulation time	7253996462 ps
CPU time	180.03 seconds
Started	Aug 29 06:53:57 AM UTC 24
Finished	Aug 29 06:57:00 AM UTC 24
Peak memory	340224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317945834 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.317945834 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/29.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/29.kmac_error.1380874792
Short name	T494
Test name
Test status
Simulation time	8623016330 ps
CPU time	316.15 seconds
Started	Aug 29 06:53:59 AM UTC 24
Finished	Aug 29 06:59:20 AM UTC 24
Peak memory	407872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380874792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.1380874792 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/29.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/29.kmac_key_error.2214391799
Short name	T443
Test name
Test status
Simulation time	2609889080 ps
CPU time	9.17 seconds
Started	Aug 29 06:54:16 AM UTC 24
Finished	Aug 29 06:54:27 AM UTC 24
Peak memory	227580 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214391799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.2214391799 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/29.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/29.kmac_lc_escalation.4181528081
Short name	T441
Test name
Test status
Simulation time	35575150 ps
CPU time	2.13 seconds
Started	Aug 29 06:54:16 AM UTC 24
Finished	Aug 29 06:54:19 AM UTC 24
Peak memory	233864 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181528081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.4181528081 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/29.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/29.kmac_long_msg_and_output.3616346555
Short name	T664
Test name
Test status
Simulation time	37382230049 ps
CPU time	1643.74 seconds
Started	Aug 29 06:53:31 AM UTC 24
Finished	Aug 29 07:21:14 AM UTC 24
Peak memory	1894704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616346555 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_and_output.3616346555 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/29.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/29.kmac_sideload.985821204
Short name	T489
Test name
Test status
Simulation time	8860369189 ps
CPU time	313.8 seconds
Started	Aug 29 06:53:41 AM UTC 24
Finished	Aug 29 06:58:59 AM UTC 24
Peak memory	416156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985821204 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.985821204 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/29.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/29.kmac_smoke.234838657
Short name	T438
Test name
Test status
Simulation time	5357810355 ps
CPU time	66.14 seconds
Started	Aug 29 06:53:07 AM UTC 24
Finished	Aug 29 06:54:15 AM UTC 24
Peak memory	235816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234838657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.234838657 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/29.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/29.kmac_stress_all.3790101696
Short name	T713
Test name
Test status
Simulation time	343094121418 ps
CPU time	3784.78 seconds
Started	Aug 29 06:54:20 AM UTC 24
Finished	Aug 29 07:58:08 AM UTC 24
Peak memory	1383104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790101696 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.3790101696 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/29.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/3.kmac_alert_test.1026536297
Short name	T207
Test name
Test status
Simulation time	70167108 ps
CPU time	1.37 seconds
Started	Aug 29 06:19:17 AM UTC 24
Finished	Aug 29 06:19:19 AM UTC 24
Peak memory	226048 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026536297 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.1026536297 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/3.kmac_app.1020790335
Short name	T37
Test name
Test status
Simulation time	5965246424 ps
CPU time	257.46 seconds
Started	Aug 29 06:19:00 AM UTC 24
Finished	Aug 29 06:23:21 AM UTC 24
Peak memory	307540 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020790335 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.1020790335 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/3.kmac_app_with_partial_data.4087529705
Short name	T16
Test name
Test status
Simulation time	5102310333 ps
CPU time	140.02 seconds
Started	Aug 29 06:19:00 AM UTC 24
Finished	Aug 29 06:21:23 AM UTC 24
Peak memory	296132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087529705 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.4087529705 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_app_with_partial_data/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/3.kmac_burst_write.769159582
Short name	T126
Test name
Test status
Simulation time	18817109737 ps
CPU time	200.79 seconds
Started	Aug 29 06:18:54 AM UTC 24
Finished	Aug 29 06:22:18 AM UTC 24
Peak memory	237892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769159582 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.769159582 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/3.kmac_edn_timeout_error.2295327516
Short name	T89
Test name
Test status
Simulation time	1463675149 ps
CPU time	51.76 seconds
Started	Aug 29 06:19:06 AM UTC 24
Finished	Aug 29 06:20:00 AM UTC 24
Peak memory	237600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295327516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.2295327516 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_mode_error.3632506924
Short name	T93
Test name
Test status
Simulation time	13478017 ps
CPU time	1.26 seconds
Started	Aug 29 06:19:06 AM UTC 24
Finished	Aug 29 06:19:09 AM UTC 24
Peak memory	224844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632506924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.3632506924 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_ready_error.1336691513
Short name	T5
Test name
Test status
Simulation time	715126633 ps
CPU time	10.78 seconds
Started	Aug 29 06:19:10 AM UTC 24
Finished	Aug 29 06:19:22 AM UTC 24
Peak memory	231708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336691513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.1336691513 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_entropy_ready_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_refresh.3630214310
Short name	T95
Test name
Test status
Simulation time	8346861958 ps
CPU time	271.02 seconds
Started	Aug 29 06:19:00 AM UTC 24
Finished	Aug 29 06:23:35 AM UTC 24
Peak memory	407864 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630214310 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.3630214310 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/3.kmac_error.3104196401
Short name	T19
Test name
Test status
Simulation time	50258275073 ps
CPU time	366.03 seconds
Started	Aug 29 06:19:04 AM UTC 24
Finished	Aug 29 06:25:15 AM UTC 24
Peak memory	504044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104196401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.3104196401 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/3.kmac_key_error.1310340064
Short name	T56
Test name
Test status
Simulation time	31337130 ps
CPU time	1.78 seconds
Started	Aug 29 06:19:06 AM UTC 24
Finished	Aug 29 06:19:09 AM UTC 24
Peak memory	224256 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310340064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.1310340064 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/3.kmac_long_msg_and_output.3883323767
Short name	T712
Test name
Test status
Simulation time	130759661849 ps
CPU time	5763.42 seconds
Started	Aug 29 06:18:52 AM UTC 24
Finished	Aug 29 07:56:00 AM UTC 24
Peak memory	4898948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883323767 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_and_output.3883323767 +enable_masking =1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/3.kmac_mubi.2502535175
Short name	T77
Test name
Test status
Simulation time	3564626475 ps
CPU time	245.7 seconds
Started	Aug 29 06:19:02 AM UTC 24
Finished	Aug 29 06:23:12 AM UTC 24
Peak memory	297612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502535175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.2502535175 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/3.kmac_sec_cm.941126775
Short name	T103
Test name
Test status
Simulation time	6755968795 ps
CPU time	116.21 seconds
Started	Aug 29 06:19:17 AM UTC 24
Finished	Aug 29 06:21:15 AM UTC 24
Peak memory	310840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941126775 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.941126775 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/3.kmac_sideload.4021914698
Short name	T24
Test name
Test status
Simulation time	12952585801 ps
CPU time	121.69 seconds
Started	Aug 29 06:18:52 AM UTC 24
Finished	Aug 29 06:20:56 AM UTC 24
Peak memory	313724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021914698 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.4021914698 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/3.kmac_smoke.1291955571
Short name	T31
Test name
Test status
Simulation time	263996511 ps
CPU time	5.77 seconds
Started	Aug 29 06:18:52 AM UTC 24
Finished	Aug 29 06:18:59 AM UTC 24
Peak memory	235680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291955571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.1291955571 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/3.kmac_stress_all.715640071
Short name	T163
Test name
Test status
Simulation time	13822609355 ps
CPU time	982.6 seconds
Started	Aug 29 06:19:12 AM UTC 24
Finished	Aug 29 06:35:47 AM UTC 24
Peak memory	383628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715640071 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.715640071 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac.1624782652
Short name	T90
Test name
Test status
Simulation time	78704000 ps
CPU time	3.48 seconds
Started	Aug 29 06:18:58 AM UTC 24
Finished	Aug 29 06:19:02 AM UTC 24
Peak memory	229744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624782652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac.1624782652 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac_xof.3999241735
Short name	T92
Test name
Test status
Simulation time	101362226 ps
CPU time	3.92 seconds
Started	Aug 29 06:19:00 AM UTC 24
Finished	Aug 29 06:19:05 AM UTC 24
Peak memory	235712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999241735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac_xof.3999241735 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac_xof/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_224.408099453
Short name	T597
Test name
Test status
Simulation time	90739001482 ps
CPU time	3242.06 seconds
Started	Aug 29 06:18:54 AM UTC 24
Finished	Aug 29 07:13:35 AM UTC 24
Peak memory	3096828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408099453 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.408099453 +enable _masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_224/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_256.915929144
Short name	T447
Test name
Test status
Simulation time	16868285712 ps
CPU time	2142.86 seconds
Started	Aug 29 06:18:55 AM UTC 24
Finished	Aug 29 06:55:04 AM UTC 24
Peak memory	1120404 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915929144 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.915929144 +enable _masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_256/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_384.2973144822
Short name	T384
Test name
Test status
Simulation time	80608349089 ps
CPU time	1574.31 seconds
Started	Aug 29 06:18:55 AM UTC 24
Finished	Aug 29 06:45:28 AM UTC 24
Peak memory	899232 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973144822 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.2973144822 +enab le_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_384/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_512.357095307
Short name	T208
Test name
Test status
Simulation time	5095012804 ps
CPU time	28.08 seconds
Started	Aug 29 06:18:55 AM UTC 24
Finished	Aug 29 06:19:25 AM UTC 24
Peak memory	233916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357095307 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.357095307 +enable _masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_512/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_128.1574719083
Short name	T525
Test name
Test status
Simulation time	21522446250 ps
CPU time	2667.23 seconds
Started	Aug 29 06:18:56 AM UTC 24
Finished	Aug 29 07:03:54 AM UTC 24
Peak memory	1333408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574719083 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.1574719083 +e nable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_128/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_256.4101373330
Short name	T205
Test name
Test status
Simulation time	64106397066 ps
CPU time	393.65 seconds
Started	Aug 29 06:18:58 AM UTC 24
Finished	Aug 29 06:25:37 AM UTC 24
Peak memory	368804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101373330 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.4101373330 +e nable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_256/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/30.kmac_alert_test.2404172646
Short name	T452
Test name
Test status
Simulation time	124637917 ps
CPU time	1.19 seconds
Started	Aug 29 06:55:23 AM UTC 24
Finished	Aug 29 06:55:26 AM UTC 24
Peak memory	226052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404172646 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.2404172646 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/30.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/30.kmac_app.1460214063
Short name	T498
Test name
Test status
Simulation time	175818996239 ps
CPU time	305.55 seconds
Started	Aug 29 06:54:53 AM UTC 24
Finished	Aug 29 07:00:03 AM UTC 24
Peak memory	457012 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460214063 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.1460214063 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/30.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/30.kmac_burst_write.3156518396
Short name	T650
Test name
Test status
Simulation time	33113501307 ps
CPU time	1486.66 seconds
Started	Aug 29 06:54:48 AM UTC 24
Finished	Aug 29 07:19:52 AM UTC 24
Peak memory	274732 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156518396 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.3156518396 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/30.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/30.kmac_entropy_refresh.2810000534
Short name	T476
Test name
Test status
Simulation time	13317925731 ps
CPU time	158.52 seconds
Started	Aug 29 06:55:05 AM UTC 24
Finished	Aug 29 06:57:46 AM UTC 24
Peak memory	317792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810000534 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.2810000534 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/30.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/30.kmac_error.1247449596
Short name	T515
Test name
Test status
Simulation time	5251363414 ps
CPU time	424.8 seconds
Started	Aug 29 06:55:08 AM UTC 24
Finished	Aug 29 07:02:19 AM UTC 24
Peak memory	373060 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247449596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.1247449596 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/30.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/30.kmac_key_error.3704776542
Short name	T454
Test name
Test status
Simulation time	3022639061 ps
CPU time	14.07 seconds
Started	Aug 29 06:55:15 AM UTC 24
Finished	Aug 29 06:55:30 AM UTC 24
Peak memory	229640 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704776542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.3704776542 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/30.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/30.kmac_lc_escalation.3957931500
Short name	T75
Test name
Test status
Simulation time	60118725 ps
CPU time	2.3 seconds
Started	Aug 29 06:55:17 AM UTC 24
Finished	Aug 29 06:55:21 AM UTC 24
Peak memory	231756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957931500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.3957931500 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/30.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/30.kmac_long_msg_and_output.1029825776
Short name	T608
Test name
Test status
Simulation time	45672496732 ps
CPU time	1177.44 seconds
Started	Aug 29 06:54:28 AM UTC 24
Finished	Aug 29 07:14:19 AM UTC 24
Peak memory	809208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029825776 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_and_output.1029825776 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/30.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/30.kmac_sideload.548155629
Short name	T485
Test name
Test status
Simulation time	10616954426 ps
CPU time	227.53 seconds
Started	Aug 29 06:54:44 AM UTC 24
Finished	Aug 29 06:58:35 AM UTC 24
Peak memory	315700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548155629 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.548155629 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/30.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/30.kmac_smoke.1094018139
Short name	T446
Test name
Test status
Simulation time	5544916714 ps
CPU time	27.04 seconds
Started	Aug 29 06:54:23 AM UTC 24
Finished	Aug 29 06:54:52 AM UTC 24
Peak memory	235776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094018139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.1094018139 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/30.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/30.kmac_stress_all.1724612422
Short name	T558
Test name
Test status
Simulation time	16235691384 ps
CPU time	705.73 seconds
Started	Aug 29 06:55:21 AM UTC 24
Finished	Aug 29 07:07:17 AM UTC 24
Peak memory	805540 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724612422 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.1724612422 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/30.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/31.kmac_alert_test.1266104161
Short name	T462
Test name
Test status
Simulation time	18111168 ps
CPU time	1.37 seconds
Started	Aug 29 06:56:10 AM UTC 24
Finished	Aug 29 06:56:13 AM UTC 24
Peak memory	226052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266104161 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.1266104161 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/31.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/31.kmac_app.1094563022
Short name	T486
Test name
Test status
Simulation time	4901876452 ps
CPU time	174.15 seconds
Started	Aug 29 06:55:39 AM UTC 24
Finished	Aug 29 06:58:36 AM UTC 24
Peak memory	336180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094563022 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.1094563022 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/31.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/31.kmac_burst_write.2498104840
Short name	T491
Test name
Test status
Simulation time	9641859204 ps
CPU time	220.92 seconds
Started	Aug 29 06:55:33 AM UTC 24
Finished	Aug 29 06:59:17 AM UTC 24
Peak memory	237864 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498104840 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.2498104840 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/31.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/31.kmac_entropy_refresh.1745580663
Short name	T102
Test name
Test status
Simulation time	8119472458 ps
CPU time	75.21 seconds
Started	Aug 29 06:55:45 AM UTC 24
Finished	Aug 29 06:57:02 AM UTC 24
Peak memory	270636 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745580663 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.1745580663 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/31.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/31.kmac_error.936148436
Short name	T527
Test name
Test status
Simulation time	11958383512 ps
CPU time	481.2 seconds
Started	Aug 29 06:55:58 AM UTC 24
Finished	Aug 29 07:04:06 AM UTC 24
Peak memory	542944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936148436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.936148436 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/31.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/31.kmac_key_error.1620240900
Short name	T461
Test name
Test status
Simulation time	556991867 ps
CPU time	8.03 seconds
Started	Aug 29 06:56:00 AM UTC 24
Finished	Aug 29 06:56:09 AM UTC 24
Peak memory	227512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620240900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.1620240900 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/31.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/31.kmac_lc_escalation.4063671290
Short name	T73
Test name
Test status
Simulation time	572559012 ps
CPU time	2.24 seconds
Started	Aug 29 06:56:03 AM UTC 24
Finished	Aug 29 06:56:06 AM UTC 24
Peak memory	233800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063671290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.4063671290 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/31.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/31.kmac_long_msg_and_output.1654752830
Short name	T533
Test name
Test status
Simulation time	64691889603 ps
CPU time	560.63 seconds
Started	Aug 29 06:55:32 AM UTC 24
Finished	Aug 29 07:05:00 AM UTC 24
Peak memory	817396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654752830 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_and_output.1654752830 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/31.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/31.kmac_sideload.476388730
Short name	T463
Test name
Test status
Simulation time	23662013912 ps
CPU time	85.09 seconds
Started	Aug 29 06:55:32 AM UTC 24
Finished	Aug 29 06:56:59 AM UTC 24
Peak memory	280836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476388730 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.476388730 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/31.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/31.kmac_smoke.3199843896
Short name	T460
Test name
Test status
Simulation time	2907491995 ps
CPU time	33.94 seconds
Started	Aug 29 06:55:26 AM UTC 24
Finished	Aug 29 06:56:02 AM UTC 24
Peak memory	235832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199843896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.3199843896 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/31.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/31.kmac_stress_all.3801904743
Short name	T496
Test name
Test status
Simulation time	16640877230 ps
CPU time	208.93 seconds
Started	Aug 29 06:56:07 AM UTC 24
Finished	Aug 29 06:59:39 AM UTC 24
Peak memory	318140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801904743 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.3801904743 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/31.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/32.kmac_alert_test.2603070132
Short name	T472
Test name
Test status
Simulation time	169185687 ps
CPU time	1.19 seconds
Started	Aug 29 06:57:30 AM UTC 24
Finished	Aug 29 06:57:32 AM UTC 24
Peak memory	225984 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603070132 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.2603070132 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/32.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/32.kmac_app.418361784
Short name	T520
Test name
Test status
Simulation time	80283818129 ps
CPU time	368.27 seconds
Started	Aug 29 06:57:16 AM UTC 24
Finished	Aug 29 07:03:30 AM UTC 24
Peak memory	469236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418361784 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.418361784 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/32.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/32.kmac_burst_write.3505922700
Short name	T559
Test name
Test status
Simulation time	53028476328 ps
CPU time	616.92 seconds
Started	Aug 29 06:57:03 AM UTC 24
Finished	Aug 29 07:07:28 AM UTC 24
Peak memory	252200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505922700 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.3505922700 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/32.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/32.kmac_entropy_refresh.1034677665
Short name	T499
Test name
Test status
Simulation time	7616094280 ps
CPU time	176.36 seconds
Started	Aug 29 06:57:16 AM UTC 24
Finished	Aug 29 07:00:16 AM UTC 24
Peak memory	284984 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034677665 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.1034677665 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/32.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/32.kmac_error.1054719290
Short name	T506
Test name
Test status
Simulation time	7999934796 ps
CPU time	210.21 seconds
Started	Aug 29 06:57:20 AM UTC 24
Finished	Aug 29 07:00:54 AM UTC 24
Peak memory	401656 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054719290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.1054719290 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/32.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/32.kmac_key_error.475995057
Short name	T470
Test name
Test status
Simulation time	134356135 ps
CPU time	2.57 seconds
Started	Aug 29 06:57:24 AM UTC 24
Finished	Aug 29 06:57:28 AM UTC 24
Peak memory	227520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475995057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.475995057 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/32.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/32.kmac_lc_escalation.3429825391
Short name	T473
Test name
Test status
Simulation time	163201811 ps
CPU time	2.54 seconds
Started	Aug 29 06:57:28 AM UTC 24
Finished	Aug 29 06:57:32 AM UTC 24
Peak memory	234084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429825391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.3429825391 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/32.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/32.kmac_long_msg_and_output.2716824443
Short name	T616
Test name
Test status
Simulation time	20111287171 ps
CPU time	1058.34 seconds
Started	Aug 29 06:57:00 AM UTC 24
Finished	Aug 29 07:14:52 AM UTC 24
Peak memory	1147188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716824443 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_and_output.2716824443 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/32.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/32.kmac_sideload.3330287659
Short name	T475
Test name
Test status
Simulation time	1218511771 ps
CPU time	43.94 seconds
Started	Aug 29 06:57:01 AM UTC 24
Finished	Aug 29 06:57:46 AM UTC 24
Peak memory	254252 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330287659 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.3330287659 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/32.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/32.kmac_smoke.192063558
Short name	T465
Test name
Test status
Simulation time	2910177468 ps
CPU time	59.68 seconds
Started	Aug 29 06:56:13 AM UTC 24
Finished	Aug 29 06:57:15 AM UTC 24
Peak memory	235768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192063558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.192063558 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/32.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/32.kmac_stress_all.1795154562
Short name	T676
Test name
Test status
Simulation time	234088887797 ps
CPU time	1572.25 seconds
Started	Aug 29 06:57:30 AM UTC 24
Finished	Aug 29 07:24:01 AM UTC 24
Peak memory	1221272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795154562 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.1795154562 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/32.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/33.kmac_alert_test.2720094599
Short name	T482
Test name
Test status
Simulation time	23487903 ps
CPU time	1.2 seconds
Started	Aug 29 06:58:25 AM UTC 24
Finished	Aug 29 06:58:28 AM UTC 24
Peak memory	226700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720094599 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.2720094599 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/33.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/33.kmac_app.2432817706
Short name	T528
Test name
Test status
Simulation time	62153503443 ps
CPU time	379.92 seconds
Started	Aug 29 06:57:47 AM UTC 24
Finished	Aug 29 07:04:12 AM UTC 24
Peak memory	422220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432817706 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.2432817706 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/33.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/33.kmac_burst_write.3852224337
Short name	T613
Test name
Test status
Simulation time	35723245624 ps
CPU time	992.69 seconds
Started	Aug 29 06:57:47 AM UTC 24
Finished	Aug 29 07:14:31 AM UTC 24
Peak memory	260440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852224337 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.3852224337 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/33.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/33.kmac_entropy_refresh.30646332
Short name	T517
Test name
Test status
Simulation time	4979033774 ps
CPU time	265.21 seconds
Started	Aug 29 06:58:07 AM UTC 24
Finished	Aug 29 07:02:37 AM UTC 24
Peak memory	301364 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30646332 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.30646332 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/33.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/33.kmac_error.3976675941
Short name	T553
Test name
Test status
Simulation time	27196615873 ps
CPU time	523.96 seconds
Started	Aug 29 06:58:09 AM UTC 24
Finished	Aug 29 07:07:00 AM UTC 24
Peak memory	383228 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976675941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.3976675941 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/33.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/33.kmac_key_error.556671943
Short name	T479
Test name
Test status
Simulation time	355886636 ps
CPU time	5.72 seconds
Started	Aug 29 06:58:13 AM UTC 24
Finished	Aug 29 06:58:20 AM UTC 24
Peak memory	227584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556671943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.556671943 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/33.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/33.kmac_lc_escalation.1990764195
Short name	T481
Test name
Test status
Simulation time	39979963 ps
CPU time	2.09 seconds
Started	Aug 29 06:58:21 AM UTC 24
Finished	Aug 29 06:58:24 AM UTC 24
Peak memory	233808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990764195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.1990764195 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/33.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/33.kmac_long_msg_and_output.3130853711
Short name	T501
Test name
Test status
Simulation time	1437925991 ps
CPU time	163.62 seconds
Started	Aug 29 06:57:33 AM UTC 24
Finished	Aug 29 07:00:20 AM UTC 24
Peak memory	297196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130853711 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_and_output.3130853711 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/33.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/33.kmac_sideload.32719004
Short name	T536
Test name
Test status
Simulation time	16625826421 ps
CPU time	454.96 seconds
Started	Aug 29 06:57:45 AM UTC 24
Finished	Aug 29 07:05:26 AM UTC 24
Peak memory	553336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32719004 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.32719004 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/33.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/33.kmac_smoke.359062600
Short name	T484
Test name
Test status
Simulation time	2392185211 ps
CPU time	59.71 seconds
Started	Aug 29 06:57:33 AM UTC 24
Finished	Aug 29 06:58:34 AM UTC 24
Peak memory	235772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359062600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.359062600 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/33.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/33.kmac_stress_all.2403208063
Short name	T605
Test name
Test status
Simulation time	95201046273 ps
CPU time	918.86 seconds
Started	Aug 29 06:58:24 AM UTC 24
Finished	Aug 29 07:13:54 AM UTC 24
Peak memory	613060 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403208063 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.2403208063 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/33.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/34.kmac_alert_test.2580014721
Short name	T493
Test name
Test status
Simulation time	17021665 ps
CPU time	1.26 seconds
Started	Aug 29 06:59:17 AM UTC 24
Finished	Aug 29 06:59:20 AM UTC 24
Peak memory	225692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580014721 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.2580014721 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/34.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/34.kmac_app.1048487267
Short name	T507
Test name
Test status
Simulation time	5183034342 ps
CPU time	135.65 seconds
Started	Aug 29 06:58:37 AM UTC 24
Finished	Aug 29 07:00:55 AM UTC 24
Peak memory	313628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048487267 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.1048487267 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/34.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/34.kmac_burst_write.1669215626
Short name	T643
Test name
Test status
Simulation time	22330158688 ps
CPU time	1195.12 seconds
Started	Aug 29 06:58:36 AM UTC 24
Finished	Aug 29 07:18:45 AM UTC 24
Peak memory	252144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669215626 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.1669215626 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/34.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/34.kmac_entropy_refresh.2619509037
Short name	T488
Test name
Test status
Simulation time	327153297 ps
CPU time	15.17 seconds
Started	Aug 29 06:58:40 AM UTC 24
Finished	Aug 29 06:58:56 AM UTC 24
Peak memory	245584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619509037 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.2619509037 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/34.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/34.kmac_error.3746368039
Short name	T561
Test name
Test status
Simulation time	61512639569 ps
CPU time	505.91 seconds
Started	Aug 29 06:58:57 AM UTC 24
Finished	Aug 29 07:07:30 AM UTC 24
Peak memory	612680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746368039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.3746368039 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/34.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/34.kmac_key_error.1411084513
Short name	T492
Test name
Test status
Simulation time	2296076564 ps
CPU time	16.92 seconds
Started	Aug 29 06:59:00 AM UTC 24
Finished	Aug 29 06:59:18 AM UTC 24
Peak memory	229708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411084513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.1411084513 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/34.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/34.kmac_long_msg_and_output.324416255
Short name	T710
Test name
Test status
Simulation time	26388205501 ps
CPU time	3249.96 seconds
Started	Aug 29 06:58:32 AM UTC 24
Finished	Aug 29 07:53:21 AM UTC 24
Peak memory	1708452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324416255 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_and_output.324416255 +enable_masking= 1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/34.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/34.kmac_sideload.1114299395
Short name	T497
Test name
Test status
Simulation time	907611499 ps
CPU time	78.43 seconds
Started	Aug 29 06:58:36 AM UTC 24
Finished	Aug 29 06:59:56 AM UTC 24
Peak memory	252084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114299395 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.1114299395 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/34.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/34.kmac_smoke.557191086
Short name	T500
Test name
Test status
Simulation time	15102067873 ps
CPU time	106.39 seconds
Started	Aug 29 06:58:29 AM UTC 24
Finished	Aug 29 07:00:17 AM UTC 24
Peak memory	235804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557191086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.557191086 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/34.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/34.kmac_stress_all.3841096585
Short name	T701
Test name
Test status
Simulation time	55859314919 ps
CPU time	2400.93 seconds
Started	Aug 29 06:59:08 AM UTC 24
Finished	Aug 29 07:39:38 AM UTC 24
Peak memory	1252016 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841096585 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.3841096585 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/34.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/35.kmac_alert_test.1571325189
Short name	T503
Test name
Test status
Simulation time	25551769 ps
CPU time	1.23 seconds
Started	Aug 29 07:00:22 AM UTC 24
Finished	Aug 29 07:00:24 AM UTC 24
Peak memory	226052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571325189 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.1571325189 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/35.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/35.kmac_app.1397640831
Short name	T554
Test name
Test status
Simulation time	88154330501 ps
CPU time	434.51 seconds
Started	Aug 29 06:59:40 AM UTC 24
Finished	Aug 29 07:07:01 AM UTC 24
Peak memory	495940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397640831 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.1397640831 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/35.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/35.kmac_burst_write.3431828678
Short name	T659
Test name
Test status
Simulation time	42093159929 ps
CPU time	1229.86 seconds
Started	Aug 29 06:59:39 AM UTC 24
Finished	Aug 29 07:20:24 AM UTC 24
Peak memory	252208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431828678 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.3431828678 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/35.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/35.kmac_entropy_refresh.3513022510
Short name	T550
Test name
Test status
Simulation time	30419234118 ps
CPU time	404.39 seconds
Started	Aug 29 06:59:57 AM UTC 24
Finished	Aug 29 07:06:47 AM UTC 24
Peak memory	463160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513022510 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.3513022510 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/35.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/35.kmac_error.1578078570
Short name	T523
Test name
Test status
Simulation time	8929014976 ps
CPU time	221.71 seconds
Started	Aug 29 07:00:06 AM UTC 24
Finished	Aug 29 07:03:51 AM UTC 24
Peak memory	422196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578078570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.1578078570 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/35.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/35.kmac_key_error.2470520967
Short name	T502
Test name
Test status
Simulation time	1216188295 ps
CPU time	3.1 seconds
Started	Aug 29 07:00:16 AM UTC 24
Finished	Aug 29 07:00:20 AM UTC 24
Peak memory	227580 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470520967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.2470520967 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/35.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/35.kmac_lc_escalation.3133646599
Short name	T66
Test name
Test status
Simulation time	973817607 ps
CPU time	16.61 seconds
Started	Aug 29 07:00:18 AM UTC 24
Finished	Aug 29 07:00:36 AM UTC 24
Peak memory	246016 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133646599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.3133646599 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/35.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/35.kmac_long_msg_and_output.333937659
Short name	T667
Test name
Test status
Simulation time	46786974751 ps
CPU time	1363.28 seconds
Started	Aug 29 06:59:21 AM UTC 24
Finished	Aug 29 07:22:20 AM UTC 24
Peak memory	1710380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333937659 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_and_output.333937659 +enable_masking= 1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/35.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/35.kmac_sideload.12383781
Short name	T542
Test name
Test status
Simulation time	14243133554 ps
CPU time	403.35 seconds
Started	Aug 29 06:59:21 AM UTC 24
Finished	Aug 29 07:06:10 AM UTC 24
Peak memory	536816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12383781 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.12383781 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/35.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/35.kmac_smoke.2663887844
Short name	T505
Test name
Test status
Simulation time	1884818984 ps
CPU time	90.13 seconds
Started	Aug 29 06:59:19 AM UTC 24
Finished	Aug 29 07:00:52 AM UTC 24
Peak memory	235772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663887844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.2663887844 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/35.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/36.kmac_alert_test.3909264841
Short name	T513
Test name
Test status
Simulation time	18186922 ps
CPU time	1.31 seconds
Started	Aug 29 07:02:00 AM UTC 24
Finished	Aug 29 07:02:02 AM UTC 24
Peak memory	226052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909264841 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.3909264841 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/36.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/36.kmac_app.221557585
Short name	T526
Test name
Test status
Simulation time	8171487233 ps
CPU time	184.74 seconds
Started	Aug 29 07:00:55 AM UTC 24
Finished	Aug 29 07:04:03 AM UTC 24
Peak memory	280832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221557585 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.221557585 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/36.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/36.kmac_burst_write.1587821398
Short name	T625
Test name
Test status
Simulation time	7211510182 ps
CPU time	878.35 seconds
Started	Aug 29 07:00:53 AM UTC 24
Finished	Aug 29 07:15:43 AM UTC 24
Peak memory	248052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587821398 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.1587821398 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/36.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/36.kmac_entropy_refresh.3884843149
Short name	T530
Test name
Test status
Simulation time	18342762609 ps
CPU time	218.27 seconds
Started	Aug 29 07:00:56 AM UTC 24
Finished	Aug 29 07:04:38 AM UTC 24
Peak memory	299312 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884843149 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.3884843149 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/36.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/36.kmac_error.2955203146
Short name	T509
Test name
Test status
Simulation time	3137695297 ps
CPU time	30.22 seconds
Started	Aug 29 07:01:04 AM UTC 24
Finished	Aug 29 07:01:36 AM UTC 24
Peak memory	252212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955203146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.2955203146 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/36.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/36.kmac_key_error.3775260411
Short name	T512
Test name
Test status
Simulation time	1693897290 ps
CPU time	20.89 seconds
Started	Aug 29 07:01:37 AM UTC 24
Finished	Aug 29 07:01:59 AM UTC 24
Peak memory	227488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775260411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.3775260411 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/36.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/36.kmac_lc_escalation.2751920560
Short name	T511
Test name
Test status
Simulation time	123707800 ps
CPU time	2.1 seconds
Started	Aug 29 07:01:46 AM UTC 24
Finished	Aug 29 07:01:49 AM UTC 24
Peak memory	233888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751920560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.2751920560 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/36.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/36.kmac_long_msg_and_output.3291594512
Short name	T697
Test name
Test status
Simulation time	322726007817 ps
CPU time	2104.44 seconds
Started	Aug 29 07:00:26 AM UTC 24
Finished	Aug 29 07:35:54 AM UTC 24
Peak memory	1155376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291594512 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_and_output.3291594512 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/36.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/36.kmac_sideload.1448337501
Short name	T551
Test name
Test status
Simulation time	99567512280 ps
CPU time	368.47 seconds
Started	Aug 29 07:00:37 AM UTC 24
Finished	Aug 29 07:06:51 AM UTC 24
Peak memory	457084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448337501 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.1448337501 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/36.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/36.kmac_smoke.3909203450
Short name	T508
Test name
Test status
Simulation time	2203868697 ps
CPU time	37.38 seconds
Started	Aug 29 07:00:25 AM UTC 24
Finished	Aug 29 07:01:03 AM UTC 24
Peak memory	235808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909203450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.3909203450 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/36.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/36.kmac_stress_all.2736194898
Short name	T685
Test name
Test status
Simulation time	71735992257 ps
CPU time	1571.7 seconds
Started	Aug 29 07:01:50 AM UTC 24
Finished	Aug 29 07:28:20 AM UTC 24
Peak memory	658108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736194898 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.2736194898 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/36.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/37.kmac_alert_test.550182642
Short name	T524
Test name
Test status
Simulation time	50122755 ps
CPU time	1.27 seconds
Started	Aug 29 07:03:50 AM UTC 24
Finished	Aug 29 07:03:53 AM UTC 24
Peak memory	227556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550182642 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.550182642 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/37.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/37.kmac_app.855080029
Short name	T538
Test name
Test status
Simulation time	10586162565 ps
CPU time	167.44 seconds
Started	Aug 29 07:02:37 AM UTC 24
Finished	Aug 29 07:05:28 AM UTC 24
Peak memory	278844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855080029 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.855080029 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/37.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/37.kmac_burst_write.1630761929
Short name	T541
Test name
Test status
Simulation time	20381247319 ps
CPU time	209.78 seconds
Started	Aug 29 07:02:33 AM UTC 24
Finished	Aug 29 07:06:06 AM UTC 24
Peak memory	239912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630761929 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.1630761929 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/37.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/37.kmac_entropy_refresh.1956415177
Short name	T570
Test name
Test status
Simulation time	9697395136 ps
CPU time	340.64 seconds
Started	Aug 29 07:03:27 AM UTC 24
Finished	Aug 29 07:09:12 AM UTC 24
Peak memory	309504 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956415177 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.1956415177 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/37.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/37.kmac_error.3863768203
Short name	T584
Test name
Test status
Simulation time	66900408736 ps
CPU time	474.58 seconds
Started	Aug 29 07:03:27 AM UTC 24
Finished	Aug 29 07:11:28 AM UTC 24
Peak memory	563492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863768203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.3863768203 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/37.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/37.kmac_key_error.2556458090
Short name	T521
Test name
Test status
Simulation time	1970555859 ps
CPU time	12.54 seconds
Started	Aug 29 07:03:31 AM UTC 24
Finished	Aug 29 07:03:45 AM UTC 24
Peak memory	229536 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556458090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.2556458090 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/37.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/37.kmac_lc_escalation.251786244
Short name	T76
Test name
Test status
Simulation time	33477626 ps
CPU time	2.05 seconds
Started	Aug 29 07:03:46 AM UTC 24
Finished	Aug 29 07:03:49 AM UTC 24
Peak memory	233876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251786244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.251786244 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/37.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/37.kmac_long_msg_and_output.202330814
Short name	T634
Test name
Test status
Simulation time	9370798009 ps
CPU time	915.49 seconds
Started	Aug 29 07:02:04 AM UTC 24
Finished	Aug 29 07:17:31 AM UTC 24
Peak memory	698668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202330814 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_and_output.202330814 +enable_masking= 1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/37.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/37.kmac_sideload.1318459350
Short name	T567
Test name
Test status
Simulation time	11415200716 ps
CPU time	357.12 seconds
Started	Aug 29 07:02:20 AM UTC 24
Finished	Aug 29 07:08:22 AM UTC 24
Peak memory	499956 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318459350 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.1318459350 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/37.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/37.kmac_smoke.3968624186
Short name	T518
Test name
Test status
Simulation time	9864556068 ps
CPU time	80.71 seconds
Started	Aug 29 07:02:03 AM UTC 24
Finished	Aug 29 07:03:26 AM UTC 24
Peak memory	235840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968624186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.3968624186 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/37.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/37.kmac_stress_all.1354530367
Short name	T689
Test name
Test status
Simulation time	60715141234 ps
CPU time	1583.8 seconds
Started	Aug 29 07:03:48 AM UTC 24
Finished	Aug 29 07:30:31 AM UTC 24
Peak memory	590044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354530367 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.1354530367 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/37.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/38.kmac_alert_test.3831509599
Short name	T534
Test name
Test status
Simulation time	38448859 ps
CPU time	1.24 seconds
Started	Aug 29 07:05:00 AM UTC 24
Finished	Aug 29 07:05:02 AM UTC 24
Peak memory	226292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831509599 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.3831509599 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/38.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/38.kmac_app.3600810988
Short name	T560
Test name
Test status
Simulation time	33126858573 ps
CPU time	200.07 seconds
Started	Aug 29 07:04:07 AM UTC 24
Finished	Aug 29 07:07:30 AM UTC 24
Peak memory	303332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600810988 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.3600810988 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/38.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/38.kmac_burst_write.2922038408
Short name	T698
Test name
Test status
Simulation time	40759007512 ps
CPU time	1891.54 seconds
Started	Aug 29 07:04:04 AM UTC 24
Finished	Aug 29 07:35:58 AM UTC 24
Peak memory	276696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922038408 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.2922038408 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/38.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/38.kmac_entropy_refresh.2403077174
Short name	T582
Test name
Test status
Simulation time	134218656137 ps
CPU time	423.63 seconds
Started	Aug 29 07:04:14 AM UTC 24
Finished	Aug 29 07:11:23 AM UTC 24
Peak memory	557340 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403077174 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.2403077174 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/38.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/38.kmac_error.2869181952
Short name	T581
Test name
Test status
Simulation time	3648773397 ps
CPU time	350.37 seconds
Started	Aug 29 07:04:37 AM UTC 24
Finished	Aug 29 07:10:32 AM UTC 24
Peak memory	334076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869181952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.2869181952 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/38.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/38.kmac_key_error.3568622434
Short name	T531
Test name
Test status
Simulation time	907381101 ps
CPU time	11.41 seconds
Started	Aug 29 07:04:39 AM UTC 24
Finished	Aug 29 07:04:51 AM UTC 24
Peak memory	229560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568622434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.3568622434 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/38.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/38.kmac_lc_escalation.1595286285
Short name	T532
Test name
Test status
Simulation time	81600180 ps
CPU time	2.15 seconds
Started	Aug 29 07:04:52 AM UTC 24
Finished	Aug 29 07:04:55 AM UTC 24
Peak memory	231820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595286285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.1595286285 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/38.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/38.kmac_long_msg_and_output.2382512290
Short name	T708
Test name
Test status
Simulation time	331722291364 ps
CPU time	2775.12 seconds
Started	Aug 29 07:03:53 AM UTC 24
Finished	Aug 29 07:50:39 AM UTC 24
Peak memory	3004780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382512290 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_and_output.2382512290 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/38.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/38.kmac_sideload.2295845951
Short name	T575
Test name
Test status
Simulation time	8722542203 ps
CPU time	357.5 seconds
Started	Aug 29 07:03:55 AM UTC 24
Finished	Aug 29 07:09:59 AM UTC 24
Peak memory	471340 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295845951 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.2295845951 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/38.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/38.kmac_smoke.206834330
Short name	T529
Test name
Test status
Simulation time	2116710559 ps
CPU time	42.69 seconds
Started	Aug 29 07:03:52 AM UTC 24
Finished	Aug 29 07:04:36 AM UTC 24
Peak memory	235776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206834330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.206834330 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/38.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/38.kmac_stress_all.4050188491
Short name	T674
Test name
Test status
Simulation time	47933878740 ps
CPU time	1111.55 seconds
Started	Aug 29 07:04:56 AM UTC 24
Finished	Aug 29 07:23:41 AM UTC 24
Peak memory	531060 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050188491 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.4050188491 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/38.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/39.kmac_alert_test.3567159152
Short name	T547
Test name
Test status
Simulation time	66163005 ps
CPU time	1.2 seconds
Started	Aug 29 07:06:28 AM UTC 24
Finished	Aug 29 07:06:31 AM UTC 24
Peak memory	224312 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567159152 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.3567159152 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/39.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/39.kmac_app.1395853048
Short name	T603
Test name
Test status
Simulation time	100537720063 ps
CPU time	487.11 seconds
Started	Aug 29 07:05:29 AM UTC 24
Finished	Aug 29 07:13:42 AM UTC 24
Peak memory	538864 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395853048 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.1395853048 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/39.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/39.kmac_burst_write.1983155326
Short name	T688
Test name
Test status
Simulation time	33988213745 ps
CPU time	1452.73 seconds
Started	Aug 29 07:05:28 AM UTC 24
Finished	Aug 29 07:29:57 AM UTC 24
Peak memory	272684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983155326 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.1983155326 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/39.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/39.kmac_entropy_refresh.2050082804
Short name	T580
Test name
Test status
Simulation time	7134381390 ps
CPU time	281.44 seconds
Started	Aug 29 07:05:46 AM UTC 24
Finished	Aug 29 07:10:31 AM UTC 24
Peak memory	315616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050082804 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.2050082804 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/39.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/39.kmac_error.1753120873
Short name	T590
Test name
Test status
Simulation time	39476883607 ps
CPU time	423.02 seconds
Started	Aug 29 07:05:56 AM UTC 24
Finished	Aug 29 07:13:05 AM UTC 24
Peak memory	354676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753120873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.1753120873 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/39.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/39.kmac_key_error.3655417097
Short name	T543
Test name
Test status
Simulation time	1114753353 ps
CPU time	9.43 seconds
Started	Aug 29 07:06:07 AM UTC 24
Finished	Aug 29 07:06:18 AM UTC 24
Peak memory	227512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655417097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.3655417097 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/39.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/39.kmac_lc_escalation.1093502658
Short name	T546
Test name
Test status
Simulation time	448515504 ps
CPU time	17.78 seconds
Started	Aug 29 07:06:11 AM UTC 24
Finished	Aug 29 07:06:30 AM UTC 24
Peak memory	252296 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093502658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.1093502658 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/39.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/39.kmac_long_msg_and_output.646879103
Short name	T718
Test name
Test status
Simulation time	242225055498 ps
CPU time	4837.09 seconds
Started	Aug 29 07:05:16 AM UTC 24
Finished	Aug 29 08:26:47 AM UTC 24
Peak memory	4374936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646879103 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_and_output.646879103 +enable_masking= 1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/39.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/39.kmac_sideload.917307179
Short name	T593
Test name
Test status
Simulation time	16177701586 ps
CPU time	466.35 seconds
Started	Aug 29 07:05:26 AM UTC 24
Finished	Aug 29 07:13:20 AM UTC 24
Peak memory	596188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917307179 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.917307179 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/39.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/39.kmac_smoke.109430394
Short name	T544
Test name
Test status
Simulation time	6631036674 ps
CPU time	82.38 seconds
Started	Aug 29 07:05:03 AM UTC 24
Finished	Aug 29 07:06:28 AM UTC 24
Peak memory	235828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109430394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.109430394 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/39.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/39.kmac_stress_all.1253701953
Short name	T714
Test name
Test status
Simulation time	139878672251 ps
CPU time	3267.14 seconds
Started	Aug 29 07:06:18 AM UTC 24
Finished	Aug 29 08:01:24 AM UTC 24
Peak memory	1282364 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253701953 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.1253701953 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/39.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/4.kmac_alert_test.376788569
Short name	T210
Test name
Test status
Simulation time	50316028 ps
CPU time	1.27 seconds
Started	Aug 29 06:20:26 AM UTC 24
Finished	Aug 29 06:20:28 AM UTC 24
Peak memory	225876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376788569 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.376788569 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/4.kmac_app.1576120993
Short name	T226
Test name
Test status
Simulation time	40467659961 ps
CPU time	271.98 seconds
Started	Aug 29 06:19:50 AM UTC 24
Finished	Aug 29 06:24:25 AM UTC 24
Peak memory	469244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576120993 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.1576120993 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/4.kmac_app_with_partial_data.298206528
Short name	T26
Test name
Test status
Simulation time	20082666784 ps
CPU time	140.76 seconds
Started	Aug 29 06:19:50 AM UTC 24
Finished	Aug 29 06:22:13 AM UTC 24
Peak memory	272600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298206528 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.298206528 +enable_masking= 1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_app_with_partial_data/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/4.kmac_burst_write.3608798960
Short name	T88
Test name
Test status
Simulation time	514988215 ps
CPU time	24.56 seconds
Started	Aug 29 06:19:26 AM UTC 24
Finished	Aug 29 06:19:52 AM UTC 24
Peak memory	235760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608798960 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.3608798960 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_mode_error.1772668243
Short name	T211
Test name
Test status
Simulation time	1577303716 ps
CPU time	27.64 seconds
Started	Aug 29 06:20:07 AM UTC 24
Finished	Aug 29 06:20:36 AM UTC 24
Peak memory	235472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772668243 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.1772668243 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_ready_error.4061386978
Short name	T181
Test name
Test status
Simulation time	2887203869 ps
CPU time	51.68 seconds
Started	Aug 29 06:20:10 AM UTC 24
Finished	Aug 29 06:21:04 AM UTC 24
Peak memory	233932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061386978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.4061386978 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_entropy_ready_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_refresh.3802292535
Short name	T98
Test name
Test status
Simulation time	34418745549 ps
CPU time	325.63 seconds
Started	Aug 29 06:19:51 AM UTC 24
Finished	Aug 29 06:25:21 AM UTC 24
Peak memory	458996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802292535 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.3802292535 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/4.kmac_error.2545574968
Short name	T28
Test name
Test status
Simulation time	3296383007 ps
CPU time	82.74 seconds
Started	Aug 29 06:19:53 AM UTC 24
Finished	Aug 29 06:21:18 AM UTC 24
Peak memory	262436 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545574968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.2545574968 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/4.kmac_key_error.94483748
Short name	T57
Test name
Test status
Simulation time	1647819779 ps
CPU time	12.17 seconds
Started	Aug 29 06:20:01 AM UTC 24
Finished	Aug 29 06:20:14 AM UTC 24
Peak memory	227648 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94483748 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.94483748 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/4.kmac_lc_escalation.3670202166
Short name	T45
Test name
Test status
Simulation time	68294695 ps
CPU time	2.14 seconds
Started	Aug 29 06:20:15 AM UTC 24
Finished	Aug 29 06:20:19 AM UTC 24
Peak memory	233896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670202166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.3670202166 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/4.kmac_long_msg_and_output.1011154600
Short name	T549
Test name
Test status
Simulation time	129300430094 ps
CPU time	2808.78 seconds
Started	Aug 29 06:19:21 AM UTC 24
Finished	Aug 29 07:06:43 AM UTC 24
Peak memory	2756908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011154600 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and_output.1011154600 +enable_masking =1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/4.kmac_mubi.4270607156
Short name	T34
Test name
Test status
Simulation time	1824010264 ps
CPU time	135.39 seconds
Started	Aug 29 06:19:53 AM UTC 24
Finished	Aug 29 06:22:11 AM UTC 24
Peak memory	266816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270607156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.4270607156 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/4.kmac_sec_cm.2200132766
Short name	T129
Test name
Test status
Simulation time	14081336704 ps
CPU time	80.98 seconds
Started	Aug 29 06:20:22 AM UTC 24
Finished	Aug 29 06:21:46 AM UTC 24
Peak memory	280672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200132766 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.2200132766 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/4.kmac_sideload.2857536910
Short name	T29
Test name
Test status
Simulation time	5770816890 ps
CPU time	261.34 seconds
Started	Aug 29 06:19:24 AM UTC 24
Finished	Aug 29 06:23:50 AM UTC 24
Peak memory	313696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857536910 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.2857536910 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/4.kmac_smoke.899872998
Short name	T203
Test name
Test status
Simulation time	9066104134 ps
CPU time	106.34 seconds
Started	Aug 29 06:19:21 AM UTC 24
Finished	Aug 29 06:21:09 AM UTC 24
Peak memory	237828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899872998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.899872998 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac.1627893854
Short name	T59
Test name
Test status
Simulation time	76277289 ps
CPU time	3.2 seconds
Started	Aug 29 06:19:44 AM UTC 24
Finished	Aug 29 06:19:49 AM UTC 24
Peak memory	229804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627893854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac.1627893854 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac_xof.621561072
Short name	T131
Test name
Test status
Simulation time	625615663 ps
CPU time	3.93 seconds
Started	Aug 29 06:19:47 AM UTC 24
Finished	Aug 29 06:19:52 AM UTC 24
Peak memory	235776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621561072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vector s_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac_xof.621561072 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac_xof/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_224.3330763405
Short name	T596
Test name
Test status
Simulation time	102863493985 ps
CPU time	3202.75 seconds
Started	Aug 29 06:19:26 AM UTC 24
Finished	Aug 29 07:13:26 AM UTC 24
Peak memory	3221660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330763405 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.3330763405 +enab le_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_224/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_256.1275807956
Short name	T519
Test name
Test status
Simulation time	123839019879 ps
CPU time	2604.25 seconds
Started	Aug 29 06:19:32 AM UTC 24
Finished	Aug 29 07:03:26 AM UTC 24
Peak memory	3012768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275807956 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.1275807956 +enab le_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_256/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_384.808159746
Short name	T132
Test name
Test status
Simulation time	1398523385 ps
CPU time	30.7 seconds
Started	Aug 29 06:19:34 AM UTC 24
Finished	Aug 29 06:20:06 AM UTC 24
Peak memory	243820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808159746 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.808159746 +enable _masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_384/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_512.70993379
Short name	T133
Test name
Test status
Simulation time	3528605718 ps
CPU time	26.81 seconds
Started	Aug 29 06:19:38 AM UTC 24
Finished	Aug 29 06:20:06 AM UTC 24
Peak memory	235808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70993379 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.70993379 +enable_m asking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_512/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_128.2058321611
Short name	T224
Test name
Test status
Simulation time	28339197576 ps
CPU time	263.97 seconds
Started	Aug 29 06:19:38 AM UTC 24
Finished	Aug 29 06:24:06 AM UTC 24
Peak memory	444668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058321611 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.2058321611 +e nable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_128/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_256.2729740723
Short name	T535
Test name
Test status
Simulation time	76386527333 ps
CPU time	2703.55 seconds
Started	Aug 29 06:19:40 AM UTC 24
Finished	Aug 29 07:05:15 AM UTC 24
Peak memory	2984100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729740723 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.2729740723 +e nable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_256/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/40.kmac_alert_test.1054448714
Short name	T556
Test name
Test status
Simulation time	25162946 ps
CPU time	1.36 seconds
Started	Aug 29 07:07:06 AM UTC 24
Finished	Aug 29 07:07:08 AM UTC 24
Peak memory	226472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054448714 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.1054448714 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/40.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/40.kmac_app.2562447417
Short name	T604
Test name
Test status
Simulation time	43016573490 ps
CPU time	420.81 seconds
Started	Aug 29 07:06:44 AM UTC 24
Finished	Aug 29 07:13:51 AM UTC 24
Peak memory	454944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562447417 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.2562447417 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/40.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/40.kmac_burst_write.2251179046
Short name	T692
Test name
Test status
Simulation time	27917859463 ps
CPU time	1478.88 seconds
Started	Aug 29 07:06:41 AM UTC 24
Finished	Aug 29 07:31:37 AM UTC 24
Peak memory	272620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251179046 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.2251179046 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/40.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/40.kmac_entropy_refresh.1698932507
Short name	T574
Test name
Test status
Simulation time	30544446216 ps
CPU time	181.68 seconds
Started	Aug 29 07:06:48 AM UTC 24
Finished	Aug 29 07:09:53 AM UTC 24
Peak memory	303440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698932507 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.1698932507 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/40.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/40.kmac_error.3036032197
Short name	T629
Test name
Test status
Simulation time	10908526748 ps
CPU time	586.2 seconds
Started	Aug 29 07:06:52 AM UTC 24
Finished	Aug 29 07:16:47 AM UTC 24
Peak memory	399616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036032197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.3036032197 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/40.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/40.kmac_key_error.2113551997
Short name	T557
Test name
Test status
Simulation time	7174846211 ps
CPU time	18.26 seconds
Started	Aug 29 07:06:55 AM UTC 24
Finished	Aug 29 07:07:15 AM UTC 24
Peak memory	227656 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113551997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.2113551997 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/40.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/40.kmac_lc_escalation.2935832542
Short name	T555
Test name
Test status
Simulation time	130187579 ps
CPU time	2.1 seconds
Started	Aug 29 07:07:01 AM UTC 24
Finished	Aug 29 07:07:04 AM UTC 24
Peak memory	231812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935832542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.2935832542 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/40.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/40.kmac_long_msg_and_output.30644443
Short name	T645
Test name
Test status
Simulation time	71399942553 ps
CPU time	754.79 seconds
Started	Aug 29 07:06:32 AM UTC 24
Finished	Aug 29 07:19:17 AM UTC 24
Peak memory	573732 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30644443 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_and_output.30644443 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/40.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/40.kmac_sideload.2468878181
Short name	T620
Test name
Test status
Simulation time	63498139738 ps
CPU time	512.2 seconds
Started	Aug 29 07:06:32 AM UTC 24
Finished	Aug 29 07:15:11 AM UTC 24
Peak memory	596204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468878181 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.2468878181 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/40.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/40.kmac_smoke.776943782
Short name	T548
Test name
Test status
Simulation time	286574445 ps
CPU time	8.57 seconds
Started	Aug 29 07:06:31 AM UTC 24
Finished	Aug 29 07:06:40 AM UTC 24
Peak memory	235772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776943782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.776943782 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/40.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/40.kmac_stress_all.3570592749
Short name	T691
Test name
Test status
Simulation time	72114454213 ps
CPU time	1437.76 seconds
Started	Aug 29 07:07:01 AM UTC 24
Finished	Aug 29 07:31:17 AM UTC 24
Peak memory	1509620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570592749 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.3570592749 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/40.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/41.kmac_alert_test.92121745
Short name	T568
Test name
Test status
Simulation time	46880414 ps
CPU time	1.09 seconds
Started	Aug 29 07:08:21 AM UTC 24
Finished	Aug 29 07:08:23 AM UTC 24
Peak memory	226236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92121745 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.92121745 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/41.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/41.kmac_app.4145549433
Short name	T594
Test name
Test status
Simulation time	60987632396 ps
CPU time	343.58 seconds
Started	Aug 29 07:07:31 AM UTC 24
Finished	Aug 29 07:13:20 AM UTC 24
Peak memory	432456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145549433 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.4145549433 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/41.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/41.kmac_burst_write.3056911769
Short name	T700
Test name
Test status
Simulation time	58935064870 ps
CPU time	1805.27 seconds
Started	Aug 29 07:07:29 AM UTC 24
Finished	Aug 29 07:37:57 AM UTC 24
Peak memory	274740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056911769 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.3056911769 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/41.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/41.kmac_entropy_refresh.2807181867
Short name	T563
Test name
Test status
Simulation time	12485658551 ps
CPU time	32.43 seconds
Started	Aug 29 07:07:31 AM UTC 24
Finished	Aug 29 07:08:05 AM UTC 24
Peak memory	252316 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807181867 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.2807181867 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/41.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/41.kmac_error.982146102
Short name	T585
Test name
Test status
Simulation time	14397095841 ps
CPU time	234.48 seconds
Started	Aug 29 07:07:47 AM UTC 24
Finished	Aug 29 07:11:46 AM UTC 24
Peak memory	391508 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982146102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.982146102 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/41.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/41.kmac_key_error.1571651576
Short name	T566
Test name
Test status
Simulation time	3096447726 ps
CPU time	12.47 seconds
Started	Aug 29 07:08:06 AM UTC 24
Finished	Aug 29 07:08:20 AM UTC 24
Peak memory	227576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571651576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.1571651576 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/41.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/41.kmac_lc_escalation.3029623646
Short name	T565
Test name
Test status
Simulation time	133181948 ps
CPU time	1.98 seconds
Started	Aug 29 07:08:17 AM UTC 24
Finished	Aug 29 07:08:20 AM UTC 24
Peak memory	231360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029623646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.3029623646 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/41.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/41.kmac_long_msg_and_output.2792464791
Short name	T719
Test name
Test status
Simulation time	374317528838 ps
CPU time	5210.84 seconds
Started	Aug 29 07:07:16 AM UTC 24
Finished	Aug 29 08:35:04 AM UTC 24
Peak memory	4802896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792464791 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_and_output.2792464791 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/41.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/41.kmac_sideload.1262557263
Short name	T618
Test name
Test status
Simulation time	263086869632 ps
CPU time	449.79 seconds
Started	Aug 29 07:07:18 AM UTC 24
Finished	Aug 29 07:14:54 AM UTC 24
Peak memory	504120 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262557263 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.1262557263 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/41.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/41.kmac_smoke.2511112654
Short name	T564
Test name
Test status
Simulation time	1369388401 ps
CPU time	64.92 seconds
Started	Aug 29 07:07:09 AM UTC 24
Finished	Aug 29 07:08:15 AM UTC 24
Peak memory	235768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511112654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.2511112654 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/41.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/41.kmac_stress_all.452851109
Short name	T572
Test name
Test status
Simulation time	1132389347 ps
CPU time	75.66 seconds
Started	Aug 29 07:08:21 AM UTC 24
Finished	Aug 29 07:09:38 AM UTC 24
Peak memory	268992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452851109 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.452851109 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/41.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/42.kmac_alert_test.1910381278
Short name	T579
Test name
Test status
Simulation time	18274348 ps
CPU time	1.32 seconds
Started	Aug 29 07:10:19 AM UTC 24
Finished	Aug 29 07:10:21 AM UTC 24
Peak memory	226052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910381278 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.1910381278 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/42.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/42.kmac_app.4163545570
Short name	T592
Test name
Test status
Simulation time	21406781422 ps
CPU time	235.46 seconds
Started	Aug 29 07:09:14 AM UTC 24
Finished	Aug 29 07:13:13 AM UTC 24
Peak memory	373056 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163545570 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.4163545570 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/42.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/42.kmac_burst_write.3121231740
Short name	T624
Test name
Test status
Simulation time	17479923475 ps
CPU time	371.35 seconds
Started	Aug 29 07:09:13 AM UTC 24
Finished	Aug 29 07:15:30 AM UTC 24
Peak memory	246128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121231740 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.3121231740 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/42.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/42.kmac_entropy_refresh.3437812239
Short name	T591
Test name
Test status
Simulation time	12587413051 ps
CPU time	208.02 seconds
Started	Aug 29 07:09:39 AM UTC 24
Finished	Aug 29 07:13:11 AM UTC 24
Peak memory	286968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437812239 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.3437812239 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/42.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/42.kmac_error.1783443627
Short name	T638
Test name
Test status
Simulation time	15902712879 ps
CPU time	504.47 seconds
Started	Aug 29 07:09:47 AM UTC 24
Finished	Aug 29 07:18:18 AM UTC 24
Peak memory	377132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783443627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.1783443627 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/42.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/42.kmac_key_error.3072210298
Short name	T576
Test name
Test status
Simulation time	9113342248 ps
CPU time	21.52 seconds
Started	Aug 29 07:09:54 AM UTC 24
Finished	Aug 29 07:10:17 AM UTC 24
Peak memory	229628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072210298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.3072210298 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/42.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/42.kmac_lc_escalation.2474750009
Short name	T578
Test name
Test status
Simulation time	2719743765 ps
CPU time	17.58 seconds
Started	Aug 29 07:10:00 AM UTC 24
Finished	Aug 29 07:10:19 AM UTC 24
Peak memory	248264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474750009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.2474750009 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/42.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/42.kmac_long_msg_and_output.1611675473
Short name	T704
Test name
Test status
Simulation time	56759767263 ps
CPU time	2256.16 seconds
Started	Aug 29 07:08:24 AM UTC 24
Finished	Aug 29 07:46:26 AM UTC 24
Peak memory	2482548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611675473 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_and_output.1611675473 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/42.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/42.kmac_sideload.100367323
Short name	T588
Test name
Test status
Simulation time	9249090582 ps
CPU time	232.85 seconds
Started	Aug 29 07:08:52 AM UTC 24
Finished	Aug 29 07:12:49 AM UTC 24
Peak memory	299376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100367323 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.100367323 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/42.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/42.kmac_smoke.3907043223
Short name	T573
Test name
Test status
Simulation time	6635226438 ps
CPU time	81.36 seconds
Started	Aug 29 07:08:23 AM UTC 24
Finished	Aug 29 07:09:46 AM UTC 24
Peak memory	233960 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907043223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.3907043223 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/42.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/42.kmac_stress_all.2097917596
Short name	T687
Test name
Test status
Simulation time	143932969303 ps
CPU time	1165.22 seconds
Started	Aug 29 07:10:18 AM UTC 24
Finished	Aug 29 07:29:57 AM UTC 24
Peak memory	938272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097917596 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.2097917596 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/42.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/43.kmac_alert_test.1921161530
Short name	T589
Test name
Test status
Simulation time	24609600 ps
CPU time	1.32 seconds
Started	Aug 29 07:12:49 AM UTC 24
Finished	Aug 29 07:12:52 AM UTC 24
Peak memory	226052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921161530 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.1921161530 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/43.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/43.kmac_app.1114610176
Short name	T626
Test name
Test status
Simulation time	8660172019 ps
CPU time	271.54 seconds
Started	Aug 29 07:11:24 AM UTC 24
Finished	Aug 29 07:16:00 AM UTC 24
Peak memory	368944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114610176 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.1114610176 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/43.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/43.kmac_burst_write.1384798723
Short name	T683
Test name
Test status
Simulation time	39095153354 ps
CPU time	1013.53 seconds
Started	Aug 29 07:10:33 AM UTC 24
Finished	Aug 29 07:27:40 AM UTC 24
Peak memory	258356 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384798723 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.1384798723 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/43.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/43.kmac_entropy_refresh.3489519736
Short name	T599
Test name
Test status
Simulation time	7029027022 ps
CPU time	128.24 seconds
Started	Aug 29 07:11:26 AM UTC 24
Finished	Aug 29 07:13:37 AM UTC 24
Peak memory	264500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489519736 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.3489519736 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/43.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/43.kmac_error.4158022589
Short name	T646
Test name
Test status
Simulation time	21001758541 ps
CPU time	462.45 seconds
Started	Aug 29 07:11:29 AM UTC 24
Finished	Aug 29 07:19:18 AM UTC 24
Peak memory	377084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158022589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.4158022589 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/43.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/43.kmac_key_error.3766619724
Short name	T586
Test name
Test status
Simulation time	1442995362 ps
CPU time	18.89 seconds
Started	Aug 29 07:11:46 AM UTC 24
Finished	Aug 29 07:12:06 AM UTC 24
Peak memory	227512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766619724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.3766619724 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/43.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/43.kmac_lc_escalation.257579345
Short name	T587
Test name
Test status
Simulation time	30123586 ps
CPU time	1.95 seconds
Started	Aug 29 07:12:07 AM UTC 24
Finished	Aug 29 07:12:10 AM UTC 24
Peak memory	231304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257579345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.257579345 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/43.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/43.kmac_long_msg_and_output.4264783498
Short name	T717
Test name
Test status
Simulation time	117726789159 ps
CPU time	3764.01 seconds
Started	Aug 29 07:10:22 AM UTC 24
Finished	Aug 29 08:13:51 AM UTC 24
Peak memory	1728744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264783498 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_and_output.4264783498 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/43.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/43.kmac_sideload.386701044
Short name	T595
Test name
Test status
Simulation time	10541358148 ps
CPU time	166.67 seconds
Started	Aug 29 07:10:32 AM UTC 24
Finished	Aug 29 07:13:22 AM UTC 24
Peak memory	329932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386701044 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.386701044 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/43.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/43.kmac_smoke.2645309560
Short name	T583
Test name
Test status
Simulation time	1468064474 ps
CPU time	64.23 seconds
Started	Aug 29 07:10:19 AM UTC 24
Finished	Aug 29 07:11:25 AM UTC 24
Peak memory	235900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645309560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.2645309560 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/43.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/43.kmac_stress_all.1167860140
Short name	T702
Test name
Test status
Simulation time	65611654096 ps
CPU time	1777.32 seconds
Started	Aug 29 07:12:11 AM UTC 24
Finished	Aug 29 07:42:10 AM UTC 24
Peak memory	1036960 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167860140 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.1167860140 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/43.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/44.kmac_alert_test.3888201554
Short name	T601
Test name
Test status
Simulation time	15768398 ps
CPU time	1.24 seconds
Started	Aug 29 07:13:37 AM UTC 24
Finished	Aug 29 07:13:40 AM UTC 24
Peak memory	226292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888201554 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.3888201554 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/44.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/44.kmac_app.3387696354
Short name	T636
Test name
Test status
Simulation time	9575380636 ps
CPU time	262.93 seconds
Started	Aug 29 07:13:21 AM UTC 24
Finished	Aug 29 07:17:48 AM UTC 24
Peak memory	455012 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387696354 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.3387696354 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/44.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/44.kmac_burst_write.1470285333
Short name	T623
Test name
Test status
Simulation time	8779089789 ps
CPU time	128.95 seconds
Started	Aug 29 07:13:14 AM UTC 24
Finished	Aug 29 07:15:25 AM UTC 24
Peak memory	235816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470285333 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.1470285333 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/44.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/44.kmac_entropy_refresh.2263352789
Short name	T640
Test name
Test status
Simulation time	4963844888 ps
CPU time	309.84 seconds
Started	Aug 29 07:13:21 AM UTC 24
Finished	Aug 29 07:18:35 AM UTC 24
Peak memory	330084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263352789 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.2263352789 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/44.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/44.kmac_error.92538484
Short name	T610
Test name
Test status
Simulation time	25863432744 ps
CPU time	62.92 seconds
Started	Aug 29 07:13:23 AM UTC 24
Finished	Aug 29 07:14:28 AM UTC 24
Peak memory	285012 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92538484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.92538484 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/44.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/44.kmac_key_error.2603437762
Short name	T602
Test name
Test status
Simulation time	889193743 ps
CPU time	12.87 seconds
Started	Aug 29 07:13:26 AM UTC 24
Finished	Aug 29 07:13:40 AM UTC 24
Peak memory	227576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603437762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.2603437762 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/44.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/44.kmac_lc_escalation.1474039726
Short name	T600
Test name
Test status
Simulation time	77037668 ps
CPU time	1.93 seconds
Started	Aug 29 07:13:35 AM UTC 24
Finished	Aug 29 07:13:38 AM UTC 24
Peak memory	231304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474039726 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.1474039726 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/44.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/44.kmac_long_msg_and_output.3267502947
Short name	T709
Test name
Test status
Simulation time	50056913515 ps
CPU time	2321.78 seconds
Started	Aug 29 07:13:06 AM UTC 24
Finished	Aug 29 07:52:15 AM UTC 24
Peak memory	2382096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267502947 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_and_output.3267502947 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/44.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/44.kmac_sideload.2304821146
Short name	T670
Test name
Test status
Simulation time	89479808038 ps
CPU time	557.86 seconds
Started	Aug 29 07:13:12 AM UTC 24
Finished	Aug 29 07:22:36 AM UTC 24
Peak memory	694560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304821146 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.2304821146 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/44.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/44.kmac_smoke.1688098150
Short name	T598
Test name
Test status
Simulation time	1046034012 ps
CPU time	42.4 seconds
Started	Aug 29 07:12:53 AM UTC 24
Finished	Aug 29 07:13:36 AM UTC 24
Peak memory	235772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688098150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.1688098150 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/44.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/45.kmac_alert_test.934426266
Short name	T612
Test name
Test status
Simulation time	20190864 ps
CPU time	1.36 seconds
Started	Aug 29 07:14:29 AM UTC 24
Finished	Aug 29 07:14:31 AM UTC 24
Peak memory	226048 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934426266 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.934426266 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/45.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/45.kmac_app.2252164480
Short name	T654
Test name
Test status
Simulation time	20192918018 ps
CPU time	363.15 seconds
Started	Aug 29 07:13:52 AM UTC 24
Finished	Aug 29 07:20:00 AM UTC 24
Peak memory	334128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252164480 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.2252164480 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/45.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/45.kmac_burst_write.4011783317
Short name	T671
Test name
Test status
Simulation time	9857084598 ps
CPU time	529.13 seconds
Started	Aug 29 07:13:43 AM UTC 24
Finished	Aug 29 07:22:39 AM UTC 24
Peak memory	252200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011783317 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.4011783317 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/45.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/45.kmac_error.574175961
Short name	T661
Test name
Test status
Simulation time	67217905653 ps
CPU time	386.38 seconds
Started	Aug 29 07:14:01 AM UTC 24
Finished	Aug 29 07:20:33 AM UTC 24
Peak memory	522488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574175961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.574175961 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/45.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/45.kmac_key_error.2970933805
Short name	T609
Test name
Test status
Simulation time	2553159777 ps
CPU time	6.29 seconds
Started	Aug 29 07:14:17 AM UTC 24
Finished	Aug 29 07:14:25 AM UTC 24
Peak memory	227608 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970933805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.2970933805 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/45.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/45.kmac_lc_escalation.2172908992
Short name	T611
Test name
Test status
Simulation time	414017813 ps
CPU time	6.88 seconds
Started	Aug 29 07:14:21 AM UTC 24
Finished	Aug 29 07:14:28 AM UTC 24
Peak memory	240132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172908992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.2172908992 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/45.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/45.kmac_long_msg_and_output.4084354605
Short name	T637
Test name
Test status
Simulation time	20352153844 ps
CPU time	260.04 seconds
Started	Aug 29 07:13:41 AM UTC 24
Finished	Aug 29 07:18:04 AM UTC 24
Peak memory	586024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084354605 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_and_output.4084354605 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/45.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/45.kmac_sideload.571163929
Short name	T615
Test name
Test status
Simulation time	3109674278 ps
CPU time	66.86 seconds
Started	Aug 29 07:13:41 AM UTC 24
Finished	Aug 29 07:14:49 AM UTC 24
Peak memory	252224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571163929 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.571163929 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/45.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/45.kmac_smoke.3463691892
Short name	T619
Test name
Test status
Simulation time	10531014578 ps
CPU time	72.82 seconds
Started	Aug 29 07:13:40 AM UTC 24
Finished	Aug 29 07:14:54 AM UTC 24
Peak memory	235772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463691892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.3463691892 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/45.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/45.kmac_stress_all.56998053
Short name	T651
Test name
Test status
Simulation time	11072529895 ps
CPU time	323.26 seconds
Started	Aug 29 07:14:26 AM UTC 24
Finished	Aug 29 07:19:53 AM UTC 24
Peak memory	508728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56998053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.56998053 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/45.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/46.kmac_alert_test.3259999874
Short name	T622
Test name
Test status
Simulation time	16583140 ps
CPU time	1.27 seconds
Started	Aug 29 07:15:12 AM UTC 24
Finished	Aug 29 07:15:14 AM UTC 24
Peak memory	225212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259999874 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.3259999874 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/46.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/46.kmac_app.3646997723
Short name	T627
Test name
Test status
Simulation time	12674833970 ps
CPU time	79.66 seconds
Started	Aug 29 07:14:50 AM UTC 24
Finished	Aug 29 07:16:12 AM UTC 24
Peak memory	280900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646997723 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.3646997723 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/46.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/46.kmac_burst_write.2976897345
Short name	T686
Test name
Test status
Simulation time	105703951330 ps
CPU time	814.83 seconds
Started	Aug 29 07:14:44 AM UTC 24
Finished	Aug 29 07:28:30 AM UTC 24
Peak memory	254320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976897345 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.2976897345 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/46.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/46.kmac_entropy_refresh.2712305672
Short name	T653
Test name
Test status
Simulation time	17959046453 ps
CPU time	301.8 seconds
Started	Aug 29 07:14:53 AM UTC 24
Finished	Aug 29 07:20:00 AM UTC 24
Peak memory	407860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712305672 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.2712305672 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/46.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/46.kmac_error.120833673
Short name	T669
Test name
Test status
Simulation time	11175229227 ps
CPU time	454.72 seconds
Started	Aug 29 07:14:55 AM UTC 24
Finished	Aug 29 07:22:36 AM UTC 24
Peak memory	514304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120833673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.120833673 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/46.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/46.kmac_key_error.2120408786
Short name	T621
Test name
Test status
Simulation time	8305384715 ps
CPU time	16.84 seconds
Started	Aug 29 07:14:55 AM UTC 24
Finished	Aug 29 07:15:13 AM UTC 24
Peak memory	227680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120408786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.2120408786 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/46.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/46.kmac_lc_escalation.772764498
Short name	T111
Test name
Test status
Simulation time	46814962 ps
CPU time	2.14 seconds
Started	Aug 29 07:14:56 AM UTC 24
Finished	Aug 29 07:14:59 AM UTC 24
Peak memory	231828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772764498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.772764498 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/46.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/46.kmac_long_msg_and_output.2998274586
Short name	T711
Test name
Test status
Simulation time	49950610210 ps
CPU time	2456.73 seconds
Started	Aug 29 07:14:32 AM UTC 24
Finished	Aug 29 07:55:58 AM UTC 24
Peak memory	2568428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998274586 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_and_output.2998274586 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/46.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/46.kmac_sideload.19470168
Short name	T677
Test name
Test status
Simulation time	212016592930 ps
CPU time	573.83 seconds
Started	Aug 29 07:14:32 AM UTC 24
Finished	Aug 29 07:24:13 AM UTC 24
Peak memory	624884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19470168 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.19470168 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/46.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/46.kmac_smoke.2699802092
Short name	T617
Test name
Test status
Simulation time	4378020480 ps
CPU time	23.05 seconds
Started	Aug 29 07:14:29 AM UTC 24
Finished	Aug 29 07:14:53 AM UTC 24
Peak memory	235836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699802092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.2699802092 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/46.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/46.kmac_stress_all.428088983
Short name	T633
Test name
Test status
Simulation time	2474558039 ps
CPU time	135.62 seconds
Started	Aug 29 07:15:00 AM UTC 24
Finished	Aug 29 07:17:18 AM UTC 24
Peak memory	235776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428088983 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.428088983 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/46.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/47.kmac_alert_test.2566057256
Short name	T632
Test name
Test status
Simulation time	56124521 ps
CPU time	1.29 seconds
Started	Aug 29 07:16:56 AM UTC 24
Finished	Aug 29 07:16:59 AM UTC 24
Peak memory	226052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566057256 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.2566057256 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/47.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/47.kmac_app.630824394
Short name	T656
Test name
Test status
Simulation time	7525301533 ps
CPU time	263.5 seconds
Started	Aug 29 07:15:45 AM UTC 24
Finished	Aug 29 07:20:12 AM UTC 24
Peak memory	379248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630824394 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.630824394 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/47.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/47.kmac_burst_write.2819247291
Short name	T673
Test name
Test status
Simulation time	8964738568 ps
CPU time	456.62 seconds
Started	Aug 29 07:15:30 AM UTC 24
Finished	Aug 29 07:23:14 AM UTC 24
Peak memory	246064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819247291 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.2819247291 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/47.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/47.kmac_entropy_refresh.3238378633
Short name	T662
Test name
Test status
Simulation time	7043586575 ps
CPU time	277.61 seconds
Started	Aug 29 07:16:01 AM UTC 24
Finished	Aug 29 07:20:43 AM UTC 24
Peak memory	311600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238378633 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.3238378633 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/47.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/47.kmac_error.2533434284
Short name	T675
Test name
Test status
Simulation time	14658166676 ps
CPU time	445.01 seconds
Started	Aug 29 07:16:13 AM UTC 24
Finished	Aug 29 07:23:44 AM UTC 24
Peak memory	524612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533434284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.2533434284 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/47.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/47.kmac_key_error.2165013839
Short name	T630
Test name
Test status
Simulation time	548301934 ps
CPU time	2.98 seconds
Started	Aug 29 07:16:46 AM UTC 24
Finished	Aug 29 07:16:50 AM UTC 24
Peak memory	227360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165013839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.2165013839 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/47.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/47.kmac_lc_escalation.142365260
Short name	T631
Test name
Test status
Simulation time	129668474 ps
CPU time	7.25 seconds
Started	Aug 29 07:16:47 AM UTC 24
Finished	Aug 29 07:16:56 AM UTC 24
Peak memory	231764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142365260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.142365260 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/47.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/47.kmac_long_msg_and_output.1999801053
Short name	T699
Test name
Test status
Simulation time	114425559257 ps
CPU time	1343.58 seconds
Started	Aug 29 07:15:15 AM UTC 24
Finished	Aug 29 07:37:55 AM UTC 24
Peak memory	1589576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999801053 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_and_output.1999801053 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/47.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/47.kmac_sideload.288929515
Short name	T649
Test name
Test status
Simulation time	21518484419 ps
CPU time	248.51 seconds
Started	Aug 29 07:15:26 AM UTC 24
Finished	Aug 29 07:19:39 AM UTC 24
Peak memory	299252 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288929515 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.288929515 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/47.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/47.kmac_smoke.2489194315
Short name	T628
Test name
Test status
Simulation time	1870294200 ps
CPU time	89.83 seconds
Started	Aug 29 07:15:13 AM UTC 24
Finished	Aug 29 07:16:45 AM UTC 24
Peak memory	235708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489194315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.2489194315 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/47.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/47.kmac_stress_all.3272501404
Short name	T679
Test name
Test status
Simulation time	13044640246 ps
CPU time	447.87 seconds
Started	Aug 29 07:16:51 AM UTC 24
Finished	Aug 29 07:24:25 AM UTC 24
Peak memory	328316 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272501404 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.3272501404 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/47.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/48.kmac_alert_test.2295144303
Short name	T644
Test name
Test status
Simulation time	20241436 ps
CPU time	1.29 seconds
Started	Aug 29 07:18:44 AM UTC 24
Finished	Aug 29 07:18:46 AM UTC 24
Peak memory	224972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295144303 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.2295144303 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/48.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/48.kmac_app.3269625033
Short name	T658
Test name
Test status
Simulation time	4318458389 ps
CPU time	141.31 seconds
Started	Aug 29 07:17:49 AM UTC 24
Finished	Aug 29 07:20:13 AM UTC 24
Peak memory	315656 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269625033 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.3269625033 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/48.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/48.kmac_burst_write.3183398574
Short name	T639
Test name
Test status
Simulation time	751086906 ps
CPU time	44.95 seconds
Started	Aug 29 07:17:43 AM UTC 24
Finished	Aug 29 07:18:29 AM UTC 24
Peak memory	233852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183398574 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.3183398574 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/48.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/48.kmac_entropy_refresh.3729399171
Short name	T681
Test name
Test status
Simulation time	8793157787 ps
CPU time	501.74 seconds
Started	Aug 29 07:18:05 AM UTC 24
Finished	Aug 29 07:26:34 AM UTC 24
Peak memory	375008 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729399171 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.3729399171 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/48.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/48.kmac_error.1246758794
Short name	T666
Test name
Test status
Simulation time	8884886216 ps
CPU time	221.7 seconds
Started	Aug 29 07:18:19 AM UTC 24
Finished	Aug 29 07:22:05 AM UTC 24
Peak memory	301304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246758794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.1246758794 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/48.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/48.kmac_key_error.3227941228
Short name	T641
Test name
Test status
Simulation time	878547380 ps
CPU time	10.22 seconds
Started	Aug 29 07:18:30 AM UTC 24
Finished	Aug 29 07:18:42 AM UTC 24
Peak memory	227612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227941228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.3227941228 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/48.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/48.kmac_lc_escalation.12816070
Short name	T642
Test name
Test status
Simulation time	674602954 ps
CPU time	4.8 seconds
Started	Aug 29 07:18:36 AM UTC 24
Finished	Aug 29 07:18:42 AM UTC 24
Peak memory	235888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12816070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.12816070 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/48.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/48.kmac_long_msg_and_output.2689689402
Short name	T715
Test name
Test status
Simulation time	24230880445 ps
CPU time	2911.63 seconds
Started	Aug 29 07:17:19 AM UTC 24
Finished	Aug 29 08:06:25 AM UTC 24
Peak memory	1509620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689689402 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_and_output.2689689402 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/48.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/48.kmac_sideload.484416980
Short name	T665
Test name
Test status
Simulation time	2864702343 ps
CPU time	241.79 seconds
Started	Aug 29 07:17:32 AM UTC 24
Finished	Aug 29 07:21:37 AM UTC 24
Peak memory	317672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484416980 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.484416980 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/48.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/48.kmac_smoke.508588593
Short name	T635
Test name
Test status
Simulation time	7193279737 ps
CPU time	41.03 seconds
Started	Aug 29 07:16:59 AM UTC 24
Finished	Aug 29 07:17:42 AM UTC 24
Peak memory	235776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508588593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.508588593 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/48.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/48.kmac_stress_all.3695809293
Short name	T706
Test name
Test status
Simulation time	46518722386 ps
CPU time	1755.49 seconds
Started	Aug 29 07:18:43 AM UTC 24
Finished	Aug 29 07:48:19 AM UTC 24
Peak memory	1157344 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695809293 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.3695809293 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/48.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/49.kmac_alert_test.3769052377
Short name	T655
Test name
Test status
Simulation time	19865753 ps
CPU time	1.22 seconds
Started	Aug 29 07:20:01 AM UTC 24
Finished	Aug 29 07:20:03 AM UTC 24
Peak memory	224492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769052377 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.3769052377 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/49.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/49.kmac_app.221074935
Short name	T680
Test name
Test status
Simulation time	44496477544 ps
CPU time	402.93 seconds
Started	Aug 29 07:19:25 AM UTC 24
Finished	Aug 29 07:26:14 AM UTC 24
Peak memory	491832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221074935 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.221074935 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/49.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/49.kmac_burst_write.3029129357
Short name	T696
Test name
Test status
Simulation time	23019970107 ps
CPU time	944.52 seconds
Started	Aug 29 07:19:19 AM UTC 24
Finished	Aug 29 07:35:16 AM UTC 24
Peak memory	258344 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029129357 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.3029129357 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/49.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/49.kmac_entropy_refresh.4269043327
Short name	T663
Test name
Test status
Simulation time	1285880731 ps
CPU time	93.62 seconds
Started	Aug 29 07:19:27 AM UTC 24
Finished	Aug 29 07:21:03 AM UTC 24
Peak memory	256256 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269043327 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.4269043327 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/49.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/49.kmac_error.3591152896
Short name	T684
Test name
Test status
Simulation time	25061488102 ps
CPU time	508.55 seconds
Started	Aug 29 07:19:40 AM UTC 24
Finished	Aug 29 07:28:15 AM UTC 24
Peak memory	612676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591152896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.3591152896 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/49.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/49.kmac_key_error.2810053842
Short name	T652
Test name
Test status
Simulation time	575616799 ps
CPU time	4.11 seconds
Started	Aug 29 07:19:53 AM UTC 24
Finished	Aug 29 07:19:58 AM UTC 24
Peak memory	227512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810053842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.2810053842 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/49.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/49.kmac_lc_escalation.3553130576
Short name	T657
Test name
Test status
Simulation time	3011714201 ps
CPU time	17.75 seconds
Started	Aug 29 07:19:54 AM UTC 24
Finished	Aug 29 07:20:13 AM UTC 24
Peak memory	244360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553130576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.3553130576 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/49.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/49.kmac_long_msg_and_output.1938500150
Short name	T720
Test name
Test status
Simulation time	407976322979 ps
CPU time	5216.82 seconds
Started	Aug 29 07:18:47 AM UTC 24
Finished	Aug 29 08:46:44 AM UTC 24
Peak memory	4428180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938500150 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_and_output.1938500150 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/49.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/49.kmac_sideload.2745714169
Short name	T678
Test name
Test status
Simulation time	6502505377 ps
CPU time	297.95 seconds
Started	Aug 29 07:19:17 AM UTC 24
Finished	Aug 29 07:24:20 AM UTC 24
Peak memory	397624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745714169 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.2745714169 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/49.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/49.kmac_smoke.496728209
Short name	T647
Test name
Test status
Simulation time	1309827577 ps
CPU time	36.72 seconds
Started	Aug 29 07:18:46 AM UTC 24
Finished	Aug 29 07:19:24 AM UTC 24
Peak memory	235712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496728209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.496728209 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/49.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/49.kmac_stress_all.2921025931
Short name	T660
Test name
Test status
Simulation time	2423174818 ps
CPU time	31.36 seconds
Started	Aug 29 07:19:59 AM UTC 24
Finished	Aug 29 07:20:32 AM UTC 24
Peak memory	245848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921025931 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.2921025931 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/49.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/5.kmac_alert_test.3789381496
Short name	T212
Test name
Test status
Simulation time	20736533 ps
CPU time	1.34 seconds
Started	Aug 29 06:21:18 AM UTC 24
Finished	Aug 29 06:21:20 AM UTC 24
Peak memory	226168 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789381496 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.3789381496 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/5.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/5.kmac_app.3140402778
Short name	T229
Test name
Test status
Simulation time	97381045712 ps
CPU time	238.78 seconds
Started	Aug 29 06:20:43 AM UTC 24
Finished	Aug 29 06:24:45 AM UTC 24
Peak memory	405824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140402778 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.3140402778 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/5.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/5.kmac_app_with_partial_data.406339108
Short name	T128
Test name
Test status
Simulation time	2334675831 ps
CPU time	14.3 seconds
Started	Aug 29 06:20:57 AM UTC 24
Finished	Aug 29 06:21:13 AM UTC 24
Peak memory	235892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406339108 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.406339108 +enable_masking= 1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/5.kmac_app_with_partial_data/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/5.kmac_burst_write.3347746812
Short name	T323
Test name
Test status
Simulation time	16993082180 ps
CPU time	905.13 seconds
Started	Aug 29 06:20:37 AM UTC 24
Finished	Aug 29 06:35:53 AM UTC 24
Peak memory	258424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347746812 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.3347746812 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/5.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/5.kmac_edn_timeout_error.54348300
Short name	T100
Test name
Test status
Simulation time	103017746 ps
CPU time	1.68 seconds
Started	Aug 29 06:21:11 AM UTC 24
Finished	Aug 29 06:21:14 AM UTC 24
Peak memory	227456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54348300 -assert nopostproc +UVM_TESTNAME=kmac_base_test + UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/k mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.54348300 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/5.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_mode_error.2362934054
Short name	T107
Test name
Test status
Simulation time	111830576 ps
CPU time	1.56 seconds
Started	Aug 29 06:21:14 AM UTC 24
Finished	Aug 29 06:21:16 AM UTC 24
Peak memory	224424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362934054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.2362934054 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/5.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_ready_error.4066095888
Short name	T83
Test name
Test status
Simulation time	2386415139 ps
CPU time	40.56 seconds
Started	Aug 29 06:21:15 AM UTC 24
Finished	Aug 29 06:21:57 AM UTC 24
Peak memory	231876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066095888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.4066095888 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/5.kmac_entropy_ready_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_refresh.2118122563
Short name	T104
Test name
Test status
Simulation time	2032124999 ps
CPU time	37.1 seconds
Started	Aug 29 06:20:58 AM UTC 24
Finished	Aug 29 06:21:37 AM UTC 24
Peak memory	268528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118122563 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.2118122563 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/5.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/5.kmac_key_error.2168513907
Short name	T196
Test name
Test status
Simulation time	10296794510 ps
CPU time	10.15 seconds
Started	Aug 29 06:21:04 AM UTC 24
Finished	Aug 29 06:21:16 AM UTC 24
Peak memory	227668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168513907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.2168513907 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/5.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/5.kmac_long_msg_and_output.2096804097
Short name	T219
Test name
Test status
Simulation time	9584614434 ps
CPU time	204.04 seconds
Started	Aug 29 06:20:27 AM UTC 24
Finished	Aug 29 06:23:54 AM UTC 24
Peak memory	340188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096804097 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and_output.2096804097 +enable_masking =1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/5.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/5.kmac_sideload.777002342
Short name	T244
Test name
Test status
Simulation time	4470999120 ps
CPU time	343.86 seconds
Started	Aug 29 06:20:29 AM UTC 24
Finished	Aug 29 06:26:17 AM UTC 24
Peak memory	352496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777002342 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.777002342 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/5.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/5.kmac_smoke.4282949703
Short name	T202
Test name
Test status
Simulation time	3201863929 ps
CPU time	30.85 seconds
Started	Aug 29 06:20:26 AM UTC 24
Finished	Aug 29 06:20:58 AM UTC 24
Peak memory	233936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282949703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.4282949703 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/5.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/5.kmac_stress_all_with_rand_reset.4246314720
Short name	T67
Test name
Test status
Simulation time	1732019392 ps
CPU time	98.73 seconds
Started	Aug 29 06:21:17 AM UTC 24
Finished	Aug 29 06:22:58 AM UTC 24
Peak memory	278824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4246314720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all_with_r and_reset.4246314720 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/6.kmac_alert_test.2010685038
Short name	T87
Test name
Test status
Simulation time	46234266 ps
CPU time	1.25 seconds
Started	Aug 29 06:22:12 AM UTC 24
Finished	Aug 29 06:22:14 AM UTC 24
Peak memory	226288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010685038 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.2010685038 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/6.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/6.kmac_app.2663940086
Short name	T214
Test name
Test status
Simulation time	6786346722 ps
CPU time	112.05 seconds
Started	Aug 29 06:21:31 AM UTC 24
Finished	Aug 29 06:23:26 AM UTC 24
Peak memory	293176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663940086 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.2663940086 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/6.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/6.kmac_app_with_partial_data.2252918367
Short name	T146
Test name
Test status
Simulation time	14052897221 ps
CPU time	75.86 seconds
Started	Aug 29 06:21:32 AM UTC 24
Finished	Aug 29 06:22:50 AM UTC 24
Peak memory	291112 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252918367 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.2252918367 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/6.kmac_app_with_partial_data/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/6.kmac_burst_write.2924060660
Short name	T361
Test name
Test status
Simulation time	25451409357 ps
CPU time	1236.36 seconds
Started	Aug 29 06:21:28 AM UTC 24
Finished	Aug 29 06:42:19 AM UTC 24
Peak memory	266480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924060660 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.2924060660 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/6.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/6.kmac_edn_timeout_error.4239784944
Short name	T85
Test name
Test status
Simulation time	25371315 ps
CPU time	1.09 seconds
Started	Aug 29 06:21:58 AM UTC 24
Finished	Aug 29 06:22:00 AM UTC 24
Peak memory	225028 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239784944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.4239784944 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/6.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_mode_error.112648922
Short name	T86
Test name
Test status
Simulation time	17110331 ps
CPU time	1.3 seconds
Started	Aug 29 06:21:59 AM UTC 24
Finished	Aug 29 06:22:01 AM UTC 24
Peak memory	227440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112648922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.112648922 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/6.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_ready_error.3974342719
Short name	T148
Test name
Test status
Simulation time	18524924221 ps
CPU time	55.08 seconds
Started	Aug 29 06:22:01 AM UTC 24
Finished	Aug 29 06:22:58 AM UTC 24
Peak memory	235828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974342719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.3974342719 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/6.kmac_entropy_ready_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_refresh.177977359
Short name	T238
Test name
Test status
Simulation time	38406548912 ps
CPU time	254.36 seconds
Started	Aug 29 06:21:39 AM UTC 24
Finished	Aug 29 06:25:57 AM UTC 24
Peak memory	440600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177977359 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.177977359 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/6.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/6.kmac_error.28566290
Short name	T39
Test name
Test status
Simulation time	26292224898 ps
CPU time	432.29 seconds
Started	Aug 29 06:21:47 AM UTC 24
Finished	Aug 29 06:29:05 AM UTC 24
Peak memory	370944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28566290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.28566290 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/6.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/6.kmac_key_error.2307226572
Short name	T84
Test name
Test status
Simulation time	605268412 ps
CPU time	5.19 seconds
Started	Aug 29 06:21:52 AM UTC 24
Finished	Aug 29 06:21:58 AM UTC 24
Peak memory	229636 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307226572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.2307226572 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/6.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/6.kmac_lc_escalation.3009878944
Short name	T47
Test name
Test status
Simulation time	44562358 ps
CPU time	2.24 seconds
Started	Aug 29 06:22:02 AM UTC 24
Finished	Aug 29 06:22:05 AM UTC 24
Peak memory	234256 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009878944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.3009878944 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/6.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/6.kmac_long_msg_and_output.2189904954
Short name	T413
Test name
Test status
Simulation time	93773582176 ps
CPU time	1734.6 seconds
Started	Aug 29 06:21:21 AM UTC 24
Finished	Aug 29 06:50:36 AM UTC 24
Peak memory	1980720 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189904954 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_and_output.2189904954 +enable_masking =1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/6.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/6.kmac_mubi.3442596006
Short name	T33
Test name
Test status
Simulation time	249746523 ps
CPU time	6.48 seconds
Started	Aug 29 06:21:44 AM UTC 24
Finished	Aug 29 06:21:51 AM UTC 24
Peak memory	246336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442596006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.3442596006 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/6.kmac_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/6.kmac_sideload.3603892852
Short name	T217
Test name
Test status
Simulation time	3240363513 ps
CPU time	125.05 seconds
Started	Aug 29 06:21:23 AM UTC 24
Finished	Aug 29 06:23:31 AM UTC 24
Peak memory	317672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603892852 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.3603892852 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/6.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/6.kmac_smoke.780742987
Short name	T213
Test name
Test status
Simulation time	351120781 ps
CPU time	6.03 seconds
Started	Aug 29 06:21:20 AM UTC 24
Finished	Aug 29 06:21:27 AM UTC 24
Peak memory	235784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780742987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.780742987 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/6.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/6.kmac_stress_all.1363651579
Short name	T707
Test name
Test status
Simulation time	272525293730 ps
CPU time	5171.82 seconds
Started	Aug 29 06:22:06 AM UTC 24
Finished	Aug 29 07:49:19 AM UTC 24
Peak memory	1565416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363651579 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.1363651579 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/6.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/6.kmac_stress_all_with_rand_reset.2366030978
Short name	T68
Test name
Test status
Simulation time	24542392843 ps
CPU time	174.32 seconds
Started	Aug 29 06:22:10 AM UTC 24
Finished	Aug 29 06:25:08 AM UTC 24
Peak memory	285440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2366030978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all_with_r and_reset.2366030978 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/7.kmac_alert_test.1249605279
Short name	T216
Test name
Test status
Simulation time	43327857 ps
CPU time	1.24 seconds
Started	Aug 29 06:23:28 AM UTC 24
Finished	Aug 29 06:23:30 AM UTC 24
Peak memory	226228 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249605279 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.1249605279 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/7.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/7.kmac_app.2150905683
Short name	T267
Test name
Test status
Simulation time	17961915824 ps
CPU time	404.49 seconds
Started	Aug 29 06:22:41 AM UTC 24
Finished	Aug 29 06:29:30 AM UTC 24
Peak memory	542948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150905683 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.2150905683 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/7.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/7.kmac_app_with_partial_data.2694747032
Short name	T254
Test name
Test status
Simulation time	4665241587 ps
CPU time	295.98 seconds
Started	Aug 29 06:22:51 AM UTC 24
Finished	Aug 29 06:27:51 AM UTC 24
Peak memory	334084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694747032 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.2694747032 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/7.kmac_app_with_partial_data/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/7.kmac_burst_write.3334127214
Short name	T352
Test name
Test status
Simulation time	19806378525 ps
CPU time	990.17 seconds
Started	Aug 29 06:22:33 AM UTC 24
Finished	Aug 29 06:39:15 AM UTC 24
Peak memory	260336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334127214 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.3334127214 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/7.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/7.kmac_edn_timeout_error.4192672666
Short name	T215
Test name
Test status
Simulation time	253055579 ps
CPU time	13.76 seconds
Started	Aug 29 06:23:11 AM UTC 24
Finished	Aug 29 06:23:26 AM UTC 24
Peak memory	235484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192672666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.4192672666 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/7.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_mode_error.4051052175
Short name	T151
Test name
Test status
Simulation time	55327011 ps
CPU time	1.43 seconds
Started	Aug 29 06:23:12 AM UTC 24
Finished	Aug 29 06:23:15 AM UTC 24
Peak memory	224424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051052175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.4051052175 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/7.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_ready_error.3954101043
Short name	T220
Test name
Test status
Simulation time	13969596386 ps
CPU time	37.84 seconds
Started	Aug 29 06:23:15 AM UTC 24
Finished	Aug 29 06:23:54 AM UTC 24
Peak memory	231856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954101043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.3954101043 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/7.kmac_entropy_ready_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_refresh.564316872
Short name	T180
Test name
Test status
Simulation time	13691497304 ps
CPU time	393.9 seconds
Started	Aug 29 06:22:58 AM UTC 24
Finished	Aug 29 06:29:37 AM UTC 24
Peak memory	502088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564316872 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.564316872 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/7.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/7.kmac_error.406834770
Short name	T27
Test name
Test status
Simulation time	7282311196 ps
CPU time	290.09 seconds
Started	Aug 29 06:22:59 AM UTC 24
Finished	Aug 29 06:27:54 AM UTC 24
Peak memory	432356 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406834770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.406834770 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/7.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/7.kmac_key_error.2047055210
Short name	T150
Test name
Test status
Simulation time	537041499 ps
CPU time	7.76 seconds
Started	Aug 29 06:23:01 AM UTC 24
Finished	Aug 29 06:23:10 AM UTC 24
Peak memory	227524 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047055210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.2047055210 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/7.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/7.kmac_lc_escalation.1080021903
Short name	T40
Test name
Test status
Simulation time	57164459 ps
CPU time	1.8 seconds
Started	Aug 29 06:23:22 AM UTC 24
Finished	Aug 29 06:23:25 AM UTC 24
Peak memory	231340 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080021903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.1080021903 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/7.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/7.kmac_long_msg_and_output.230567273
Short name	T672
Test name
Test status
Simulation time	294240747366 ps
CPU time	3587.72 seconds
Started	Aug 29 06:22:15 AM UTC 24
Finished	Aug 29 07:22:43 AM UTC 24
Peak memory	3778864 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230567273 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_and_output.230567273 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/7.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/7.kmac_mubi.921444884
Short name	T78
Test name
Test status
Simulation time	946183922 ps
CPU time	30.54 seconds
Started	Aug 29 06:22:59 AM UTC 24
Finished	Aug 29 06:23:31 AM UTC 24
Peak memory	250488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921444884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.921444884 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/7.kmac_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/7.kmac_sideload.1515480355
Short name	T234
Test name
Test status
Simulation time	7002921651 ps
CPU time	173.74 seconds
Started	Aug 29 06:22:19 AM UTC 24
Finished	Aug 29 06:25:17 AM UTC 24
Peak memory	282880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515480355 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.1515480355 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/7.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/7.kmac_smoke.1335558552
Short name	T221
Test name
Test status
Simulation time	20104605603 ps
CPU time	100.1 seconds
Started	Aug 29 06:22:13 AM UTC 24
Finished	Aug 29 06:23:56 AM UTC 24
Peak memory	233992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335558552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.1335558552 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/7.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/7.kmac_stress_all.1122277521
Short name	T427
Test name
Test status
Simulation time	185818703362 ps
CPU time	1727.58 seconds
Started	Aug 29 06:23:26 AM UTC 24
Finished	Aug 29 06:52:35 AM UTC 24
Peak memory	1331852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122277521 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.1122277521 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/7.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/8.kmac_alert_test.2255307592
Short name	T225
Test name
Test status
Simulation time	53540952 ps
CPU time	1.34 seconds
Started	Aug 29 06:24:17 AM UTC 24
Finished	Aug 29 06:24:19 AM UTC 24
Peak memory	227556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255307592 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.2255307592 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/8.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/8.kmac_app.4198453621
Short name	T243
Test name
Test status
Simulation time	32586504244 ps
CPU time	155.07 seconds
Started	Aug 29 06:23:36 AM UTC 24
Finished	Aug 29 06:26:14 AM UTC 24
Peak memory	311616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198453621 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.4198453621 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/8.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/8.kmac_app_with_partial_data.1370147532
Short name	T230
Test name
Test status
Simulation time	6160172821 ps
CPU time	71.59 seconds
Started	Aug 29 06:23:43 AM UTC 24
Finished	Aug 29 06:24:57 AM UTC 24
Peak memory	272688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370147532 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.1370147532 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/8.kmac_app_with_partial_data/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/8.kmac_burst_write.3328649763
Short name	T159
Test name
Test status
Simulation time	16291810220 ps
CPU time	392.32 seconds
Started	Aug 29 06:23:36 AM UTC 24
Finished	Aug 29 06:30:14 AM UTC 24
Peak memory	243952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328649763 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.3328649763 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/8.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/8.kmac_edn_timeout_error.717916434
Short name	T227
Test name
Test status
Simulation time	4313610206 ps
CPU time	28.63 seconds
Started	Aug 29 06:24:01 AM UTC 24
Finished	Aug 29 06:24:30 AM UTC 24
Peak memory	244576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717916434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.717916434 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/8.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_mode_error.925060267
Short name	T223
Test name
Test status
Simulation time	22312354 ps
CPU time	1.24 seconds
Started	Aug 29 06:24:03 AM UTC 24
Finished	Aug 29 06:24:05 AM UTC 24
Peak memory	227440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925060267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.925060267 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/8.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_ready_error.2842690390
Short name	T228
Test name
Test status
Simulation time	2553343711 ps
CPU time	38.27 seconds
Started	Aug 29 06:24:06 AM UTC 24
Finished	Aug 29 06:24:45 AM UTC 24
Peak memory	231984 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842690390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.2842690390 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/8.kmac_entropy_ready_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_refresh.1039942499
Short name	T284
Test name
Test status
Simulation time	10149901012 ps
CPU time	386.64 seconds
Started	Aug 29 06:23:50 AM UTC 24
Finished	Aug 29 06:30:22 AM UTC 24
Peak memory	348468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039942499 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.1039942499 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/8.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/8.kmac_error.2384566421
Short name	T172
Test name
Test status
Simulation time	9624699807 ps
CPU time	284.73 seconds
Started	Aug 29 06:23:55 AM UTC 24
Finished	Aug 29 06:28:44 AM UTC 24
Peak memory	440568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384566421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.2384566421 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/8.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/8.kmac_key_error.2005933049
Short name	T222
Test name
Test status
Simulation time	52488197 ps
CPU time	1.97 seconds
Started	Aug 29 06:23:56 AM UTC 24
Finished	Aug 29 06:23:59 AM UTC 24
Peak memory	227524 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005933049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.2005933049 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/8.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/8.kmac_lc_escalation.3904273659
Short name	T70
Test name
Test status
Simulation time	143479223 ps
CPU time	1.95 seconds
Started	Aug 29 06:24:07 AM UTC 24
Finished	Aug 29 06:24:10 AM UTC 24
Peak memory	231340 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904273659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.3904273659 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/8.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/8.kmac_long_msg_and_output.3980590414
Short name	T540
Test name
Test status
Simulation time	196924454678 ps
CPU time	2511.35 seconds
Started	Aug 29 06:23:32 AM UTC 24
Finished	Aug 29 07:05:55 AM UTC 24
Peak memory	2443576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980590414 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_and_output.3980590414 +enable_masking =1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/8.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/8.kmac_mubi.2918693748
Short name	T304
Test name
Test status
Simulation time	19105940822 ps
CPU time	592.09 seconds
Started	Aug 29 06:23:55 AM UTC 24
Finished	Aug 29 06:33:55 AM UTC 24
Peak memory	567436 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918693748 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.2918693748 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/8.kmac_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/8.kmac_sideload.2298494588
Short name	T272
Test name
Test status
Simulation time	4891880809 ps
CPU time	363.96 seconds
Started	Aug 29 06:23:32 AM UTC 24
Finished	Aug 29 06:29:41 AM UTC 24
Peak memory	368948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298494588 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.2298494588 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/8.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/8.kmac_smoke.1968266156
Short name	T206
Test name
Test status
Simulation time	1367871225 ps
CPU time	29.38 seconds
Started	Aug 29 06:23:31 AM UTC 24
Finished	Aug 29 06:24:01 AM UTC 24
Peak memory	235764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968266156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.1968266156 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/8.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/8.kmac_stress_all.3714138448
Short name	T539
Test name
Test status
Simulation time	145815397859 ps
CPU time	2465.48 seconds
Started	Aug 29 06:24:11 AM UTC 24
Finished	Aug 29 07:05:44 AM UTC 24
Peak memory	1088132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714138448 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.3714138448 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/8.kmac_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/9.kmac_alert_test.586469622
Short name	T235
Test name
Test status
Simulation time	30481614 ps
CPU time	1.25 seconds
Started	Aug 29 06:25:18 AM UTC 24
Finished	Aug 29 06:25:21 AM UTC 24
Peak memory	224436 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586469622 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.586469622 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/9.kmac_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/9.kmac_app.3941093921
Short name	T251
Test name
Test status
Simulation time	3977005599 ps
CPU time	156.32 seconds
Started	Aug 29 06:24:31 AM UTC 24
Finished	Aug 29 06:27:11 AM UTC 24
Peak memory	313720 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941093921 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.3941093921 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/9.kmac_app/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/9.kmac_app_with_partial_data.3502329090
Short name	T262
Test name
Test status
Simulation time	36488756129 ps
CPU time	231.29 seconds
Started	Aug 29 06:24:32 AM UTC 24
Finished	Aug 29 06:28:27 AM UTC 24
Peak memory	373028 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502329090 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.3502329090 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/9.kmac_app_with_partial_data/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/9.kmac_burst_write.1902816644
Short name	T403
Test name
Test status
Simulation time	261601639887 ps
CPU time	1391.28 seconds
Started	Aug 29 06:24:29 AM UTC 24
Finished	Aug 29 06:47:58 AM UTC 24
Peak memory	264496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902816644 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.1902816644 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/9.kmac_burst_write/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/9.kmac_edn_timeout_error.2060492767
Short name	T233
Test name
Test status
Simulation time	46602836 ps
CPU time	1.92 seconds
Started	Aug 29 06:25:09 AM UTC 24
Finished	Aug 29 06:25:12 AM UTC 24
Peak memory	227512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060492767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.2060492767 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/9.kmac_edn_timeout_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_mode_error.1807470679
Short name	T232
Test name
Test status
Simulation time	34441139 ps
CPU time	1.23 seconds
Started	Aug 29 06:25:09 AM UTC 24
Finished	Aug 29 06:25:11 AM UTC 24
Peak memory	224844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807470679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.1807470679 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/9.kmac_entropy_mode_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_ready_error.1350769157
Short name	T246
Test name
Test status
Simulation time	22758114000 ps
CPU time	77.35 seconds
Started	Aug 29 06:25:12 AM UTC 24
Finished	Aug 29 06:26:31 AM UTC 24
Peak memory	233996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350769157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.1350769157 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/9.kmac_entropy_ready_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_refresh.410158070
Short name	T283
Test name
Test status
Simulation time	27364705585 ps
CPU time	339.16 seconds
Started	Aug 29 06:24:34 AM UTC 24
Finished	Aug 29 06:30:18 AM UTC 24
Peak memory	338152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410158070 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.410158070 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/9.kmac_entropy_refresh/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/9.kmac_error.1096907527
Short name	T316
Test name
Test status
Simulation time	83530844590 ps
CPU time	603.87 seconds
Started	Aug 29 06:24:47 AM UTC 24
Finished	Aug 29 06:34:58 AM UTC 24
Peak memory	676160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096907527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.1096907527 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/9.kmac_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/9.kmac_key_error.2109331263
Short name	T231
Test name
Test status
Simulation time	1932449395 ps
CPU time	9.21 seconds
Started	Aug 29 06:24:58 AM UTC 24
Finished	Aug 29 06:25:08 AM UTC 24
Peak memory	229636 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109331263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.2109331263 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/9.kmac_key_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/9.kmac_lc_escalation.290010714
Short name	T108
Test name
Test status
Simulation time	55680953 ps
CPU time	2.93 seconds
Started	Aug 29 06:25:13 AM UTC 24
Finished	Aug 29 06:25:17 AM UTC 24
Peak memory	231756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290010714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.290010714 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/9.kmac_lc_escalation/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/9.kmac_long_msg_and_output.3780386060
Short name	T571
Test name
Test status
Simulation time	335240006191 ps
CPU time	2657.83 seconds
Started	Aug 29 06:24:26 AM UTC 24
Finished	Aug 29 07:09:14 AM UTC 24
Peak memory	2715896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780386060 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and_output.3780386060 +enable_masking =1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/9.kmac_long_msg_and_output/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/9.kmac_mubi.562106651
Short name	T280
Test name
Test status
Simulation time	9759490995 ps
CPU time	322.35 seconds
Started	Aug 29 06:24:47 AM UTC 24
Finished	Aug 29 06:30:14 AM UTC 24
Peak memory	438876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562106651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.562106651 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/9.kmac_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/9.kmac_sideload.1270776591
Short name	T327
Test name
Test status
Simulation time	92331170314 ps
CPU time	691.88 seconds
Started	Aug 29 06:24:28 AM UTC 24
Finished	Aug 29 06:36:09 AM UTC 24
Peak memory	696636 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270776591 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.1270776591 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/9.kmac_sideload/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/9.kmac_smoke.2113957027
Short name	T236
Test name
Test status
Simulation time	2783128424 ps
CPU time	68.03 seconds
Started	Aug 29 06:24:20 AM UTC 24
Finished	Aug 29 06:25:31 AM UTC 24
Peak memory	231992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113957027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.2113957027 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/9.kmac_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default/9.kmac_stress_all.1570598438
Short name	T469
Test name
Test status
Simulation time	84672820714 ps
CPU time	1907.85 seconds
Started	Aug 29 06:25:16 AM UTC 24
Finished	Aug 29 06:57:28 AM UTC 24
Peak memory	1512072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570598438 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.1570598438 +enable_masking=1 +sw_key_masked=0
Directory	/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/9.kmac_stress_all/latest