Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
168826 |
1 |
|
|
T9 |
2 |
|
T4 |
629 |
|
T5 |
362 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
87450 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
60659 |
1 |
|
|
T9 |
2 |
|
T4 |
618 |
|
T5 |
356 |
seven_bytes |
2921 |
1 |
|
|
T15 |
45 |
|
T16 |
8 |
|
T95 |
34 |
six_bytes |
2858 |
1 |
|
|
T15 |
44 |
|
T16 |
5 |
|
T95 |
28 |
five_bytes |
2950 |
1 |
|
|
T15 |
42 |
|
T16 |
6 |
|
T95 |
29 |
four_bytes |
3012 |
1 |
|
|
T15 |
38 |
|
T16 |
10 |
|
T95 |
40 |
three_bytes |
3022 |
1 |
|
|
T15 |
34 |
|
T16 |
6 |
|
T95 |
27 |
two_bytes |
2956 |
1 |
|
|
T15 |
53 |
|
T16 |
6 |
|
T95 |
33 |
one_byte |
2998 |
1 |
|
|
T15 |
39 |
|
T16 |
2 |
|
T95 |
30 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
165644 |
1 |
|
|
T9 |
2 |
|
T4 |
607 |
|
T5 |
350 |
auto[1] |
3182 |
1 |
|
|
T4 |
22 |
|
T5 |
12 |
|
T6 |
56 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
168826 |
1 |
|
|
T9 |
2 |
|
T4 |
629 |
|
T5 |
362 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
168813 |
1 |
|
|
T9 |
2 |
|
T4 |
629 |
|
T5 |
362 |
auto[1] |
13 |
1 |
|
|
T184 |
1 |
|
T185 |
1 |
|
T34 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1085 |
1 |
|
|
T4 |
11 |
|
T5 |
6 |
|
T6 |
28 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3182 |
1 |
|
|
T4 |
22 |
|
T5 |
12 |
|
T6 |
56 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
168192 |
1 |
|
|
T4 |
669 |
|
T5 |
641 |
|
T11 |
260 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
89069 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
58168 |
1 |
|
|
T4 |
661 |
|
T5 |
631 |
|
T11 |
7 |
seven_bytes |
3000 |
1 |
|
|
T11 |
7 |
|
T13 |
20 |
|
T15 |
15 |
six_bytes |
3016 |
1 |
|
|
T11 |
5 |
|
T13 |
16 |
|
T15 |
21 |
five_bytes |
2996 |
1 |
|
|
T11 |
6 |
|
T13 |
21 |
|
T15 |
26 |
four_bytes |
2946 |
1 |
|
|
T11 |
7 |
|
T13 |
18 |
|
T15 |
16 |
three_bytes |
2985 |
1 |
|
|
T11 |
5 |
|
T13 |
25 |
|
T15 |
25 |
two_bytes |
3032 |
1 |
|
|
T11 |
9 |
|
T13 |
23 |
|
T15 |
24 |
one_byte |
2980 |
1 |
|
|
T11 |
9 |
|
T13 |
24 |
|
T15 |
18 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
164962 |
1 |
|
|
T4 |
653 |
|
T5 |
621 |
|
T11 |
258 |
auto[1] |
3230 |
1 |
|
|
T4 |
16 |
|
T5 |
20 |
|
T11 |
2 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
168192 |
1 |
|
|
T4 |
669 |
|
T5 |
641 |
|
T11 |
260 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
168181 |
1 |
|
|
T4 |
669 |
|
T5 |
640 |
|
T11 |
260 |
auto[1] |
11 |
1 |
|
|
T5 |
1 |
|
T6 |
1 |
|
T184 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1118 |
1 |
|
|
T4 |
8 |
|
T5 |
10 |
|
T13 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3230 |
1 |
|
|
T4 |
16 |
|
T5 |
20 |
|
T11 |
2 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
333999 |
1 |
|
|
T4 |
1165 |
|
T5 |
607 |
|
T19 |
12 |
auto[1] |
492 |
1 |
|
|
T4 |
21 |
|
T5 |
12 |
|
T6 |
45 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
177427 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
114825 |
1 |
|
|
T4 |
1165 |
|
T5 |
607 |
|
T19 |
12 |
seven_bytes |
6020 |
1 |
|
|
T13 |
38 |
|
T15 |
42 |
|
T16 |
15 |
six_bytes |
6134 |
1 |
|
|
T13 |
41 |
|
T15 |
44 |
|
T16 |
10 |
five_bytes |
6107 |
1 |
|
|
T13 |
33 |
|
T15 |
41 |
|
T16 |
9 |
four_bytes |
6018 |
1 |
|
|
T13 |
36 |
|
T15 |
40 |
|
T16 |
13 |
three_bytes |
5972 |
1 |
|
|
T13 |
40 |
|
T15 |
47 |
|
T16 |
16 |
two_bytes |
5936 |
1 |
|
|
T13 |
35 |
|
T15 |
44 |
|
T16 |
16 |
one_byte |
6052 |
1 |
|
|
T13 |
29 |
|
T15 |
55 |
|
T16 |
14 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
328125 |
1 |
|
|
T4 |
1144 |
|
T5 |
595 |
|
T19 |
12 |
auto[1] |
6366 |
1 |
|
|
T4 |
42 |
|
T5 |
24 |
|
T12 |
4 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
334491 |
1 |
|
|
T4 |
1186 |
|
T5 |
619 |
|
T19 |
12 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
334476 |
1 |
|
|
T4 |
1186 |
|
T5 |
619 |
|
T19 |
12 |
auto[1] |
15 |
1 |
|
|
T186 |
1 |
|
T28 |
1 |
|
T187 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2173 |
1 |
|
|
T4 |
21 |
|
T5 |
12 |
|
T12 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6366 |
1 |
|
|
T4 |
42 |
|
T5 |
24 |
|
T12 |
4 |