Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45733088	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

45265263

1

T1

329

T2

295

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	50404232	1			T1	223		T2	177		T3	5
values[0x0]	19659077	1			T1	157		T2	133		T3	4
values[0x1]	20935042	1			T1	190		T2	147		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35159539	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

55838812

1

T1

381

T2

335

T3

8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	284898	1			T17	5		T49	2		T9	1
valid_sources[0x01]	283298	1			T10	2		T17	1		T49	3
valid_sources[0x02]	970446	1			T1	20		T17	2		T49	2
valid_sources[0x03]	281676	1			T47	1		T10	6		T49	5
valid_sources[0x04]	475747	1			T17	4		T49	3		T7	7
valid_sources[0x05]	285662	1			T47	1		T17	2		T9	1
valid_sources[0x06]	287456	1			T1	12		T10	5		T17	1
valid_sources[0x07]	378984	1			T17	4		T49	3		T8	3
valid_sources[0x08]	281852	1			T3	1		T47	1		T10	3
valid_sources[0x09]	285903	1			T49	3		T7	3		T8	8
valid_sources[0x0a]	827550	1			T17	3		T49	6		T7	3
valid_sources[0x0b]	285848	1			T3	1		T47	2		T17	2
valid_sources[0x0c]	287483	1			T49	3		T9	5		T7	5
valid_sources[0x0d]	281180	1			T1	17		T17	2		T49	1
valid_sources[0x0e]	924578	1			T10	1		T49	5		T7	5
valid_sources[0x0f]	399029	1			T47	1		T17	2		T49	6
valid_sources[0x10]	284576	1			T17	2		T49	2		T7	5
valid_sources[0x11]	473600	1			T17	4		T49	3		T7	3
valid_sources[0x12]	484756	1			T17	1		T49	3		T9	2
valid_sources[0x13]	305070	1			T17	2		T49	5		T8	10
valid_sources[0x14]	286860	1			T17	2		T49	6		T7	10
valid_sources[0x15]	475189	1			T1	11		T17	3		T49	3
valid_sources[0x16]	282570	1			T1	2		T47	1		T17	1
valid_sources[0x17]	282743	1			T1	4		T17	5		T49	3
valid_sources[0x18]	282197	1			T1	7		T17	3		T49	3
valid_sources[0x19]	719576	1			T46	1		T47	1		T10	2
valid_sources[0x1a]	282268	1			T47	1		T17	4		T49	2
valid_sources[0x1b]	282533	1			T1	48		T10	1		T17	2
valid_sources[0x1c]	281595	1			T46	1		T17	5		T49	1
valid_sources[0x1d]	288593	1			T1	13		T49	4		T8	6
valid_sources[0x1e]	277599	1			T10	2		T17	3		T49	2
valid_sources[0x1f]	348031	1			T47	1		T10	3		T17	2
valid_sources[0x20]	285476	1			T1	2		T17	2		T49	3
valid_sources[0x21]	283679	1			T17	3		T49	4		T8	8
valid_sources[0x22]	285462	1			T1	1		T17	4		T49	3
valid_sources[0x23]	313998	1			T47	1		T17	1		T49	2
valid_sources[0x24]	365090	1			T47	1		T17	1		T49	3
valid_sources[0x25]	282828	1			T10	2		T49	2		T7	8
valid_sources[0x26]	303070	1			T17	3		T49	5		T9	1
valid_sources[0x27]	282685	1			T47	1		T17	3		T49	1
valid_sources[0x28]	286499	1			T1	5		T47	1		T17	1
valid_sources[0x29]	296048	1			T10	4		T17	1		T49	5
valid_sources[0x2a]	400558	1			T10	2		T17	3		T49	3
valid_sources[0x2b]	283466	1			T47	1		T10	1		T49	2
valid_sources[0x2c]	285884	1			T47	1		T17	2		T49	1
valid_sources[0x2d]	282007	1			T17	1		T49	4		T8	1
valid_sources[0x2e]	283398	1			T10	2		T17	3		T49	1
valid_sources[0x2f]	289787	1			T1	3		T47	2		T10	4
valid_sources[0x30]	282852	1			T49	3		T7	4		T8	4
valid_sources[0x31]	280889	1			T3	1		T17	5		T49	3
valid_sources[0x32]	289788	1			T47	1		T17	2		T49	2
valid_sources[0x33]	280628	1			T1	9		T49	1		T7	8
valid_sources[0x34]	742630	1			T17	3		T49	3		T7	5
valid_sources[0x35]	870516	1			T10	2		T49	2		T8	2
valid_sources[0x36]	279883	1			T1	1		T47	1		T17	1
valid_sources[0x37]	281328	1			T47	1		T10	1		T17	1
valid_sources[0x38]	282995	1			T1	3		T17	4		T49	2
valid_sources[0x39]	481593	1			T17	2		T49	4		T8	5
valid_sources[0x3a]	395876	1			T8	3		T52	4		T44	24
valid_sources[0x3b]	286275	1			T1	3		T47	1		T10	2
valid_sources[0x3c]	288191	1			T47	1		T17	3		T49	9
valid_sources[0x3d]	328849	1			T1	1		T47	1		T17	3
valid_sources[0x3e]	371691	1			T47	1		T17	3		T49	4
valid_sources[0x3f]	537614	1			T17	3		T49	7		T7	10
valid_sources[0x40]	283583	1			T47	1		T10	1		T17	4
valid_sources[0x41]	282606	1			T10	1		T17	1		T49	3
valid_sources[0x42]	285712	1			T1	3		T46	2		T10	1
valid_sources[0x43]	283076	1			T1	1		T10	1		T17	2
valid_sources[0x44]	284105	1			T17	2		T49	4		T9	1
valid_sources[0x45]	284068	1			T47	1		T17	4		T49	3
valid_sources[0x46]	287800	1			T47	1		T10	1		T17	1
valid_sources[0x47]	278444	1			T1	9		T17	2		T49	1
valid_sources[0x48]	412660	1			T47	1		T10	8		T17	6
valid_sources[0x49]	307504	1			T17	6		T49	2		T7	14
valid_sources[0x4a]	287776	1			T49	4		T7	2		T8	5
valid_sources[0x4b]	284923	1			T10	2		T17	2		T49	1
valid_sources[0x4c]	279171	1			T17	6		T49	8		T9	2
valid_sources[0x4d]	286417	1			T17	4		T49	3		T7	13
valid_sources[0x4e]	397339	1			T10	1		T17	2		T49	5
valid_sources[0x4f]	445490	1			T1	3		T17	3		T49	4
valid_sources[0x50]	334622	1			T17	3		T49	3		T7	8
valid_sources[0x51]	284211	1			T17	3		T49	2		T50	1
valid_sources[0x52]	286982	1			T17	5		T49	8		T7	2
valid_sources[0x53]	1197667	1			T47	1		T17	3		T49	4
valid_sources[0x54]	287800	1			T10	1		T17	1		T49	1
valid_sources[0x55]	1114385	1			T17	4		T49	4		T50	3
valid_sources[0x56]	488451	1			T1	7		T47	1		T17	5
valid_sources[0x57]	281834	1			T3	2		T10	1		T17	5
valid_sources[0x58]	300204	1			T17	5		T9	2		T7	2
valid_sources[0x59]	282825	1			T47	1		T10	1		T17	5
valid_sources[0x5a]	280015	1			T17	2		T49	5		T8	3
valid_sources[0x5b]	286985	1			T17	5		T49	1		T9	1
valid_sources[0x5c]	355932	1			T10	1		T49	5		T7	3
valid_sources[0x5d]	282097	1			T10	1		T17	4		T49	4
valid_sources[0x5e]	281109	1			T17	3		T49	2		T7	4
valid_sources[0x5f]	283603	1			T10	3		T17	2		T49	4
valid_sources[0x60]	388373	1			T17	3		T49	3		T7	7
valid_sources[0x61]	282600	1			T17	8		T49	4		T9	2
valid_sources[0x62]	279874	1			T17	2		T49	2		T7	1
valid_sources[0x63]	378409	1			T49	4		T7	4		T8	4
valid_sources[0x64]	285633	1			T17	5		T49	5		T7	4
valid_sources[0x65]	284018	1			T1	1		T17	6		T49	5
valid_sources[0x66]	281898	1			T9	1		T7	10		T8	3
valid_sources[0x67]	284543	1			T1	26		T17	5		T49	6
valid_sources[0x68]	291732	1			T1	8		T17	5		T49	4
valid_sources[0x69]	285347	1			T1	17		T17	4		T49	2
valid_sources[0x6a]	288904	1			T10	1		T17	4		T49	2
valid_sources[0x6b]	284761	1			T47	1		T17	4		T49	2
valid_sources[0x6c]	285807	1			T10	2		T17	1		T7	6
valid_sources[0x6d]	427694	1			T17	3		T49	4		T50	14
valid_sources[0x6e]	282864	1			T17	2		T49	5		T8	6
valid_sources[0x6f]	281724	1			T17	1		T49	6		T7	3
valid_sources[0x70]	426958	1			T47	1		T17	4		T49	5
valid_sources[0x71]	285569	1			T10	2		T17	3		T49	1
valid_sources[0x72]	281151	1			T17	4		T49	4		T7	1
valid_sources[0x73]	337980	1			T17	4		T49	5		T50	18
valid_sources[0x74]	284698	1			T1	2		T17	8		T49	2
valid_sources[0x75]	541841	1			T1	16		T17	3		T49	7
valid_sources[0x76]	280802	1			T1	15		T47	1		T17	3
valid_sources[0x77]	285037	1			T17	3		T49	7		T7	14
valid_sources[0x78]	283078	1			T17	8		T49	4		T9	6
valid_sources[0x79]	285318	1			T17	1		T49	4		T9	2
valid_sources[0x7a]	282887	1			T17	4		T49	3		T50	8
valid_sources[0x7b]	317636	1			T17	5		T49	7		T7	2
valid_sources[0x7c]	281001	1			T1	7		T2	457		T47	2
valid_sources[0x7d]	288854	1			T1	20		T47	1		T17	4
valid_sources[0x7e]	304514	1			T47	1		T17	5		T9	4
valid_sources[0x7f]	279512	1			T47	1		T17	2		T49	6
valid_sources[0x80]	358610	1			T10	1		T17	4		T49	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

20339619

1

T1

103

T2

85

T3

2

values[0x0]

all_enables

biggest_size

13119704

1

T1

111

T2

102

T3

2

values[0x1]

all_enables

biggest_size

11805940

1

T1

115

T2

108

T3

2